528 lines
15 KiB
C
528 lines
15 KiB
C
/*
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* ARM IoTKit system control element
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "system control element" which is part of the
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* Arm IoTKit and documented in
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* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
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* Specifically, it implements the "system control register" blocks.
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*/
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "sysemu/runstate.h"
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#include "trace.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "hw/registerfields.h"
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#include "hw/misc/iotkit-sysctl.h"
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#include "hw/qdev-properties.h"
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#include "target/arm/arm-powerctl.h"
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#include "target/arm/cpu.h"
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REG32(SECDBGSTAT, 0x0)
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REG32(SECDBGSET, 0x4)
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REG32(SECDBGCLR, 0x8)
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REG32(SCSECCTRL, 0xc)
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REG32(FCLK_DIV, 0x10)
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REG32(SYSCLK_DIV, 0x14)
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REG32(CLOCK_FORCE, 0x18)
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REG32(RESET_SYNDROME, 0x100)
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REG32(RESET_MASK, 0x104)
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REG32(SWRESET, 0x108)
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FIELD(SWRESET, SWRESETREQ, 9, 1)
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REG32(GRETREG, 0x10c)
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REG32(INITSVTOR0, 0x110)
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REG32(INITSVTOR1, 0x114)
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REG32(CPUWAIT, 0x118)
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REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */
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REG32(WICCTRL, 0x120)
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REG32(EWCTRL, 0x124)
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REG32(PDCM_PD_SYS_SENSE, 0x200)
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REG32(PDCM_PD_SRAM0_SENSE, 0x20c)
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REG32(PDCM_PD_SRAM1_SENSE, 0x210)
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REG32(PDCM_PD_SRAM2_SENSE, 0x214)
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REG32(PDCM_PD_SRAM3_SENSE, 0x218)
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REG32(PID4, 0xfd0)
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REG32(PID5, 0xfd4)
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REG32(PID6, 0xfd8)
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REG32(PID7, 0xfdc)
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REG32(PID0, 0xfe0)
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REG32(PID1, 0xfe4)
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REG32(PID2, 0xfe8)
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REG32(PID3, 0xfec)
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REG32(CID0, 0xff0)
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REG32(CID1, 0xff4)
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REG32(CID2, 0xff8)
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REG32(CID3, 0xffc)
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/* PID/CID values */
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static const int sysctl_id[] = {
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0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
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0x54, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
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0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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/*
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* Set the initial secure vector table offset address for the core.
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* This will take effect when the CPU next resets.
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*/
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static void set_init_vtor(uint64_t cpuid, uint32_t vtor)
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{
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Object *cpuobj = OBJECT(arm_get_cpu_by_id(cpuid));
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if (cpuobj) {
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if (object_property_find(cpuobj, "init-svtor", NULL)) {
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object_property_set_uint(cpuobj, "init-svtor", vtor, &error_abort);
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}
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}
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}
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static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
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uint64_t r;
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switch (offset) {
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case A_SECDBGSTAT:
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r = s->secure_debug;
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break;
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case A_SCSECCTRL:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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r = s->scsecctrl;
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break;
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case A_FCLK_DIV:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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r = s->fclk_div;
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break;
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case A_SYSCLK_DIV:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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r = s->sysclk_div;
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break;
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case A_CLOCK_FORCE:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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r = s->clock_force;
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break;
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case A_RESET_SYNDROME:
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r = s->reset_syndrome;
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break;
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case A_RESET_MASK:
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r = s->reset_mask;
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break;
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case A_GRETREG:
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r = s->gretreg;
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break;
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case A_INITSVTOR0:
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r = s->initsvtor0;
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break;
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case A_INITSVTOR1:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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r = s->initsvtor1;
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break;
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case A_CPUWAIT:
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r = s->cpuwait;
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break;
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case A_NMI_ENABLE:
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/* In IoTKit this is named BUSWAIT but is marked reserved, R/O, zero */
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if (!s->is_sse200) {
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r = 0;
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break;
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}
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r = s->nmi_enable;
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break;
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case A_WICCTRL:
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r = s->wicctrl;
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break;
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case A_EWCTRL:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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r = s->ewctrl;
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break;
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case A_PDCM_PD_SYS_SENSE:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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r = s->pdcm_pd_sys_sense;
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break;
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case A_PDCM_PD_SRAM0_SENSE:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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r = s->pdcm_pd_sram0_sense;
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break;
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case A_PDCM_PD_SRAM1_SENSE:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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r = s->pdcm_pd_sram1_sense;
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break;
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case A_PDCM_PD_SRAM2_SENSE:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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r = s->pdcm_pd_sram2_sense;
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break;
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case A_PDCM_PD_SRAM3_SENSE:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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r = s->pdcm_pd_sram3_sense;
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break;
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case A_PID4 ... A_CID3:
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r = sysctl_id[(offset - A_PID4) / 4];
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break;
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case A_SECDBGSET:
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case A_SECDBGCLR:
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case A_SWRESET:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IoTKit SysCtl read: read of WO offset %x\n",
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(int)offset);
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r = 0;
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break;
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default:
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bad_offset:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IoTKit SysCtl read: bad offset %x\n", (int)offset);
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r = 0;
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break;
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}
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trace_iotkit_sysctl_read(offset, r, size);
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return r;
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}
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static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
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trace_iotkit_sysctl_write(offset, value, size);
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/*
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* Most of the state here has to do with control of reset and
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* similar kinds of power up -- for instance the guest can ask
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* what the reason for the last reset was, or forbid reset for
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* some causes (like the non-secure watchdog). Most of this is
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* not relevant to QEMU, which doesn't really model anything other
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* than a full power-on reset.
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* We just model the registers as reads-as-written.
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*/
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switch (offset) {
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case A_RESET_SYNDROME:
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SysCtl RESET_SYNDROME unimplemented\n");
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s->reset_syndrome = value;
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break;
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case A_RESET_MASK:
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl RESET_MASK unimplemented\n");
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s->reset_mask = value;
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break;
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case A_GRETREG:
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/*
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* General retention register, which is only reset by a power-on
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* reset. Technically this implementation is complete, since
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* QEMU only supports power-on resets...
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*/
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s->gretreg = value;
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break;
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case A_INITSVTOR0:
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s->initsvtor0 = value;
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set_init_vtor(0, s->initsvtor0);
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break;
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case A_CPUWAIT:
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if ((s->cpuwait & 1) && !(value & 1)) {
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/* Powering up CPU 0 */
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arm_set_cpu_on_and_reset(0);
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}
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if ((s->cpuwait & 2) && !(value & 2)) {
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/* Powering up CPU 1 */
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arm_set_cpu_on_and_reset(1);
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}
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s->cpuwait = value;
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break;
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case A_WICCTRL:
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl WICCTRL unimplemented\n");
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s->wicctrl = value;
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break;
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case A_SECDBGSET:
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/* write-1-to-set */
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SECDBGSET unimplemented\n");
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s->secure_debug |= value;
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break;
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case A_SECDBGCLR:
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/* write-1-to-clear */
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s->secure_debug &= ~value;
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break;
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case A_SWRESET:
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/* One w/o bit to request a reset; all other bits reserved */
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if (value & R_SWRESET_SWRESETREQ_MASK) {
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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}
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break;
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case A_SCSECCTRL:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n");
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s->scsecctrl = value;
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break;
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case A_FCLK_DIV:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n");
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s->fclk_div = value;
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break;
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case A_SYSCLK_DIV:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n");
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s->sysclk_div = value;
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break;
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case A_CLOCK_FORCE:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\n");
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s->clock_force = value;
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break;
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case A_INITSVTOR1:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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s->initsvtor1 = value;
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set_init_vtor(1, s->initsvtor1);
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break;
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case A_EWCTRL:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n");
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s->ewctrl = value;
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break;
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case A_PDCM_PD_SYS_SENSE:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n");
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s->pdcm_pd_sys_sense = value;
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break;
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case A_PDCM_PD_SRAM0_SENSE:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n");
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s->pdcm_pd_sram0_sense = value;
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break;
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case A_PDCM_PD_SRAM1_SENSE:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n");
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s->pdcm_pd_sram1_sense = value;
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break;
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case A_PDCM_PD_SRAM2_SENSE:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n");
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s->pdcm_pd_sram2_sense = value;
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break;
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case A_PDCM_PD_SRAM3_SENSE:
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if (!s->is_sse200) {
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goto bad_offset;
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}
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n");
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s->pdcm_pd_sram3_sense = value;
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break;
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case A_NMI_ENABLE:
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/* In IoTKit this is BUSWAIT: reserved, R/O, zero */
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if (!s->is_sse200) {
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goto ro_offset;
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}
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
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s->nmi_enable = value;
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break;
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case A_SECDBGSTAT:
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case A_PID4 ... A_CID3:
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ro_offset:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IoTKit SysCtl write: write of RO offset %x\n",
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(int)offset);
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break;
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default:
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bad_offset:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IoTKit SysCtl write: bad offset %x\n", (int)offset);
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break;
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}
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}
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static const MemoryRegionOps iotkit_sysctl_ops = {
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.read = iotkit_sysctl_read,
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.write = iotkit_sysctl_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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/* byte/halfword accesses are just zero-padded on reads and writes */
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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};
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static void iotkit_sysctl_reset(DeviceState *dev)
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{
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IoTKitSysCtl *s = IOTKIT_SYSCTL(dev);
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trace_iotkit_sysctl_reset();
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s->secure_debug = 0;
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s->reset_syndrome = 1;
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s->reset_mask = 0;
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s->gretreg = 0;
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s->initsvtor0 = s->initsvtor0_rst;
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s->initsvtor1 = s->initsvtor1_rst;
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s->cpuwait = s->cpuwait_rst;
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s->wicctrl = 0;
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s->scsecctrl = 0;
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s->fclk_div = 0;
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s->sysclk_div = 0;
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s->clock_force = 0;
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s->nmi_enable = 0;
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s->ewctrl = 0;
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s->pdcm_pd_sys_sense = 0x7f;
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s->pdcm_pd_sram0_sense = 0;
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s->pdcm_pd_sram1_sense = 0;
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s->pdcm_pd_sram2_sense = 0;
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s->pdcm_pd_sram3_sense = 0;
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}
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static void iotkit_sysctl_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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IoTKitSysCtl *s = IOTKIT_SYSCTL(obj);
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memory_region_init_io(&s->iomem, obj, &iotkit_sysctl_ops,
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s, "iotkit-sysctl", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void iotkit_sysctl_realize(DeviceState *dev, Error **errp)
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{
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IoTKitSysCtl *s = IOTKIT_SYSCTL(dev);
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/* The top 4 bits of the SYS_VERSION register tell us if we're an SSE-200 */
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if (extract32(s->sys_version, 28, 4) == 2) {
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s->is_sse200 = true;
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}
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}
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static bool sse200_needed(void *opaque)
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{
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IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
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return s->is_sse200;
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}
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static const VMStateDescription iotkit_sysctl_sse200_vmstate = {
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.name = "iotkit-sysctl/sse-200",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = sse200_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(scsecctrl, IoTKitSysCtl),
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VMSTATE_UINT32(fclk_div, IoTKitSysCtl),
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VMSTATE_UINT32(sysclk_div, IoTKitSysCtl),
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VMSTATE_UINT32(clock_force, IoTKitSysCtl),
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VMSTATE_UINT32(initsvtor1, IoTKitSysCtl),
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VMSTATE_UINT32(nmi_enable, IoTKitSysCtl),
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VMSTATE_UINT32(pdcm_pd_sys_sense, IoTKitSysCtl),
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VMSTATE_UINT32(pdcm_pd_sram0_sense, IoTKitSysCtl),
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VMSTATE_UINT32(pdcm_pd_sram1_sense, IoTKitSysCtl),
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VMSTATE_UINT32(pdcm_pd_sram2_sense, IoTKitSysCtl),
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VMSTATE_UINT32(pdcm_pd_sram3_sense, IoTKitSysCtl),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription iotkit_sysctl_vmstate = {
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.name = "iotkit-sysctl",
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.version_id = 1,
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|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(secure_debug, IoTKitSysCtl),
|
|
VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl),
|
|
VMSTATE_UINT32(reset_mask, IoTKitSysCtl),
|
|
VMSTATE_UINT32(gretreg, IoTKitSysCtl),
|
|
VMSTATE_UINT32(initsvtor0, IoTKitSysCtl),
|
|
VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
|
|
VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
.subsections = (const VMStateDescription*[]) {
|
|
&iotkit_sysctl_sse200_vmstate,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
static Property iotkit_sysctl_props[] = {
|
|
DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0),
|
|
DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0),
|
|
DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst,
|
|
0x10000000),
|
|
DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst,
|
|
0x10000000),
|
|
DEFINE_PROP_END_OF_LIST()
|
|
};
|
|
|
|
static void iotkit_sysctl_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->vmsd = &iotkit_sysctl_vmstate;
|
|
dc->reset = iotkit_sysctl_reset;
|
|
device_class_set_props(dc, iotkit_sysctl_props);
|
|
dc->realize = iotkit_sysctl_realize;
|
|
}
|
|
|
|
static const TypeInfo iotkit_sysctl_info = {
|
|
.name = TYPE_IOTKIT_SYSCTL,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(IoTKitSysCtl),
|
|
.instance_init = iotkit_sysctl_init,
|
|
.class_init = iotkit_sysctl_class_init,
|
|
};
|
|
|
|
static void iotkit_sysctl_register_types(void)
|
|
{
|
|
type_register_static(&iotkit_sysctl_info);
|
|
}
|
|
|
|
type_init(iotkit_sysctl_register_types);
|