589 lines
17 KiB
C
589 lines
17 KiB
C
/*
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* QEMU model of the Smartfusion2 Ethernet MAC.
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*
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* Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* Refer to section Ethernet MAC in the document:
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* UG0331: SmartFusion2 Microcontroller Subsystem User Guide
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* Datasheet URL:
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* https://www.microsemi.com/document-portal/cat_view/56661-internal-documents/
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* 56758-soc?lang=en&limit=20&limitstart=220
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "exec/address-spaces.h"
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#include "hw/registerfields.h"
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#include "hw/net/msf2-emac.h"
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#include "hw/net/mii.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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REG32(CFG1, 0x0)
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FIELD(CFG1, RESET, 31, 1)
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FIELD(CFG1, RX_EN, 2, 1)
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FIELD(CFG1, TX_EN, 0, 1)
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FIELD(CFG1, LB_EN, 8, 1)
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REG32(CFG2, 0x4)
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REG32(IFG, 0x8)
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REG32(HALF_DUPLEX, 0xc)
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REG32(MAX_FRAME_LENGTH, 0x10)
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REG32(MII_CMD, 0x24)
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FIELD(MII_CMD, READ, 0, 1)
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REG32(MII_ADDR, 0x28)
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FIELD(MII_ADDR, REGADDR, 0, 5)
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FIELD(MII_ADDR, PHYADDR, 8, 5)
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REG32(MII_CTL, 0x2c)
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REG32(MII_STS, 0x30)
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REG32(STA1, 0x40)
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REG32(STA2, 0x44)
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REG32(FIFO_CFG0, 0x48)
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REG32(FIFO_CFG4, 0x58)
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FIELD(FIFO_CFG4, BCAST, 9, 1)
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FIELD(FIFO_CFG4, MCAST, 8, 1)
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REG32(FIFO_CFG5, 0x5C)
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FIELD(FIFO_CFG5, BCAST, 9, 1)
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FIELD(FIFO_CFG5, MCAST, 8, 1)
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REG32(DMA_TX_CTL, 0x180)
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FIELD(DMA_TX_CTL, EN, 0, 1)
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REG32(DMA_TX_DESC, 0x184)
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REG32(DMA_TX_STATUS, 0x188)
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FIELD(DMA_TX_STATUS, PKTCNT, 16, 8)
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FIELD(DMA_TX_STATUS, UNDERRUN, 1, 1)
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FIELD(DMA_TX_STATUS, PKT_SENT, 0, 1)
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REG32(DMA_RX_CTL, 0x18c)
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FIELD(DMA_RX_CTL, EN, 0, 1)
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REG32(DMA_RX_DESC, 0x190)
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REG32(DMA_RX_STATUS, 0x194)
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FIELD(DMA_RX_STATUS, PKTCNT, 16, 8)
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FIELD(DMA_RX_STATUS, OVERFLOW, 2, 1)
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FIELD(DMA_RX_STATUS, PKT_RCVD, 0, 1)
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REG32(DMA_IRQ_MASK, 0x198)
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REG32(DMA_IRQ, 0x19c)
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#define EMPTY_MASK (1 << 31)
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#define PKT_SIZE 0x7FF
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#define PHYADDR 0x1
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#define MAX_PKT_SIZE 2048
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typedef struct {
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uint32_t pktaddr;
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uint32_t pktsize;
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uint32_t next;
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} EmacDesc;
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static uint32_t emac_get_isr(MSF2EmacState *s)
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{
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uint32_t ier = s->regs[R_DMA_IRQ_MASK];
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uint32_t tx = s->regs[R_DMA_TX_STATUS] & 0xF;
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uint32_t rx = s->regs[R_DMA_RX_STATUS] & 0xF;
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uint32_t isr = (rx << 4) | tx;
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s->regs[R_DMA_IRQ] = ier & isr;
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return s->regs[R_DMA_IRQ];
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}
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static void emac_update_irq(MSF2EmacState *s)
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{
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bool intr = emac_get_isr(s);
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qemu_set_irq(s->irq, intr);
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}
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static void emac_load_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc)
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{
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address_space_read(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d);
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/* Convert from LE into host endianness. */
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d->pktaddr = le32_to_cpu(d->pktaddr);
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d->pktsize = le32_to_cpu(d->pktsize);
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d->next = le32_to_cpu(d->next);
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}
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static void emac_store_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc)
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{
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/* Convert from host endianness into LE. */
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d->pktaddr = cpu_to_le32(d->pktaddr);
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d->pktsize = cpu_to_le32(d->pktsize);
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d->next = cpu_to_le32(d->next);
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address_space_write(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d);
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}
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static void msf2_dma_tx(MSF2EmacState *s)
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{
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NetClientState *nc = qemu_get_queue(s->nic);
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hwaddr desc = s->regs[R_DMA_TX_DESC];
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uint8_t buf[MAX_PKT_SIZE];
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EmacDesc d;
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int size;
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uint8_t pktcnt;
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uint32_t status;
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if (!(s->regs[R_CFG1] & R_CFG1_TX_EN_MASK)) {
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return;
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}
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while (1) {
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emac_load_desc(s, &d, desc);
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if (d.pktsize & EMPTY_MASK) {
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break;
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}
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size = d.pktsize & PKT_SIZE;
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address_space_read(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED,
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buf, size);
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/*
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* This is very basic way to send packets. Ideally there should be
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* a FIFO and packets should be sent out from FIFO only when
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* R_CFG1 bit 0 is set.
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*/
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if (s->regs[R_CFG1] & R_CFG1_LB_EN_MASK) {
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nc->info->receive(nc, buf, size);
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} else {
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qemu_send_packet(nc, buf, size);
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}
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d.pktsize |= EMPTY_MASK;
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emac_store_desc(s, &d, desc);
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/* update sent packets count */
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status = s->regs[R_DMA_TX_STATUS];
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pktcnt = FIELD_EX32(status, DMA_TX_STATUS, PKTCNT);
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pktcnt++;
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s->regs[R_DMA_TX_STATUS] = FIELD_DP32(status, DMA_TX_STATUS,
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PKTCNT, pktcnt);
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s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_PKT_SENT_MASK;
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desc = d.next;
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}
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s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_UNDERRUN_MASK;
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s->regs[R_DMA_TX_CTL] &= ~R_DMA_TX_CTL_EN_MASK;
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}
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static void msf2_phy_update_link(MSF2EmacState *s)
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{
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/* Autonegotiation status mirrors link status. */
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if (qemu_get_queue(s->nic)->link_down) {
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s->phy_regs[MII_BMSR] &= ~(MII_BMSR_AN_COMP |
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MII_BMSR_LINK_ST);
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} else {
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s->phy_regs[MII_BMSR] |= (MII_BMSR_AN_COMP |
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MII_BMSR_LINK_ST);
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}
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}
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static void msf2_phy_reset(MSF2EmacState *s)
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{
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memset(&s->phy_regs[0], 0, sizeof(s->phy_regs));
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s->phy_regs[MII_BMCR] = 0x1140;
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s->phy_regs[MII_BMSR] = 0x7968;
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s->phy_regs[MII_PHYID1] = 0x0022;
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s->phy_regs[MII_PHYID2] = 0x1550;
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s->phy_regs[MII_ANAR] = 0x01E1;
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s->phy_regs[MII_ANLPAR] = 0xCDE1;
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msf2_phy_update_link(s);
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}
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static void write_to_phy(MSF2EmacState *s)
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{
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uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK;
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uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) &
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R_MII_ADDR_REGADDR_MASK;
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uint16_t data = s->regs[R_MII_CTL] & 0xFFFF;
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if (phy_addr != PHYADDR) {
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return;
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}
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switch (reg_addr) {
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case MII_BMCR:
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if (data & MII_BMCR_RESET) {
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/* Phy reset */
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msf2_phy_reset(s);
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data &= ~MII_BMCR_RESET;
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}
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if (data & MII_BMCR_AUTOEN) {
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/* Complete autonegotiation immediately */
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data &= ~MII_BMCR_AUTOEN;
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s->phy_regs[MII_BMSR] |= MII_BMSR_AN_COMP;
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}
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break;
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}
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s->phy_regs[reg_addr] = data;
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}
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static uint16_t read_from_phy(MSF2EmacState *s)
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{
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uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK;
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uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) &
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R_MII_ADDR_REGADDR_MASK;
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if (phy_addr == PHYADDR) {
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return s->phy_regs[reg_addr];
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} else {
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return 0xFFFF;
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}
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}
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static void msf2_emac_do_reset(MSF2EmacState *s)
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{
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memset(&s->regs[0], 0, sizeof(s->regs));
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s->regs[R_CFG1] = 0x80000000;
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s->regs[R_CFG2] = 0x00007000;
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s->regs[R_IFG] = 0x40605060;
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s->regs[R_HALF_DUPLEX] = 0x00A1F037;
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s->regs[R_MAX_FRAME_LENGTH] = 0x00000600;
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s->regs[R_FIFO_CFG5] = 0X3FFFF;
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msf2_phy_reset(s);
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}
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static uint64_t emac_read(void *opaque, hwaddr addr, unsigned int size)
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{
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MSF2EmacState *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_DMA_IRQ:
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r = emac_get_isr(s);
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break;
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default:
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if (addr >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
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addr * 4);
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return r;
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}
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r = s->regs[addr];
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break;
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}
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return r;
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}
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static void emac_write(void *opaque, hwaddr addr, uint64_t val64,
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unsigned int size)
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{
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MSF2EmacState *s = opaque;
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uint32_t value = val64;
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uint32_t enreqbits;
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uint8_t pktcnt;
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addr >>= 2;
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switch (addr) {
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case R_DMA_TX_CTL:
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s->regs[addr] = value;
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if (value & R_DMA_TX_CTL_EN_MASK) {
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msf2_dma_tx(s);
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}
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break;
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case R_DMA_RX_CTL:
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s->regs[addr] = value;
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if (value & R_DMA_RX_CTL_EN_MASK) {
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s->rx_desc = s->regs[R_DMA_RX_DESC];
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qemu_flush_queued_packets(qemu_get_queue(s->nic));
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}
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break;
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case R_CFG1:
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s->regs[addr] = value;
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if (value & R_CFG1_RESET_MASK) {
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msf2_emac_do_reset(s);
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}
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break;
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case R_FIFO_CFG0:
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/*
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* For our implementation, turning on modules is instantaneous,
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* so the states requested via the *ENREQ bits appear in the
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* *ENRPLY bits immediately. Also the reset bits to reset PE-MCXMAC
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* module are not emulated here since it deals with start of frames,
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* inter-packet gap and control frames.
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*/
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enreqbits = extract32(value, 8, 5);
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s->regs[addr] = deposit32(value, 16, 5, enreqbits);
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break;
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case R_DMA_TX_DESC:
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if (value & 0x3) {
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qemu_log_mask(LOG_GUEST_ERROR, "Tx Descriptor address should be"
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" 32 bit aligned\n");
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}
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/* Ignore [1:0] bits */
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s->regs[addr] = value & ~3;
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break;
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case R_DMA_RX_DESC:
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if (value & 0x3) {
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qemu_log_mask(LOG_GUEST_ERROR, "Rx Descriptor address should be"
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" 32 bit aligned\n");
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}
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/* Ignore [1:0] bits */
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s->regs[addr] = value & ~3;
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break;
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case R_DMA_TX_STATUS:
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if (value & R_DMA_TX_STATUS_UNDERRUN_MASK) {
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s->regs[addr] &= ~R_DMA_TX_STATUS_UNDERRUN_MASK;
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}
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if (value & R_DMA_TX_STATUS_PKT_SENT_MASK) {
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pktcnt = FIELD_EX32(s->regs[addr], DMA_TX_STATUS, PKTCNT);
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pktcnt--;
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s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_TX_STATUS,
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PKTCNT, pktcnt);
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if (pktcnt == 0) {
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s->regs[addr] &= ~R_DMA_TX_STATUS_PKT_SENT_MASK;
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}
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}
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break;
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case R_DMA_RX_STATUS:
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if (value & R_DMA_RX_STATUS_OVERFLOW_MASK) {
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s->regs[addr] &= ~R_DMA_RX_STATUS_OVERFLOW_MASK;
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}
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if (value & R_DMA_RX_STATUS_PKT_RCVD_MASK) {
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pktcnt = FIELD_EX32(s->regs[addr], DMA_RX_STATUS, PKTCNT);
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pktcnt--;
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s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_RX_STATUS,
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PKTCNT, pktcnt);
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if (pktcnt == 0) {
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s->regs[addr] &= ~R_DMA_RX_STATUS_PKT_RCVD_MASK;
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}
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}
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break;
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case R_DMA_IRQ:
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break;
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case R_MII_CMD:
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if (value & R_MII_CMD_READ_MASK) {
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s->regs[R_MII_STS] = read_from_phy(s);
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}
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break;
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case R_MII_CTL:
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s->regs[addr] = value;
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write_to_phy(s);
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break;
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case R_STA1:
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s->regs[addr] = value;
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/*
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* R_STA1 [31:24] : octet 1 of mac address
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* R_STA1 [23:16] : octet 2 of mac address
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* R_STA1 [15:8] : octet 3 of mac address
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* R_STA1 [7:0] : octet 4 of mac address
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*/
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stl_be_p(s->mac_addr, value);
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break;
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case R_STA2:
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s->regs[addr] = value;
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/*
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* R_STA2 [31:24] : octet 5 of mac address
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* R_STA2 [23:16] : octet 6 of mac address
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*/
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stw_be_p(s->mac_addr + 4, value >> 16);
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break;
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default:
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if (addr >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
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addr * 4);
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return;
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}
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s->regs[addr] = value;
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break;
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}
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emac_update_irq(s);
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}
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static const MemoryRegionOps emac_ops = {
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.read = emac_read,
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.write = emac_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4
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}
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};
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static bool emac_can_rx(NetClientState *nc)
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{
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MSF2EmacState *s = qemu_get_nic_opaque(nc);
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return (s->regs[R_CFG1] & R_CFG1_RX_EN_MASK) &&
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(s->regs[R_DMA_RX_CTL] & R_DMA_RX_CTL_EN_MASK);
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}
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static bool addr_filter_ok(MSF2EmacState *s, const uint8_t *buf)
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{
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/* The broadcast MAC address: FF:FF:FF:FF:FF:FF */
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const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF };
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bool bcast_en = true;
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bool mcast_en = true;
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if (s->regs[R_FIFO_CFG5] & R_FIFO_CFG5_BCAST_MASK) {
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bcast_en = true; /* Broadcast dont care for drop circuitry */
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} else if (s->regs[R_FIFO_CFG4] & R_FIFO_CFG4_BCAST_MASK) {
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bcast_en = false;
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}
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if (s->regs[R_FIFO_CFG5] & R_FIFO_CFG5_MCAST_MASK) {
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mcast_en = true; /* Multicast dont care for drop circuitry */
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} else if (s->regs[R_FIFO_CFG4] & R_FIFO_CFG4_MCAST_MASK) {
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mcast_en = false;
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}
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if (!memcmp(buf, broadcast_addr, sizeof(broadcast_addr))) {
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return bcast_en;
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}
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if (buf[0] & 1) {
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|
return mcast_en;
|
|
}
|
|
|
|
return !memcmp(buf, s->mac_addr, sizeof(s->mac_addr));
|
|
}
|
|
|
|
static ssize_t emac_rx(NetClientState *nc, const uint8_t *buf, size_t size)
|
|
{
|
|
MSF2EmacState *s = qemu_get_nic_opaque(nc);
|
|
EmacDesc d;
|
|
uint8_t pktcnt;
|
|
uint32_t status;
|
|
|
|
if (size > (s->regs[R_MAX_FRAME_LENGTH] & 0xFFFF)) {
|
|
return size;
|
|
}
|
|
if (!addr_filter_ok(s, buf)) {
|
|
return size;
|
|
}
|
|
|
|
emac_load_desc(s, &d, s->rx_desc);
|
|
|
|
if (d.pktsize & EMPTY_MASK) {
|
|
address_space_write(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED,
|
|
buf, size & PKT_SIZE);
|
|
d.pktsize = size & PKT_SIZE;
|
|
emac_store_desc(s, &d, s->rx_desc);
|
|
/* update received packets count */
|
|
status = s->regs[R_DMA_RX_STATUS];
|
|
pktcnt = FIELD_EX32(status, DMA_RX_STATUS, PKTCNT);
|
|
pktcnt++;
|
|
s->regs[R_DMA_RX_STATUS] = FIELD_DP32(status, DMA_RX_STATUS,
|
|
PKTCNT, pktcnt);
|
|
s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_PKT_RCVD_MASK;
|
|
s->rx_desc = d.next;
|
|
} else {
|
|
s->regs[R_DMA_RX_CTL] &= ~R_DMA_RX_CTL_EN_MASK;
|
|
s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_OVERFLOW_MASK;
|
|
}
|
|
emac_update_irq(s);
|
|
return size;
|
|
}
|
|
|
|
static void msf2_emac_reset(DeviceState *dev)
|
|
{
|
|
MSF2EmacState *s = MSS_EMAC(dev);
|
|
|
|
msf2_emac_do_reset(s);
|
|
}
|
|
|
|
static void emac_set_link(NetClientState *nc)
|
|
{
|
|
MSF2EmacState *s = qemu_get_nic_opaque(nc);
|
|
|
|
msf2_phy_update_link(s);
|
|
}
|
|
|
|
static NetClientInfo net_msf2_emac_info = {
|
|
.type = NET_CLIENT_DRIVER_NIC,
|
|
.size = sizeof(NICState),
|
|
.can_receive = emac_can_rx,
|
|
.receive = emac_rx,
|
|
.link_status_changed = emac_set_link,
|
|
};
|
|
|
|
static void msf2_emac_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
MSF2EmacState *s = MSS_EMAC(dev);
|
|
|
|
if (!s->dma_mr) {
|
|
error_setg(errp, "MSS_EMAC 'ahb-bus' link not set");
|
|
return;
|
|
}
|
|
|
|
address_space_init(&s->dma_as, s->dma_mr, "emac-ahb");
|
|
|
|
qemu_macaddr_default_if_unset(&s->conf.macaddr);
|
|
s->nic = qemu_new_nic(&net_msf2_emac_info, &s->conf,
|
|
object_get_typename(OBJECT(dev)), dev->id, s);
|
|
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
|
|
}
|
|
|
|
static void msf2_emac_init(Object *obj)
|
|
{
|
|
MSF2EmacState *s = MSS_EMAC(obj);
|
|
|
|
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
|
|
|
|
memory_region_init_io(&s->mmio, obj, &emac_ops, s,
|
|
"msf2-emac", R_MAX * 4);
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
|
|
}
|
|
|
|
static Property msf2_emac_properties[] = {
|
|
DEFINE_PROP_LINK("ahb-bus", MSF2EmacState, dma_mr,
|
|
TYPE_MEMORY_REGION, MemoryRegion *),
|
|
DEFINE_NIC_PROPERTIES(MSF2EmacState, conf),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static const VMStateDescription vmstate_msf2_emac = {
|
|
.name = TYPE_MSS_EMAC,
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT8_ARRAY(mac_addr, MSF2EmacState, ETH_ALEN),
|
|
VMSTATE_UINT32(rx_desc, MSF2EmacState),
|
|
VMSTATE_UINT16_ARRAY(phy_regs, MSF2EmacState, PHY_MAX_REGS),
|
|
VMSTATE_UINT32_ARRAY(regs, MSF2EmacState, R_MAX),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void msf2_emac_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = msf2_emac_realize;
|
|
dc->reset = msf2_emac_reset;
|
|
dc->vmsd = &vmstate_msf2_emac;
|
|
device_class_set_props(dc, msf2_emac_properties);
|
|
}
|
|
|
|
static const TypeInfo msf2_emac_info = {
|
|
.name = TYPE_MSS_EMAC,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(MSF2EmacState),
|
|
.instance_init = msf2_emac_init,
|
|
.class_init = msf2_emac_class_init,
|
|
};
|
|
|
|
static void msf2_emac_register_types(void)
|
|
{
|
|
type_register_static(&msf2_emac_info);
|
|
}
|
|
|
|
type_init(msf2_emac_register_types)
|