68 lines
2 KiB
C
68 lines
2 KiB
C
#ifndef HW_PCNET_H
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#define HW_PCNET_H
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#define PCNET_IOPORT_SIZE 0x20
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#define PCNET_PNPMMIO_SIZE 0x20
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#define PCNET_LOOPTEST_CRC 1
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#define PCNET_LOOPTEST_NOCRC 2
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#include "exec/memory.h"
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#include "hw/irq.h"
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/* BUS CONFIGURATION REGISTERS */
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#define BCR_MSRDA 0
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#define BCR_MSWRA 1
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#define BCR_MC 2
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#define BCR_LNKST 4
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#define BCR_LED1 5
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#define BCR_LED2 6
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#define BCR_LED3 7
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#define BCR_FDC 9
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#define BCR_BSBC 18
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#define BCR_EECAS 19
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#define BCR_SWS 20
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#define BCR_PLAT 22
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#define BCR_TMAULOOP(S) !!((S)->bcr[BCR_MC ] & 0x4000)
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#define BCR_APROMWE(S) !!((S)->bcr[BCR_MC ] & 0x0100)
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#define BCR_DWIO(S) !!((S)->bcr[BCR_BSBC] & 0x0080)
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#define BCR_SSIZE32(S) !!((S)->bcr[BCR_SWS ] & 0x0100)
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#define BCR_SWSTYLE(S) ((S)->bcr[BCR_SWS ] & 0x00FF)
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typedef struct PCNetState_st PCNetState;
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struct PCNetState_st {
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NICState *nic;
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NICConf conf;
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QEMUTimer *poll_timer;
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int rap, isr, lnkst;
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uint32_t rdra, tdra;
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uint8_t prom[16];
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uint16_t csr[128];
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uint16_t bcr[32];
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int xmit_pos;
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uint64_t timer;
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MemoryRegion mmio;
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uint8_t buffer[4096];
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qemu_irq irq;
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void (*phys_mem_read)(void *dma_opaque, hwaddr addr,
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uint8_t *buf, int len, int do_bswap);
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void (*phys_mem_write)(void *dma_opaque, hwaddr addr,
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uint8_t *buf, int len, int do_bswap);
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DeviceState *dma_opaque;
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int tx_busy;
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int looptest;
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};
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void pcnet_h_reset(void *opaque);
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void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val);
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uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr);
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void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val);
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uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr);
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uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap);
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ssize_t pcnet_receive(NetClientState *nc, const uint8_t *buf, size_t size_);
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void pcnet_set_link_status(NetClientState *nc);
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void pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info);
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extern const VMStateDescription vmstate_pcnet;
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#endif
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