1098 lines
29 KiB
C
1098 lines
29 KiB
C
/*
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* QEMU model of Xilinx AXI-Ethernet.
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*
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* Copyright (c) 2011 Edgar E. Iglesias.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "net/net.h"
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#include "net/checksum.h"
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#include "hw/hw.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/stream.h"
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#define DPHY(x)
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#define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet"
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#define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream"
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#define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream"
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#define XILINX_AXI_ENET(obj) \
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OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
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#define XILINX_AXI_ENET_DATA_STREAM(obj) \
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OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
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TYPE_XILINX_AXI_ENET_DATA_STREAM)
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#define XILINX_AXI_ENET_CONTROL_STREAM(obj) \
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OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
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TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
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/* Advertisement control register. */
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#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
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#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
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#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
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#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
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#define CONTROL_PAYLOAD_WORDS 5
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#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
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struct PHY {
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uint32_t regs[32];
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int link;
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unsigned int (*read)(struct PHY *phy, unsigned int req);
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void (*write)(struct PHY *phy, unsigned int req,
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unsigned int data);
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};
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static unsigned int tdk_read(struct PHY *phy, unsigned int req)
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{
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int regnum;
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unsigned r = 0;
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regnum = req & 0x1f;
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switch (regnum) {
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case 1:
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if (!phy->link) {
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break;
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}
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/* MR1. */
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/* Speeds and modes. */
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r |= (1 << 13) | (1 << 14);
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r |= (1 << 11) | (1 << 12);
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r |= (1 << 5); /* Autoneg complete. */
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r |= (1 << 3); /* Autoneg able. */
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r |= (1 << 2); /* link. */
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r |= (1 << 1); /* link. */
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break;
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case 5:
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/* Link partner ability.
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We are kind; always agree with whatever best mode
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the guest advertises. */
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r = 1 << 14; /* Success. */
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/* Copy advertised modes. */
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r |= phy->regs[4] & (15 << 5);
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/* Autoneg support. */
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r |= 1;
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break;
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case 17:
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/* Marvell PHY on many xilinx boards. */
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r = 0x8000; /* 1000Mb */
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break;
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case 18:
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{
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/* Diagnostics reg. */
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int duplex = 0;
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int speed_100 = 0;
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if (!phy->link) {
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break;
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}
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/* Are we advertising 100 half or 100 duplex ? */
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speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
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speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
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/* Are we advertising 10 duplex or 100 duplex ? */
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duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
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duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
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r = (speed_100 << 10) | (duplex << 11);
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}
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break;
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default:
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r = phy->regs[regnum];
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break;
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}
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DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum));
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return r;
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}
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static void
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tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
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{
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int regnum;
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regnum = req & 0x1f;
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DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
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switch (regnum) {
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default:
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phy->regs[regnum] = data;
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break;
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}
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/* Unconditionally clear regs[BMCR][BMCR_RESET] and auto-neg */
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phy->regs[0] &= ~0x8200;
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}
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static void
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tdk_init(struct PHY *phy)
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{
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phy->regs[0] = 0x3100;
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/* PHY Id. */
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phy->regs[2] = 0x0300;
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phy->regs[3] = 0xe400;
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/* Autonegotiation advertisement reg. */
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phy->regs[4] = 0x01E1;
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phy->link = 1;
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phy->read = tdk_read;
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phy->write = tdk_write;
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}
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struct MDIOBus {
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/* bus. */
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int mdc;
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int mdio;
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/* decoder. */
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enum {
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PREAMBLE,
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SOF,
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OPC,
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ADDR,
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REQ,
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TURNAROUND,
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DATA
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} state;
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unsigned int drive;
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unsigned int cnt;
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unsigned int addr;
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unsigned int opc;
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unsigned int req;
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unsigned int data;
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struct PHY *devs[32];
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};
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static void
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mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
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{
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bus->devs[addr & 0x1f] = phy;
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}
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#ifdef USE_THIS_DEAD_CODE
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static void
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mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
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{
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bus->devs[addr & 0x1f] = NULL;
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}
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#endif
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static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr,
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unsigned int reg)
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{
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struct PHY *phy;
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uint16_t data;
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phy = bus->devs[addr];
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if (phy && phy->read) {
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data = phy->read(phy, reg);
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} else {
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data = 0xffff;
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}
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DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
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return data;
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}
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static void mdio_write_req(struct MDIOBus *bus, unsigned int addr,
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unsigned int reg, uint16_t data)
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{
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struct PHY *phy;
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DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
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phy = bus->devs[addr];
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if (phy && phy->write) {
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phy->write(phy, reg, data);
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}
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}
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#define DENET(x)
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#define R_RAF (0x000 / 4)
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enum {
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RAF_MCAST_REJ = (1 << 1),
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RAF_BCAST_REJ = (1 << 2),
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RAF_EMCF_EN = (1 << 12),
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RAF_NEWFUNC_EN = (1 << 11)
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};
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#define R_IS (0x00C / 4)
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enum {
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IS_HARD_ACCESS_COMPLETE = 1,
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IS_AUTONEG = (1 << 1),
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IS_RX_COMPLETE = (1 << 2),
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IS_RX_REJECT = (1 << 3),
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IS_TX_COMPLETE = (1 << 5),
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IS_RX_DCM_LOCK = (1 << 6),
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IS_MGM_RDY = (1 << 7),
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IS_PHY_RST_DONE = (1 << 8),
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};
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#define R_IP (0x010 / 4)
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#define R_IE (0x014 / 4)
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#define R_UAWL (0x020 / 4)
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#define R_UAWU (0x024 / 4)
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#define R_PPST (0x030 / 4)
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enum {
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PPST_LINKSTATUS = (1 << 0),
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PPST_PHY_LINKSTATUS = (1 << 7),
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};
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#define R_STATS_RX_BYTESL (0x200 / 4)
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#define R_STATS_RX_BYTESH (0x204 / 4)
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#define R_STATS_TX_BYTESL (0x208 / 4)
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#define R_STATS_TX_BYTESH (0x20C / 4)
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#define R_STATS_RXL (0x290 / 4)
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#define R_STATS_RXH (0x294 / 4)
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#define R_STATS_RX_BCASTL (0x2a0 / 4)
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#define R_STATS_RX_BCASTH (0x2a4 / 4)
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#define R_STATS_RX_MCASTL (0x2a8 / 4)
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#define R_STATS_RX_MCASTH (0x2ac / 4)
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#define R_RCW0 (0x400 / 4)
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#define R_RCW1 (0x404 / 4)
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enum {
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RCW1_VLAN = (1 << 27),
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RCW1_RX = (1 << 28),
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RCW1_FCS = (1 << 29),
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RCW1_JUM = (1 << 30),
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RCW1_RST = (1 << 31),
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};
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#define R_TC (0x408 / 4)
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enum {
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TC_VLAN = (1 << 27),
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TC_TX = (1 << 28),
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TC_FCS = (1 << 29),
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TC_JUM = (1 << 30),
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TC_RST = (1 << 31),
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};
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#define R_EMMC (0x410 / 4)
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enum {
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EMMC_LINKSPEED_10MB = (0 << 30),
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EMMC_LINKSPEED_100MB = (1 << 30),
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EMMC_LINKSPEED_1000MB = (2 << 30),
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};
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#define R_PHYC (0x414 / 4)
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#define R_MC (0x500 / 4)
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#define MC_EN (1 << 6)
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#define R_MCR (0x504 / 4)
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#define R_MWD (0x508 / 4)
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#define R_MRD (0x50c / 4)
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#define R_MIS (0x600 / 4)
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#define R_MIP (0x620 / 4)
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#define R_MIE (0x640 / 4)
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#define R_MIC (0x640 / 4)
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#define R_UAW0 (0x700 / 4)
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#define R_UAW1 (0x704 / 4)
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#define R_FMI (0x708 / 4)
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#define R_AF0 (0x710 / 4)
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#define R_AF1 (0x714 / 4)
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#define R_MAX (0x34 / 4)
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/* Indirect registers. */
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struct TEMAC {
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struct MDIOBus mdio_bus;
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struct PHY phy;
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void *parent;
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};
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typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
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typedef struct XilinxAXIEnet XilinxAXIEnet;
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struct XilinxAXIEnetStreamSlave {
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Object parent;
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struct XilinxAXIEnet *enet;
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} ;
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struct XilinxAXIEnet {
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SysBusDevice busdev;
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MemoryRegion iomem;
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qemu_irq irq;
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StreamSlave *tx_data_dev;
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StreamSlave *tx_control_dev;
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XilinxAXIEnetStreamSlave rx_data_dev;
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XilinxAXIEnetStreamSlave rx_control_dev;
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NICState *nic;
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NICConf conf;
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uint32_t c_rxmem;
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uint32_t c_txmem;
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uint32_t c_phyaddr;
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struct TEMAC TEMAC;
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/* MII regs. */
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union {
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uint32_t regs[4];
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struct {
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uint32_t mc;
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uint32_t mcr;
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uint32_t mwd;
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uint32_t mrd;
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};
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} mii;
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struct {
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uint64_t rx_bytes;
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uint64_t tx_bytes;
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uint64_t rx;
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uint64_t rx_bcast;
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uint64_t rx_mcast;
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} stats;
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/* Receive configuration words. */
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uint32_t rcw[2];
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/* Transmit config. */
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uint32_t tc;
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uint32_t emmc;
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uint32_t phyc;
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/* Unicast Address Word. */
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uint32_t uaw[2];
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/* Unicast address filter used with extended mcast. */
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uint32_t ext_uaw[2];
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uint32_t fmi;
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uint32_t regs[R_MAX];
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/* Multicast filter addrs. */
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uint32_t maddr[4][2];
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/* 32K x 1 lookup filter. */
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uint32_t ext_mtable[1024];
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uint32_t hdr[CONTROL_PAYLOAD_WORDS];
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uint8_t *txmem;
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uint32_t txpos;
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uint8_t *rxmem;
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uint32_t rxsize;
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uint32_t rxpos;
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uint8_t rxapp[CONTROL_PAYLOAD_SIZE];
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uint32_t rxappsize;
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/* Whether axienet_eth_rx_notify should flush incoming queue. */
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bool need_flush;
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};
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static void axienet_rx_reset(XilinxAXIEnet *s)
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{
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s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN;
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}
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static void axienet_tx_reset(XilinxAXIEnet *s)
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{
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s->tc = TC_JUM | TC_TX | TC_VLAN;
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s->txpos = 0;
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}
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static inline int axienet_rx_resetting(XilinxAXIEnet *s)
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{
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return s->rcw[1] & RCW1_RST;
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}
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static inline int axienet_rx_enabled(XilinxAXIEnet *s)
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{
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return s->rcw[1] & RCW1_RX;
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}
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static inline int axienet_extmcf_enabled(XilinxAXIEnet *s)
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{
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return !!(s->regs[R_RAF] & RAF_EMCF_EN);
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}
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static inline int axienet_newfunc_enabled(XilinxAXIEnet *s)
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{
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return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN);
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}
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static void xilinx_axienet_reset(DeviceState *d)
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{
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XilinxAXIEnet *s = XILINX_AXI_ENET(d);
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axienet_rx_reset(s);
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axienet_tx_reset(s);
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s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS;
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s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE;
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s->emmc = EMMC_LINKSPEED_100MB;
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}
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static void enet_update_irq(XilinxAXIEnet *s)
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{
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s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE];
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qemu_set_irq(s->irq, !!s->regs[R_IP]);
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}
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static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
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{
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XilinxAXIEnet *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_RCW0:
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case R_RCW1:
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r = s->rcw[addr & 1];
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break;
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case R_TC:
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r = s->tc;
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break;
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case R_EMMC:
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r = s->emmc;
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break;
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case R_PHYC:
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r = s->phyc;
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break;
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case R_MCR:
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r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */
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break;
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case R_STATS_RX_BYTESL:
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case R_STATS_RX_BYTESH:
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r = s->stats.rx_bytes >> (32 * (addr & 1));
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break;
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case R_STATS_TX_BYTESL:
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case R_STATS_TX_BYTESH:
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r = s->stats.tx_bytes >> (32 * (addr & 1));
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break;
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case R_STATS_RXL:
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case R_STATS_RXH:
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r = s->stats.rx >> (32 * (addr & 1));
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break;
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case R_STATS_RX_BCASTL:
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case R_STATS_RX_BCASTH:
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r = s->stats.rx_bcast >> (32 * (addr & 1));
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break;
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case R_STATS_RX_MCASTL:
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case R_STATS_RX_MCASTH:
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r = s->stats.rx_mcast >> (32 * (addr & 1));
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break;
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case R_MC:
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case R_MWD:
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case R_MRD:
|
|
r = s->mii.regs[addr & 3];
|
|
break;
|
|
|
|
case R_UAW0:
|
|
case R_UAW1:
|
|
r = s->uaw[addr & 1];
|
|
break;
|
|
|
|
case R_UAWU:
|
|
case R_UAWL:
|
|
r = s->ext_uaw[addr & 1];
|
|
break;
|
|
|
|
case R_FMI:
|
|
r = s->fmi;
|
|
break;
|
|
|
|
case R_AF0:
|
|
case R_AF1:
|
|
r = s->maddr[s->fmi & 3][addr & 1];
|
|
break;
|
|
|
|
case 0x8000 ... 0x83ff:
|
|
r = s->ext_mtable[addr - 0x8000];
|
|
break;
|
|
|
|
default:
|
|
if (addr < ARRAY_SIZE(s->regs)) {
|
|
r = s->regs[addr];
|
|
}
|
|
DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
|
|
__func__, addr * 4, r));
|
|
break;
|
|
}
|
|
return r;
|
|
}
|
|
|
|
static void enet_write(void *opaque, hwaddr addr,
|
|
uint64_t value, unsigned size)
|
|
{
|
|
XilinxAXIEnet *s = opaque;
|
|
struct TEMAC *t = &s->TEMAC;
|
|
|
|
addr >>= 2;
|
|
switch (addr) {
|
|
case R_RCW0:
|
|
case R_RCW1:
|
|
s->rcw[addr & 1] = value;
|
|
if ((addr & 1) && value & RCW1_RST) {
|
|
axienet_rx_reset(s);
|
|
} else {
|
|
qemu_flush_queued_packets(qemu_get_queue(s->nic));
|
|
}
|
|
break;
|
|
|
|
case R_TC:
|
|
s->tc = value;
|
|
if (value & TC_RST) {
|
|
axienet_tx_reset(s);
|
|
}
|
|
break;
|
|
|
|
case R_EMMC:
|
|
s->emmc = value;
|
|
break;
|
|
|
|
case R_PHYC:
|
|
s->phyc = value;
|
|
break;
|
|
|
|
case R_MC:
|
|
value &= ((1 << 7) - 1);
|
|
|
|
/* Enable the MII. */
|
|
if (value & MC_EN) {
|
|
unsigned int miiclkdiv = value & ((1 << 6) - 1);
|
|
if (!miiclkdiv) {
|
|
qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n");
|
|
}
|
|
}
|
|
s->mii.mc = value;
|
|
break;
|
|
|
|
case R_MCR: {
|
|
unsigned int phyaddr = (value >> 24) & 0x1f;
|
|
unsigned int regaddr = (value >> 16) & 0x1f;
|
|
unsigned int op = (value >> 14) & 3;
|
|
unsigned int initiate = (value >> 11) & 1;
|
|
|
|
if (initiate) {
|
|
if (op == 1) {
|
|
mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd);
|
|
} else if (op == 2) {
|
|
s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr);
|
|
} else {
|
|
qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op);
|
|
}
|
|
}
|
|
s->mii.mcr = value;
|
|
break;
|
|
}
|
|
|
|
case R_MWD:
|
|
case R_MRD:
|
|
s->mii.regs[addr & 3] = value;
|
|
break;
|
|
|
|
|
|
case R_UAW0:
|
|
case R_UAW1:
|
|
s->uaw[addr & 1] = value;
|
|
break;
|
|
|
|
case R_UAWL:
|
|
case R_UAWU:
|
|
s->ext_uaw[addr & 1] = value;
|
|
break;
|
|
|
|
case R_FMI:
|
|
s->fmi = value;
|
|
break;
|
|
|
|
case R_AF0:
|
|
case R_AF1:
|
|
s->maddr[s->fmi & 3][addr & 1] = value;
|
|
break;
|
|
|
|
case R_IS:
|
|
s->regs[addr] &= ~value;
|
|
break;
|
|
|
|
case 0x8000 ... 0x83ff:
|
|
s->ext_mtable[addr - 0x8000] = value;
|
|
break;
|
|
|
|
default:
|
|
DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
|
|
__func__, addr * 4, (unsigned)value));
|
|
if (addr < ARRAY_SIZE(s->regs)) {
|
|
s->regs[addr] = value;
|
|
}
|
|
break;
|
|
}
|
|
enet_update_irq(s);
|
|
}
|
|
|
|
static const MemoryRegionOps enet_ops = {
|
|
.read = enet_read,
|
|
.write = enet_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
};
|
|
|
|
static int eth_can_rx(XilinxAXIEnet *s)
|
|
{
|
|
/* RX enabled? */
|
|
return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s);
|
|
}
|
|
|
|
static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1)
|
|
{
|
|
int match = 1;
|
|
|
|
if (memcmp(buf, &f0, 4)) {
|
|
match = 0;
|
|
}
|
|
|
|
if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) {
|
|
match = 0;
|
|
}
|
|
|
|
return match;
|
|
}
|
|
|
|
static void axienet_eth_rx_notify(void *opaque)
|
|
{
|
|
XilinxAXIEnet *s = XILINX_AXI_ENET(opaque);
|
|
|
|
while (s->rxappsize && stream_can_push(s->tx_control_dev,
|
|
axienet_eth_rx_notify, s)) {
|
|
size_t ret = stream_push(s->tx_control_dev,
|
|
(void *)s->rxapp + CONTROL_PAYLOAD_SIZE
|
|
- s->rxappsize, s->rxappsize, true);
|
|
s->rxappsize -= ret;
|
|
}
|
|
|
|
while (s->rxsize && stream_can_push(s->tx_data_dev,
|
|
axienet_eth_rx_notify, s)) {
|
|
size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos,
|
|
s->rxsize, true);
|
|
s->rxsize -= ret;
|
|
s->rxpos += ret;
|
|
if (!s->rxsize) {
|
|
s->regs[R_IS] |= IS_RX_COMPLETE;
|
|
if (s->need_flush) {
|
|
s->need_flush = false;
|
|
qemu_flush_queued_packets(qemu_get_queue(s->nic));
|
|
}
|
|
}
|
|
}
|
|
enet_update_irq(s);
|
|
}
|
|
|
|
static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
|
|
{
|
|
XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
|
|
static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
|
|
0xff, 0xff, 0xff};
|
|
static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52};
|
|
uint32_t app[CONTROL_PAYLOAD_WORDS] = {0};
|
|
int promisc = s->fmi & (1 << 31);
|
|
int unicast, broadcast, multicast, ip_multicast = 0;
|
|
uint32_t csum32;
|
|
uint16_t csum16;
|
|
int i;
|
|
|
|
DENET(qemu_log("%s: %zd bytes\n", __func__, size));
|
|
|
|
if (!eth_can_rx(s)) {
|
|
s->need_flush = true;
|
|
return 0;
|
|
}
|
|
|
|
unicast = ~buf[0] & 0x1;
|
|
broadcast = memcmp(buf, sa_bcast, 6) == 0;
|
|
multicast = !unicast && !broadcast;
|
|
if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) {
|
|
ip_multicast = 1;
|
|
}
|
|
|
|
/* Jumbo or vlan sizes ? */
|
|
if (!(s->rcw[1] & RCW1_JUM)) {
|
|
if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) {
|
|
return size;
|
|
}
|
|
}
|
|
|
|
/* Basic Address filters. If you want to use the extended filters
|
|
you'll generally have to place the ethernet mac into promiscuous mode
|
|
to avoid the basic filtering from dropping most frames. */
|
|
if (!promisc) {
|
|
if (unicast) {
|
|
if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) {
|
|
return size;
|
|
}
|
|
} else {
|
|
if (broadcast) {
|
|
/* Broadcast. */
|
|
if (s->regs[R_RAF] & RAF_BCAST_REJ) {
|
|
return size;
|
|
}
|
|
} else {
|
|
int drop = 1;
|
|
|
|
/* Multicast. */
|
|
if (s->regs[R_RAF] & RAF_MCAST_REJ) {
|
|
return size;
|
|
}
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) {
|
|
drop = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (drop) {
|
|
return size;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Extended mcast filtering enabled? */
|
|
if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) {
|
|
if (unicast) {
|
|
if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) {
|
|
return size;
|
|
}
|
|
} else {
|
|
if (broadcast) {
|
|
/* Broadcast. ??? */
|
|
if (s->regs[R_RAF] & RAF_BCAST_REJ) {
|
|
return size;
|
|
}
|
|
} else {
|
|
int idx, bit;
|
|
|
|
/* Multicast. */
|
|
if (!memcmp(buf, sa_ipmcast, 3)) {
|
|
return size;
|
|
}
|
|
|
|
idx = (buf[4] & 0x7f) << 8;
|
|
idx |= buf[5];
|
|
|
|
bit = 1 << (idx & 0x1f);
|
|
idx >>= 5;
|
|
|
|
if (!(s->ext_mtable[idx] & bit)) {
|
|
return size;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (size < 12) {
|
|
s->regs[R_IS] |= IS_RX_REJECT;
|
|
enet_update_irq(s);
|
|
return -1;
|
|
}
|
|
|
|
if (size > (s->c_rxmem - 4)) {
|
|
size = s->c_rxmem - 4;
|
|
}
|
|
|
|
memcpy(s->rxmem, buf, size);
|
|
memset(s->rxmem + size, 0, 4); /* Clear the FCS. */
|
|
|
|
if (s->rcw[1] & RCW1_FCS) {
|
|
size += 4; /* fcs is inband. */
|
|
}
|
|
|
|
app[0] = 5 << 28;
|
|
csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14);
|
|
/* Fold it once. */
|
|
csum32 = (csum32 & 0xffff) + (csum32 >> 16);
|
|
/* And twice to get rid of possible carries. */
|
|
csum16 = (csum32 & 0xffff) + (csum32 >> 16);
|
|
app[3] = csum16;
|
|
app[4] = size & 0xffff;
|
|
|
|
s->stats.rx_bytes += size;
|
|
s->stats.rx++;
|
|
if (multicast) {
|
|
s->stats.rx_mcast++;
|
|
app[2] |= 1 | (ip_multicast << 1);
|
|
} else if (broadcast) {
|
|
s->stats.rx_bcast++;
|
|
app[2] |= 1 << 3;
|
|
}
|
|
|
|
/* Good frame. */
|
|
app[2] |= 1 << 6;
|
|
|
|
s->rxsize = size;
|
|
s->rxpos = 0;
|
|
for (i = 0; i < ARRAY_SIZE(app); ++i) {
|
|
app[i] = cpu_to_le32(app[i]);
|
|
}
|
|
s->rxappsize = CONTROL_PAYLOAD_SIZE;
|
|
memcpy(s->rxapp, app, s->rxappsize);
|
|
axienet_eth_rx_notify(s);
|
|
|
|
enet_update_irq(s);
|
|
return size;
|
|
}
|
|
|
|
static size_t
|
|
xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len,
|
|
bool eop)
|
|
{
|
|
int i;
|
|
XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
|
|
XilinxAXIEnet *s = cs->enet;
|
|
|
|
assert(eop);
|
|
if (len != CONTROL_PAYLOAD_SIZE) {
|
|
hw_error("AXI Enet requires %d byte control stream payload\n",
|
|
(int)CONTROL_PAYLOAD_SIZE);
|
|
}
|
|
|
|
memcpy(s->hdr, buf, len);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) {
|
|
s->hdr[i] = le32_to_cpu(s->hdr[i]);
|
|
}
|
|
return len;
|
|
}
|
|
|
|
static size_t
|
|
xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size,
|
|
bool eop)
|
|
{
|
|
XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
|
|
XilinxAXIEnet *s = ds->enet;
|
|
|
|
/* TX enable ? */
|
|
if (!(s->tc & TC_TX)) {
|
|
return size;
|
|
}
|
|
|
|
if (s->txpos + size > s->c_txmem) {
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: Packet larger than txmem\n",
|
|
TYPE_XILINX_AXI_ENET);
|
|
s->txpos = 0;
|
|
return size;
|
|
}
|
|
|
|
if (s->txpos == 0 && eop) {
|
|
/* Fast path single fragment. */
|
|
s->txpos = size;
|
|
} else {
|
|
memcpy(s->txmem + s->txpos, buf, size);
|
|
buf = s->txmem;
|
|
s->txpos += size;
|
|
|
|
if (!eop) {
|
|
return size;
|
|
}
|
|
}
|
|
|
|
/* Jumbo or vlan sizes ? */
|
|
if (!(s->tc & TC_JUM)) {
|
|
if (s->txpos > 1518 && s->txpos <= 1522 && !(s->tc & TC_VLAN)) {
|
|
s->txpos = 0;
|
|
return size;
|
|
}
|
|
}
|
|
|
|
if (s->hdr[0] & 1) {
|
|
unsigned int start_off = s->hdr[1] >> 16;
|
|
unsigned int write_off = s->hdr[1] & 0xffff;
|
|
uint32_t tmp_csum;
|
|
uint16_t csum;
|
|
|
|
tmp_csum = net_checksum_add(s->txpos - start_off,
|
|
buf + start_off);
|
|
/* Accumulate the seed. */
|
|
tmp_csum += s->hdr[2] & 0xffff;
|
|
|
|
/* Fold the 32bit partial checksum. */
|
|
csum = net_checksum_finish(tmp_csum);
|
|
|
|
/* Writeback. */
|
|
buf[write_off] = csum >> 8;
|
|
buf[write_off + 1] = csum & 0xff;
|
|
}
|
|
|
|
qemu_send_packet(qemu_get_queue(s->nic), buf, s->txpos);
|
|
|
|
s->stats.tx_bytes += s->txpos;
|
|
s->regs[R_IS] |= IS_TX_COMPLETE;
|
|
enet_update_irq(s);
|
|
|
|
s->txpos = 0;
|
|
return size;
|
|
}
|
|
|
|
static NetClientInfo net_xilinx_enet_info = {
|
|
.type = NET_CLIENT_DRIVER_NIC,
|
|
.size = sizeof(NICState),
|
|
.receive = eth_rx,
|
|
};
|
|
|
|
static void xilinx_enet_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
|
|
XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
|
|
XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
|
|
&s->rx_control_dev);
|
|
|
|
object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
|
|
(Object **) &ds->enet,
|
|
object_property_allow_set_link,
|
|
OBJ_PROP_LINK_STRONG);
|
|
object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet",
|
|
(Object **) &cs->enet,
|
|
object_property_allow_set_link,
|
|
OBJ_PROP_LINK_STRONG);
|
|
object_property_set_link(OBJECT(ds), "enet", OBJECT(s), &error_abort);
|
|
object_property_set_link(OBJECT(cs), "enet", OBJECT(s), &error_abort);
|
|
|
|
qemu_macaddr_default_if_unset(&s->conf.macaddr);
|
|
s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf,
|
|
object_get_typename(OBJECT(dev)), dev->id, s);
|
|
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
|
|
|
|
tdk_init(&s->TEMAC.phy);
|
|
mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr);
|
|
|
|
s->TEMAC.parent = s;
|
|
|
|
s->rxmem = g_malloc(s->c_rxmem);
|
|
s->txmem = g_malloc(s->c_txmem);
|
|
}
|
|
|
|
static void xilinx_enet_init(Object *obj)
|
|
{
|
|
XilinxAXIEnet *s = XILINX_AXI_ENET(obj);
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
|
|
object_initialize_child(OBJECT(s), "axistream-connected-target",
|
|
&s->rx_data_dev, TYPE_XILINX_AXI_ENET_DATA_STREAM);
|
|
object_initialize_child(OBJECT(s), "axistream-control-connected-target",
|
|
&s->rx_control_dev,
|
|
TYPE_XILINX_AXI_ENET_CONTROL_STREAM);
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000);
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
}
|
|
|
|
static Property xilinx_enet_properties[] = {
|
|
DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7),
|
|
DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000),
|
|
DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000),
|
|
DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf),
|
|
DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet,
|
|
tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *),
|
|
DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet,
|
|
tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void xilinx_enet_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = xilinx_enet_realize;
|
|
device_class_set_props(dc, xilinx_enet_properties);
|
|
dc->reset = xilinx_axienet_reset;
|
|
}
|
|
|
|
static void xilinx_enet_control_stream_class_init(ObjectClass *klass,
|
|
void *data)
|
|
{
|
|
StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
|
|
|
|
ssc->push = xilinx_axienet_control_stream_push;
|
|
}
|
|
|
|
static void xilinx_enet_data_stream_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
|
|
|
|
ssc->push = xilinx_axienet_data_stream_push;
|
|
}
|
|
|
|
static const TypeInfo xilinx_enet_info = {
|
|
.name = TYPE_XILINX_AXI_ENET,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(XilinxAXIEnet),
|
|
.class_init = xilinx_enet_class_init,
|
|
.instance_init = xilinx_enet_init,
|
|
};
|
|
|
|
static const TypeInfo xilinx_enet_data_stream_info = {
|
|
.name = TYPE_XILINX_AXI_ENET_DATA_STREAM,
|
|
.parent = TYPE_OBJECT,
|
|
.instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
|
|
.class_init = xilinx_enet_data_stream_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_STREAM_SLAVE },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static const TypeInfo xilinx_enet_control_stream_info = {
|
|
.name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
|
|
.parent = TYPE_OBJECT,
|
|
.instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
|
|
.class_init = xilinx_enet_control_stream_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_STREAM_SLAVE },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static void xilinx_enet_register_types(void)
|
|
{
|
|
type_register_static(&xilinx_enet_info);
|
|
type_register_static(&xilinx_enet_data_stream_info);
|
|
type_register_static(&xilinx_enet_control_stream_info);
|
|
}
|
|
|
|
type_init(xilinx_enet_register_types)
|