348 lines
8.8 KiB
C
348 lines
8.8 KiB
C
/*
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* QEMU PowerPC PowerNV (POWER8) PHB3 model
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*
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* Copyright (c) 2014-2020, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "hw/pci-host/pnv_phb3_regs.h"
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#include "hw/pci-host/pnv_phb3.h"
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#include "hw/ppc/pnv.h"
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#include "hw/pci/msi.h"
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#include "monitor/monitor.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "sysemu/reset.h"
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static uint64_t phb3_msi_ive_addr(PnvPHB3 *phb, int srcno)
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{
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uint64_t ivtbar = phb->regs[PHB_IVT_BAR >> 3];
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uint64_t phbctl = phb->regs[PHB_CONTROL >> 3];
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if (!(ivtbar & PHB_IVT_BAR_ENABLE)) {
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qemu_log_mask(LOG_GUEST_ERROR, "Failed access to disable IVT BAR !");
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return 0;
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}
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if (srcno >= (ivtbar & PHB_IVT_LENGTH_MASK)) {
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qemu_log_mask(LOG_GUEST_ERROR, "MSI out of bounds (%d vs 0x%"PRIx64")",
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srcno, (uint64_t) (ivtbar & PHB_IVT_LENGTH_MASK));
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return 0;
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}
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ivtbar &= PHB_IVT_BASE_ADDRESS_MASK;
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if (phbctl & PHB_CTRL_IVE_128_BYTES) {
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return ivtbar + 128 * srcno;
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} else {
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return ivtbar + 16 * srcno;
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}
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}
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static bool phb3_msi_read_ive(PnvPHB3 *phb, int srcno, uint64_t *out_ive)
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{
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uint64_t ive_addr, ive;
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ive_addr = phb3_msi_ive_addr(phb, srcno);
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if (!ive_addr) {
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return false;
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}
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if (dma_memory_read(&address_space_memory, ive_addr, &ive, sizeof(ive))) {
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qemu_log_mask(LOG_GUEST_ERROR, "Failed to read IVE at 0x%" PRIx64,
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ive_addr);
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return false;
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}
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*out_ive = be64_to_cpu(ive);
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return true;
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}
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static void phb3_msi_set_p(Phb3MsiState *msi, int srcno, uint8_t gen)
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{
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uint64_t ive_addr;
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uint8_t p = 0x01 | (gen << 1);
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ive_addr = phb3_msi_ive_addr(msi->phb, srcno);
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if (!ive_addr) {
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return;
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}
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if (dma_memory_write(&address_space_memory, ive_addr + 4, &p, 1)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Failed to write IVE (set P) at 0x%" PRIx64, ive_addr);
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}
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}
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static void phb3_msi_set_q(Phb3MsiState *msi, int srcno)
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{
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uint64_t ive_addr;
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uint8_t q = 0x01;
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ive_addr = phb3_msi_ive_addr(msi->phb, srcno);
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if (!ive_addr) {
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return;
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}
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if (dma_memory_write(&address_space_memory, ive_addr + 5, &q, 1)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Failed to write IVE (set Q) at 0x%" PRIx64, ive_addr);
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}
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}
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static void phb3_msi_try_send(Phb3MsiState *msi, int srcno, bool force)
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{
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ICSState *ics = ICS(msi);
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uint64_t ive;
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uint64_t server, prio, pq, gen;
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if (!phb3_msi_read_ive(msi->phb, srcno, &ive)) {
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return;
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}
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server = GETFIELD(IODA2_IVT_SERVER, ive);
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prio = GETFIELD(IODA2_IVT_PRIORITY, ive);
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if (!force) {
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pq = GETFIELD(IODA2_IVT_Q, ive) | (GETFIELD(IODA2_IVT_P, ive) << 1);
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} else {
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pq = 0;
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}
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gen = GETFIELD(IODA2_IVT_GEN, ive);
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/*
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* The low order 2 bits are the link pointer (Type II interrupts).
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* Shift back to get a valid IRQ server.
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*/
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server >>= 2;
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switch (pq) {
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case 0: /* 00 */
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if (prio == 0xff) {
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/* Masked, set Q */
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phb3_msi_set_q(msi, srcno);
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} else {
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/* Enabled, set P and send */
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phb3_msi_set_p(msi, srcno, gen);
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icp_irq(ics, server, srcno + ics->offset, prio);
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}
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break;
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case 2: /* 10 */
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/* Already pending, set Q */
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phb3_msi_set_q(msi, srcno);
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break;
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case 1: /* 01 */
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case 3: /* 11 */
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default:
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/* Just drop stuff if Q already set */
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break;
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}
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}
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static void phb3_msi_set_irq(void *opaque, int srcno, int val)
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{
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Phb3MsiState *msi = PHB3_MSI(opaque);
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if (val) {
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phb3_msi_try_send(msi, srcno, false);
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}
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}
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void pnv_phb3_msi_send(Phb3MsiState *msi, uint64_t addr, uint16_t data,
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int32_t dev_pe)
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{
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ICSState *ics = ICS(msi);
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uint64_t ive;
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uint16_t pe;
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uint32_t src = ((addr >> 4) & 0xffff) | (data & 0x1f);
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if (src >= ics->nr_irqs) {
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qemu_log_mask(LOG_GUEST_ERROR, "MSI %d out of bounds", src);
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return;
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}
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if (dev_pe >= 0) {
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if (!phb3_msi_read_ive(msi->phb, src, &ive)) {
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return;
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}
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pe = GETFIELD(IODA2_IVT_PE, ive);
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if (pe != dev_pe) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"MSI %d send by PE#%d but assigned to PE#%d",
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src, dev_pe, pe);
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return;
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}
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}
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qemu_irq_pulse(msi->qirqs[src]);
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}
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void pnv_phb3_msi_ffi(Phb3MsiState *msi, uint64_t val)
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{
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/* Emit interrupt */
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pnv_phb3_msi_send(msi, val, 0, -1);
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/* Clear FFI lock */
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msi->phb->regs[PHB_FFI_LOCK >> 3] = 0;
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}
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static void phb3_msi_reject(ICSState *ics, uint32_t nr)
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{
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Phb3MsiState *msi = PHB3_MSI(ics);
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unsigned int srcno = nr - ics->offset;
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unsigned int idx = srcno >> 6;
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unsigned int bit = 1ull << (srcno & 0x3f);
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assert(srcno < PHB3_MAX_MSI);
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msi->rba[idx] |= bit;
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msi->rba_sum |= (1u << idx);
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}
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static void phb3_msi_resend(ICSState *ics)
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{
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Phb3MsiState *msi = PHB3_MSI(ics);
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unsigned int i, j;
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if (msi->rba_sum == 0) {
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return;
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}
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for (i = 0; i < 32; i++) {
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if ((msi->rba_sum & (1u << i)) == 0) {
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continue;
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}
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msi->rba_sum &= ~(1u << i);
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for (j = 0; j < 64; j++) {
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if ((msi->rba[i] & (1ull << j)) == 0) {
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continue;
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}
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msi->rba[i] &= ~(1ull << j);
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phb3_msi_try_send(msi, i * 64 + j, true);
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}
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}
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}
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static void phb3_msi_reset(DeviceState *dev)
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{
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Phb3MsiState *msi = PHB3_MSI(dev);
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ICSStateClass *icsc = ICS_GET_CLASS(dev);
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icsc->parent_reset(dev);
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memset(msi->rba, 0, sizeof(msi->rba));
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msi->rba_sum = 0;
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}
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static void phb3_msi_reset_handler(void *dev)
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{
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phb3_msi_reset(dev);
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}
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void pnv_phb3_msi_update_config(Phb3MsiState *msi, uint32_t base,
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uint32_t count)
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{
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ICSState *ics = ICS(msi);
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if (count > PHB3_MAX_MSI) {
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count = PHB3_MAX_MSI;
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}
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ics->nr_irqs = count;
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ics->offset = base;
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}
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static void phb3_msi_realize(DeviceState *dev, Error **errp)
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{
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Phb3MsiState *msi = PHB3_MSI(dev);
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ICSState *ics = ICS(msi);
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ICSStateClass *icsc = ICS_GET_CLASS(ics);
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Error *local_err = NULL;
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assert(msi->phb);
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icsc->parent_realize(dev, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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msi->qirqs = qemu_allocate_irqs(phb3_msi_set_irq, msi, ics->nr_irqs);
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qemu_register_reset(phb3_msi_reset_handler, dev);
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}
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static void phb3_msi_instance_init(Object *obj)
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{
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Phb3MsiState *msi = PHB3_MSI(obj);
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ICSState *ics = ICS(obj);
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object_property_add_link(obj, "phb", TYPE_PNV_PHB3,
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(Object **)&msi->phb,
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object_property_allow_set_link,
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OBJ_PROP_LINK_STRONG);
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/* Will be overriden later */
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ics->offset = 0;
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}
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static void phb3_msi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ICSStateClass *isc = ICS_CLASS(klass);
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device_class_set_parent_realize(dc, phb3_msi_realize,
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&isc->parent_realize);
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device_class_set_parent_reset(dc, phb3_msi_reset,
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&isc->parent_reset);
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isc->reject = phb3_msi_reject;
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isc->resend = phb3_msi_resend;
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}
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static const TypeInfo phb3_msi_info = {
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.name = TYPE_PHB3_MSI,
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.parent = TYPE_ICS,
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.instance_size = sizeof(Phb3MsiState),
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.class_init = phb3_msi_class_init,
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.class_size = sizeof(ICSStateClass),
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.instance_init = phb3_msi_instance_init,
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};
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static void pnv_phb3_msi_register_types(void)
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{
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type_register_static(&phb3_msi_info);
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}
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type_init(pnv_phb3_msi_register_types);
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void pnv_phb3_msi_pic_print_info(Phb3MsiState *msi, Monitor *mon)
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{
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ICSState *ics = ICS(msi);
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int i;
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monitor_printf(mon, "ICS %4x..%4x %p\n",
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ics->offset, ics->offset + ics->nr_irqs - 1, ics);
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for (i = 0; i < ics->nr_irqs; i++) {
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uint64_t ive;
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if (!phb3_msi_read_ive(msi->phb, i, &ive)) {
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return;
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}
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if (GETFIELD(IODA2_IVT_PRIORITY, ive) == 0xff) {
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continue;
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}
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monitor_printf(mon, " %4x %c%c server=%04x prio=%02x gen=%d\n",
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ics->offset + i,
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GETFIELD(IODA2_IVT_P, ive) ? 'P' : '-',
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GETFIELD(IODA2_IVT_Q, ive) ? 'Q' : '-',
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(uint32_t) GETFIELD(IODA2_IVT_SERVER, ive) >> 2,
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(uint32_t) GETFIELD(IODA2_IVT_PRIORITY, ive),
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(uint32_t) GETFIELD(IODA2_IVT_GEN, ive));
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}
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}
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