536 lines
15 KiB
C
536 lines
15 KiB
C
/*
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* QEMU ESP/NCR53C9x emulation
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*
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* Copyright (c) 2005-2006 Fabrice Bellard
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* Copyright (c) 2012 Herve Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/pci.h"
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#include "hw/irq.h"
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#include "hw/nvram/eeprom93xx.h"
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#include "hw/scsi/esp.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#define TYPE_AM53C974_DEVICE "am53c974"
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#define PCI_ESP(obj) \
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OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE)
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#define DMA_CMD 0x0
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#define DMA_STC 0x1
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#define DMA_SPA 0x2
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#define DMA_WBC 0x3
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#define DMA_WAC 0x4
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#define DMA_STAT 0x5
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#define DMA_SMDLA 0x6
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#define DMA_WMAC 0x7
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#define DMA_CMD_MASK 0x03
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#define DMA_CMD_DIAG 0x04
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#define DMA_CMD_MDL 0x10
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#define DMA_CMD_INTE_P 0x20
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#define DMA_CMD_INTE_D 0x40
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#define DMA_CMD_DIR 0x80
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#define DMA_STAT_PWDN 0x01
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#define DMA_STAT_ERROR 0x02
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#define DMA_STAT_ABORT 0x04
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#define DMA_STAT_DONE 0x08
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#define DMA_STAT_SCSIINT 0x10
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#define DMA_STAT_BCMBLT 0x20
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#define SBAC_STATUS (1 << 24)
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typedef struct PCIESPState {
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/*< private >*/
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PCIDevice parent_obj;
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/*< public >*/
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MemoryRegion io;
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uint32_t dma_regs[8];
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uint32_t sbac;
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ESPState esp;
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} PCIESPState;
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static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
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{
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trace_esp_pci_dma_idle(val);
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esp_dma_enable(&pci->esp, 0, 0);
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}
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static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
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{
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trace_esp_pci_dma_blast(val);
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qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
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}
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static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
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{
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trace_esp_pci_dma_abort(val);
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if (pci->esp.current_req) {
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scsi_req_cancel(pci->esp.current_req);
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}
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}
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static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
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{
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trace_esp_pci_dma_start(val);
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pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
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pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
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pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];
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pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
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| DMA_STAT_DONE | DMA_STAT_ABORT
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| DMA_STAT_ERROR | DMA_STAT_PWDN);
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esp_dma_enable(&pci->esp, 0, 1);
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}
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static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
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{
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trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
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switch (saddr) {
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case DMA_CMD:
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pci->dma_regs[saddr] = val;
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switch (val & DMA_CMD_MASK) {
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case 0x0: /* IDLE */
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esp_pci_handle_idle(pci, val);
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break;
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case 0x1: /* BLAST */
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esp_pci_handle_blast(pci, val);
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break;
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case 0x2: /* ABORT */
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esp_pci_handle_abort(pci, val);
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break;
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case 0x3: /* START */
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esp_pci_handle_start(pci, val);
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break;
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default: /* can't happen */
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abort();
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}
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break;
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case DMA_STC:
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case DMA_SPA:
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case DMA_SMDLA:
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pci->dma_regs[saddr] = val;
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break;
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case DMA_STAT:
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if (pci->sbac & SBAC_STATUS) {
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/* clear some bits on write */
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uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
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pci->dma_regs[DMA_STAT] &= ~(val & mask);
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}
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break;
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default:
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trace_esp_pci_error_invalid_write_dma(val, saddr);
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return;
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}
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}
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static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
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{
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uint32_t val;
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val = pci->dma_regs[saddr];
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if (saddr == DMA_STAT) {
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if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) {
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val |= DMA_STAT_SCSIINT;
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}
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if (!(pci->sbac & SBAC_STATUS)) {
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pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
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DMA_STAT_DONE);
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}
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}
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trace_esp_pci_dma_read(saddr, val);
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return val;
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}
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static void esp_pci_io_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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PCIESPState *pci = opaque;
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if (size < 4 || addr & 3) {
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/* need to upgrade request: we only support 4-bytes accesses */
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uint32_t current = 0, mask;
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int shift;
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if (addr < 0x40) {
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current = pci->esp.wregs[addr >> 2];
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} else if (addr < 0x60) {
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current = pci->dma_regs[(addr - 0x40) >> 2];
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} else if (addr < 0x74) {
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current = pci->sbac;
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}
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shift = (4 - size) * 8;
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mask = (~(uint32_t)0 << shift) >> shift;
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shift = ((4 - (addr & 3)) & 3) * 8;
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val <<= shift;
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val |= current & ~(mask << shift);
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addr &= ~3;
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size = 4;
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}
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g_assert(size >= 4);
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if (addr < 0x40) {
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/* SCSI core reg */
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esp_reg_write(&pci->esp, addr >> 2, val);
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} else if (addr < 0x60) {
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/* PCI DMA CCB */
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esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
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} else if (addr == 0x70) {
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/* DMA SCSI Bus and control */
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trace_esp_pci_sbac_write(pci->sbac, val);
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pci->sbac = val;
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} else {
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trace_esp_pci_error_invalid_write((int)addr);
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}
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}
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static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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PCIESPState *pci = opaque;
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uint32_t ret;
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if (addr < 0x40) {
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/* SCSI core reg */
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ret = esp_reg_read(&pci->esp, addr >> 2);
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} else if (addr < 0x60) {
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/* PCI DMA CCB */
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ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
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} else if (addr == 0x70) {
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/* DMA SCSI Bus and control */
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trace_esp_pci_sbac_read(pci->sbac);
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ret = pci->sbac;
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} else {
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/* Invalid region */
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trace_esp_pci_error_invalid_read((int)addr);
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ret = 0;
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}
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/* give only requested data */
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ret >>= (addr & 3) * 8;
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ret &= ~(~(uint64_t)0 << (8 * size));
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return ret;
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}
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static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
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DMADirection dir)
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{
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dma_addr_t addr;
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DMADirection expected_dir;
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if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
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expected_dir = DMA_DIRECTION_FROM_DEVICE;
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} else {
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expected_dir = DMA_DIRECTION_TO_DEVICE;
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}
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if (dir != expected_dir) {
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trace_esp_pci_error_invalid_dma_direction();
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return;
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}
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if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
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qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
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}
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addr = pci->dma_regs[DMA_SPA];
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if (pci->dma_regs[DMA_WBC] < len) {
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len = pci->dma_regs[DMA_WBC];
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}
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pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir);
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/* update status registers */
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pci->dma_regs[DMA_WBC] -= len;
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pci->dma_regs[DMA_WAC] += len;
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if (pci->dma_regs[DMA_WBC] == 0) {
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pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
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}
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}
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static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len)
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{
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PCIESPState *pci = opaque;
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esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
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}
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static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len)
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{
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PCIESPState *pci = opaque;
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esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
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}
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static const MemoryRegionOps esp_pci_io_ops = {
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.read = esp_pci_io_read,
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.write = esp_pci_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static void esp_pci_hard_reset(DeviceState *dev)
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{
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PCIESPState *pci = PCI_ESP(dev);
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esp_hard_reset(&pci->esp);
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pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P
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| DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK);
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pci->dma_regs[DMA_WBC] &= ~0xffff;
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pci->dma_regs[DMA_WAC] = 0xffffffff;
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pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
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| DMA_STAT_DONE | DMA_STAT_ABORT
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| DMA_STAT_ERROR);
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pci->dma_regs[DMA_WMAC] = 0xfffffffd;
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}
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static const VMStateDescription vmstate_esp_pci_scsi = {
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.name = "pciespscsi",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
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VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
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VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void esp_pci_command_complete(SCSIRequest *req, uint32_t status,
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size_t resid)
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{
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ESPState *s = req->hba_private;
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PCIESPState *pci = container_of(s, PCIESPState, esp);
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esp_command_complete(req, status, resid);
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pci->dma_regs[DMA_WBC] = 0;
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pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
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}
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static const struct SCSIBusInfo esp_pci_scsi_info = {
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.tcq = false,
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.max_target = ESP_MAX_DEVS,
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.max_lun = 7,
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.transfer_data = esp_transfer_data,
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.complete = esp_pci_command_complete,
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.cancel = esp_request_cancelled,
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};
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static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp)
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{
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PCIESPState *pci = PCI_ESP(dev);
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DeviceState *d = DEVICE(dev);
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ESPState *s = &pci->esp;
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uint8_t *pci_conf;
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pci_conf = dev->config;
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/* Interrupt pin A */
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pci_conf[PCI_INTERRUPT_PIN] = 0x01;
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s->dma_memory_read = esp_pci_dma_memory_read;
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s->dma_memory_write = esp_pci_dma_memory_write;
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s->dma_opaque = pci;
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s->chip_id = TCHI_AM53C974;
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memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
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"esp-io", 0x80);
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pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
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s->irq = pci_allocate_irq(dev);
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scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL);
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}
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static void esp_pci_scsi_uninit(PCIDevice *d)
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{
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PCIESPState *pci = PCI_ESP(d);
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qemu_free_irq(pci->esp.irq);
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}
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static void esp_pci_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = esp_pci_scsi_realize;
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k->exit = esp_pci_scsi_uninit;
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k->vendor_id = PCI_VENDOR_ID_AMD;
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k->device_id = PCI_DEVICE_ID_AMD_SCSI;
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k->revision = 0x10;
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k->class_id = PCI_CLASS_STORAGE_SCSI;
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
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dc->reset = esp_pci_hard_reset;
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dc->vmsd = &vmstate_esp_pci_scsi;
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}
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static const TypeInfo esp_pci_info = {
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.name = TYPE_AM53C974_DEVICE,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIESPState),
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.class_init = esp_pci_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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typedef struct {
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PCIESPState pci;
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eeprom_t *eeprom;
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} DC390State;
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#define TYPE_DC390_DEVICE "dc390"
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#define DC390(obj) \
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OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE)
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#define EE_ADAPT_SCSI_ID 64
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#define EE_MODE2 65
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#define EE_DELAY 66
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#define EE_TAG_CMD_NUM 67
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#define EE_ADAPT_OPTIONS 68
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#define EE_BOOT_SCSI_ID 69
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#define EE_BOOT_SCSI_LUN 70
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#define EE_CHKSUM1 126
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#define EE_CHKSUM2 127
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#define EE_ADAPT_OPTION_F6_F8_AT_BOOT 0x01
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#define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
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#define EE_ADAPT_OPTION_INT13 0x04
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#define EE_ADAPT_OPTION_SCAM_SUPPORT 0x08
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static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l)
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{
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DC390State *pci = DC390(dev);
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uint32_t val;
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val = pci_default_read_config(dev, addr, l);
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if (addr == 0x00 && l == 1) {
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/* First byte of address space is AND-ed with EEPROM DO line */
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if (!eeprom93xx_read(pci->eeprom)) {
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val &= ~0xff;
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}
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}
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return val;
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}
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static void dc390_write_config(PCIDevice *dev,
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uint32_t addr, uint32_t val, int l)
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{
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DC390State *pci = DC390(dev);
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if (addr == 0x80) {
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/* EEPROM write */
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int eesk = val & 0x80 ? 1 : 0;
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int eedi = val & 0x40 ? 1 : 0;
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eeprom93xx_write(pci->eeprom, 1, eesk, eedi);
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} else if (addr == 0xc0) {
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/* EEPROM CS low */
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eeprom93xx_write(pci->eeprom, 0, 0, 0);
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} else {
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pci_default_write_config(dev, addr, val, l);
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}
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}
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static void dc390_scsi_realize(PCIDevice *dev, Error **errp)
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{
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DC390State *pci = DC390(dev);
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Error *err = NULL;
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uint8_t *contents;
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uint16_t chksum = 0;
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int i;
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/* init base class */
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esp_pci_scsi_realize(dev, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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/* EEPROM */
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pci->eeprom = eeprom93xx_new(DEVICE(dev), 64);
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/* set default eeprom values */
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contents = (uint8_t *)eeprom93xx_data(pci->eeprom);
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
contents[i * 2] = 0x57;
|
|
contents[i * 2 + 1] = 0x00;
|
|
}
|
|
contents[EE_ADAPT_SCSI_ID] = 7;
|
|
contents[EE_MODE2] = 0x0f;
|
|
contents[EE_TAG_CMD_NUM] = 0x04;
|
|
contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
|
|
| EE_ADAPT_OPTION_BOOT_FROM_CDROM
|
|
| EE_ADAPT_OPTION_INT13;
|
|
|
|
/* update eeprom checksum */
|
|
for (i = 0; i < EE_CHKSUM1; i += 2) {
|
|
chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8);
|
|
}
|
|
chksum = 0x1234 - chksum;
|
|
contents[EE_CHKSUM1] = chksum & 0xff;
|
|
contents[EE_CHKSUM2] = chksum >> 8;
|
|
}
|
|
|
|
static void dc390_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
k->realize = dc390_scsi_realize;
|
|
k->config_read = dc390_read_config;
|
|
k->config_write = dc390_write_config;
|
|
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
|
|
dc->desc = "Tekram DC-390 SCSI adapter";
|
|
}
|
|
|
|
static const TypeInfo dc390_info = {
|
|
.name = "dc390",
|
|
.parent = TYPE_AM53C974_DEVICE,
|
|
.instance_size = sizeof(DC390State),
|
|
.class_init = dc390_class_init,
|
|
};
|
|
|
|
static void esp_pci_register_types(void)
|
|
{
|
|
type_register_static(&esp_pci_info);
|
|
type_register_static(&dc390_info);
|
|
}
|
|
|
|
type_init(esp_pci_register_types)
|