1006 lines
26 KiB
C
1006 lines
26 KiB
C
/*
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* QEMU ESP/NCR53C9x emulation
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*
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* Copyright (c) 2005-2006 Fabrice Bellard
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* Copyright (c) 2012 Herve Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "hw/irq.h"
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#include "hw/scsi/esp.h"
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#include "trace.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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/*
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* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
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* also produced as NCR89C100. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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* and
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
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*
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* On Macintosh Quadra it is a NCR53C96.
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*/
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static void esp_raise_irq(ESPState *s)
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{
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if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
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s->rregs[ESP_RSTAT] |= STAT_INT;
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qemu_irq_raise(s->irq);
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trace_esp_raise_irq();
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}
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}
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static void esp_lower_irq(ESPState *s)
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{
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if (s->rregs[ESP_RSTAT] & STAT_INT) {
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s->rregs[ESP_RSTAT] &= ~STAT_INT;
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qemu_irq_lower(s->irq);
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trace_esp_lower_irq();
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}
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}
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static void esp_raise_drq(ESPState *s)
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{
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qemu_irq_raise(s->irq_data);
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}
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static void esp_lower_drq(ESPState *s)
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{
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qemu_irq_lower(s->irq_data);
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}
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void esp_dma_enable(ESPState *s, int irq, int level)
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{
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if (level) {
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s->dma_enabled = 1;
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trace_esp_dma_enable();
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if (s->dma_cb) {
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s->dma_cb(s);
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s->dma_cb = NULL;
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}
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} else {
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trace_esp_dma_disable();
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s->dma_enabled = 0;
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}
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}
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void esp_request_cancelled(SCSIRequest *req)
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{
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ESPState *s = req->hba_private;
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if (req == s->current_req) {
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scsi_req_unref(s->current_req);
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s->current_req = NULL;
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s->current_dev = NULL;
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}
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}
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static void set_pdma(ESPState *s, enum pdma_origin_id origin,
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uint32_t index, uint32_t len)
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{
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s->pdma_origin = origin;
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s->pdma_start = index;
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s->pdma_cur = index;
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s->pdma_len = len;
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}
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static uint8_t *get_pdma_buf(ESPState *s)
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{
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switch (s->pdma_origin) {
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case PDMA:
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return s->pdma_buf;
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case TI:
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return s->ti_buf;
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case CMD:
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return s->cmdbuf;
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case ASYNC:
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return s->async_buf;
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}
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return NULL;
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}
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static int get_cmd_cb(ESPState *s)
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{
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int target;
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target = s->wregs[ESP_WBUSID] & BUSID_DID;
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s->ti_size = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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if (s->current_req) {
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/* Started a new command before the old one finished. Cancel it. */
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scsi_req_cancel(s->current_req);
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s->async_len = 0;
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}
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s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
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if (!s->current_dev) {
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/* No such drive */
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s->rregs[ESP_RSTAT] = 0;
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s->rregs[ESP_RINTR] = INTR_DC;
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s->rregs[ESP_RSEQ] = SEQ_0;
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esp_raise_irq(s);
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return -1;
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}
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return 0;
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}
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static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen)
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{
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uint32_t dmalen;
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int target;
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target = s->wregs[ESP_WBUSID] & BUSID_DID;
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if (s->dma) {
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dmalen = s->rregs[ESP_TCLO];
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dmalen |= s->rregs[ESP_TCMID] << 8;
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dmalen |= s->rregs[ESP_TCHI] << 16;
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if (dmalen > buflen) {
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return 0;
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}
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if (s->dma_memory_read) {
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s->dma_memory_read(s->dma_opaque, buf, dmalen);
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} else {
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memcpy(s->pdma_buf, buf, dmalen);
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set_pdma(s, PDMA, 0, dmalen);
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esp_raise_drq(s);
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return 0;
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}
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} else {
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dmalen = s->ti_size;
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if (dmalen > TI_BUFSZ) {
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return 0;
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}
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memcpy(buf, s->ti_buf, dmalen);
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buf[0] = buf[2] >> 5;
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}
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trace_esp_get_cmd(dmalen, target);
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if (get_cmd_cb(s) < 0) {
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return 0;
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}
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return dmalen;
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}
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static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
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{
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int32_t datalen;
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int lun;
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SCSIDevice *current_lun;
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trace_esp_do_busid_cmd(busid);
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lun = busid & 7;
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current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
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s->current_req = scsi_req_new(current_lun, 0, lun, buf, s);
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datalen = scsi_req_enqueue(s->current_req);
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s->ti_size = datalen;
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if (datalen != 0) {
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s->rregs[ESP_RSTAT] = STAT_TC;
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s->dma_left = 0;
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s->dma_counter = 0;
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if (datalen > 0) {
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s->rregs[ESP_RSTAT] |= STAT_DI;
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} else {
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s->rregs[ESP_RSTAT] |= STAT_DO;
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}
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scsi_req_continue(s->current_req);
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}
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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esp_raise_irq(s);
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}
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static void do_cmd(ESPState *s, uint8_t *buf)
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{
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uint8_t busid = buf[0];
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do_busid_cmd(s, &buf[1], busid);
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}
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static void satn_pdma_cb(ESPState *s)
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{
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if (get_cmd_cb(s) < 0) {
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return;
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}
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if (s->pdma_cur != s->pdma_start) {
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do_cmd(s, get_pdma_buf(s) + s->pdma_start);
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}
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}
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static void handle_satn(ESPState *s)
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{
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uint8_t buf[32];
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int len;
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if (s->dma && !s->dma_enabled) {
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s->dma_cb = handle_satn;
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return;
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}
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s->pdma_cb = satn_pdma_cb;
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len = get_cmd(s, buf, sizeof(buf));
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if (len)
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do_cmd(s, buf);
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}
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static void s_without_satn_pdma_cb(ESPState *s)
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{
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if (get_cmd_cb(s) < 0) {
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return;
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}
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if (s->pdma_cur != s->pdma_start) {
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do_busid_cmd(s, get_pdma_buf(s) + s->pdma_start, 0);
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}
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}
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static void handle_s_without_atn(ESPState *s)
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{
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uint8_t buf[32];
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int len;
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if (s->dma && !s->dma_enabled) {
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s->dma_cb = handle_s_without_atn;
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return;
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}
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s->pdma_cb = s_without_satn_pdma_cb;
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len = get_cmd(s, buf, sizeof(buf));
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if (len) {
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do_busid_cmd(s, buf, 0);
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}
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}
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static void satn_stop_pdma_cb(ESPState *s)
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{
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if (get_cmd_cb(s) < 0) {
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return;
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}
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s->cmdlen = s->pdma_cur - s->pdma_start;
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if (s->cmdlen) {
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trace_esp_handle_satn_stop(s->cmdlen);
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s->do_cmd = 1;
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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esp_raise_irq(s);
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}
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}
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static void handle_satn_stop(ESPState *s)
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{
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if (s->dma && !s->dma_enabled) {
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s->dma_cb = handle_satn_stop;
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return;
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}
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s->pdma_cb = satn_stop_pdma_cb;
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s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf));
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if (s->cmdlen) {
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trace_esp_handle_satn_stop(s->cmdlen);
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s->do_cmd = 1;
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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esp_raise_irq(s);
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}
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}
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static void write_response_pdma_cb(ESPState *s)
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{
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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esp_raise_irq(s);
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}
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static void write_response(ESPState *s)
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{
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trace_esp_write_response(s->status);
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s->ti_buf[0] = s->status;
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s->ti_buf[1] = 0;
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if (s->dma) {
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if (s->dma_memory_write) {
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s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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} else {
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set_pdma(s, TI, 0, 2);
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s->pdma_cb = write_response_pdma_cb;
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esp_raise_drq(s);
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return;
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}
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} else {
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s->ti_size = 2;
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s->ti_rptr = 0;
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s->ti_wptr = 2;
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s->rregs[ESP_RFLAGS] = 2;
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}
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esp_raise_irq(s);
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}
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static void esp_dma_done(ESPState *s)
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{
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s->rregs[ESP_RSTAT] |= STAT_TC;
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s->rregs[ESP_RINTR] = INTR_BS;
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s->rregs[ESP_RSEQ] = 0;
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s->rregs[ESP_RFLAGS] = 0;
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s->rregs[ESP_TCLO] = 0;
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s->rregs[ESP_TCMID] = 0;
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s->rregs[ESP_TCHI] = 0;
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esp_raise_irq(s);
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}
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static void do_dma_pdma_cb(ESPState *s)
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{
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int to_device = (s->ti_size < 0);
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int len = s->pdma_cur - s->pdma_start;
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if (s->do_cmd) {
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s->ti_size = 0;
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s->cmdlen = 0;
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s->do_cmd = 0;
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do_cmd(s, s->cmdbuf);
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return;
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}
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s->dma_left -= len;
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s->async_buf += len;
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s->async_len -= len;
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if (to_device) {
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s->ti_size += len;
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} else {
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s->ti_size -= len;
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}
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if (s->async_len == 0) {
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scsi_req_continue(s->current_req);
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/*
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* If there is still data to be read from the device then
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* complete the DMA operation immediately. Otherwise defer
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* until the scsi layer has completed.
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*/
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if (to_device || s->dma_left != 0 || s->ti_size == 0) {
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return;
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}
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}
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/* Partially filled a scsi buffer. Complete immediately. */
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esp_dma_done(s);
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}
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static void esp_do_dma(ESPState *s)
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{
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uint32_t len;
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int to_device;
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len = s->dma_left;
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if (s->do_cmd) {
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/*
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* handle_ti_cmd() case: esp_do_dma() is called only from
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* handle_ti_cmd() with do_cmd != NULL (see the assert())
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*/
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trace_esp_do_dma(s->cmdlen, len);
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assert (s->cmdlen <= sizeof(s->cmdbuf) &&
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len <= sizeof(s->cmdbuf) - s->cmdlen);
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if (s->dma_memory_read) {
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s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
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} else {
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set_pdma(s, CMD, s->cmdlen, len);
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s->pdma_cb = do_dma_pdma_cb;
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esp_raise_drq(s);
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return;
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}
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trace_esp_handle_ti_cmd(s->cmdlen);
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s->ti_size = 0;
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s->cmdlen = 0;
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s->do_cmd = 0;
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do_cmd(s, s->cmdbuf);
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return;
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}
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if (s->async_len == 0) {
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/* Defer until data is available. */
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return;
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}
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if (len > s->async_len) {
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len = s->async_len;
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}
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to_device = (s->ti_size < 0);
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if (to_device) {
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if (s->dma_memory_read) {
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s->dma_memory_read(s->dma_opaque, s->async_buf, len);
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} else {
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set_pdma(s, ASYNC, 0, len);
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s->pdma_cb = do_dma_pdma_cb;
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esp_raise_drq(s);
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return;
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}
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} else {
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if (s->dma_memory_write) {
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s->dma_memory_write(s->dma_opaque, s->async_buf, len);
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} else {
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set_pdma(s, ASYNC, 0, len);
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s->pdma_cb = do_dma_pdma_cb;
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esp_raise_drq(s);
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return;
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}
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}
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s->dma_left -= len;
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s->async_buf += len;
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s->async_len -= len;
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if (to_device)
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s->ti_size += len;
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else
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s->ti_size -= len;
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if (s->async_len == 0) {
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scsi_req_continue(s->current_req);
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/* If there is still data to be read from the device then
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complete the DMA operation immediately. Otherwise defer
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until the scsi layer has completed. */
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if (to_device || s->dma_left != 0 || s->ti_size == 0) {
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return;
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}
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}
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/* Partially filled a scsi buffer. Complete immediately. */
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esp_dma_done(s);
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}
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static void esp_report_command_complete(ESPState *s, uint32_t status)
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{
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trace_esp_command_complete();
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if (s->ti_size != 0) {
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trace_esp_command_complete_unexpected();
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}
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s->ti_size = 0;
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s->dma_left = 0;
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s->async_len = 0;
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if (status) {
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trace_esp_command_complete_fail();
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}
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s->status = status;
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s->rregs[ESP_RSTAT] = STAT_ST;
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esp_dma_done(s);
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if (s->current_req) {
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scsi_req_unref(s->current_req);
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s->current_req = NULL;
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s->current_dev = NULL;
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}
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}
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void esp_command_complete(SCSIRequest *req, uint32_t status,
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size_t resid)
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{
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ESPState *s = req->hba_private;
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if (s->rregs[ESP_RSTAT] & STAT_INT) {
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/* Defer handling command complete until the previous
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* interrupt has been handled.
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*/
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trace_esp_command_complete_deferred();
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s->deferred_status = status;
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s->deferred_complete = true;
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return;
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}
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esp_report_command_complete(s, status);
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}
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void esp_transfer_data(SCSIRequest *req, uint32_t len)
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{
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ESPState *s = req->hba_private;
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|
|
|
assert(!s->do_cmd);
|
|
trace_esp_transfer_data(s->dma_left, s->ti_size);
|
|
s->async_len = len;
|
|
s->async_buf = scsi_req_get_buf(req);
|
|
if (s->dma_left) {
|
|
esp_do_dma(s);
|
|
} else if (s->dma_counter != 0 && s->ti_size <= 0) {
|
|
/* If this was the last part of a DMA transfer then the
|
|
completion interrupt is deferred to here. */
|
|
esp_dma_done(s);
|
|
}
|
|
}
|
|
|
|
static void handle_ti(ESPState *s)
|
|
{
|
|
uint32_t dmalen, minlen;
|
|
|
|
if (s->dma && !s->dma_enabled) {
|
|
s->dma_cb = handle_ti;
|
|
return;
|
|
}
|
|
|
|
dmalen = s->rregs[ESP_TCLO];
|
|
dmalen |= s->rregs[ESP_TCMID] << 8;
|
|
dmalen |= s->rregs[ESP_TCHI] << 16;
|
|
if (dmalen==0) {
|
|
dmalen=0x10000;
|
|
}
|
|
s->dma_counter = dmalen;
|
|
|
|
if (s->do_cmd)
|
|
minlen = (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ;
|
|
else if (s->ti_size < 0)
|
|
minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
|
|
else
|
|
minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
|
|
trace_esp_handle_ti(minlen);
|
|
if (s->dma) {
|
|
s->dma_left = minlen;
|
|
s->rregs[ESP_RSTAT] &= ~STAT_TC;
|
|
esp_do_dma(s);
|
|
} else if (s->do_cmd) {
|
|
trace_esp_handle_ti_cmd(s->cmdlen);
|
|
s->ti_size = 0;
|
|
s->cmdlen = 0;
|
|
s->do_cmd = 0;
|
|
do_cmd(s, s->cmdbuf);
|
|
}
|
|
}
|
|
|
|
void esp_hard_reset(ESPState *s)
|
|
{
|
|
memset(s->rregs, 0, ESP_REGS);
|
|
memset(s->wregs, 0, ESP_REGS);
|
|
s->tchi_written = 0;
|
|
s->ti_size = 0;
|
|
s->ti_rptr = 0;
|
|
s->ti_wptr = 0;
|
|
s->dma = 0;
|
|
s->do_cmd = 0;
|
|
s->dma_cb = NULL;
|
|
|
|
s->rregs[ESP_CFG1] = 7;
|
|
}
|
|
|
|
static void esp_soft_reset(ESPState *s)
|
|
{
|
|
qemu_irq_lower(s->irq);
|
|
qemu_irq_lower(s->irq_data);
|
|
esp_hard_reset(s);
|
|
}
|
|
|
|
static void parent_esp_reset(ESPState *s, int irq, int level)
|
|
{
|
|
if (level) {
|
|
esp_soft_reset(s);
|
|
}
|
|
}
|
|
|
|
uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
|
|
{
|
|
uint32_t old_val;
|
|
|
|
trace_esp_mem_readb(saddr, s->rregs[saddr]);
|
|
switch (saddr) {
|
|
case ESP_FIFO:
|
|
if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
|
|
/* Data out. */
|
|
qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n");
|
|
s->rregs[ESP_FIFO] = 0;
|
|
} else if (s->ti_rptr < s->ti_wptr) {
|
|
s->ti_size--;
|
|
s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
|
|
}
|
|
if (s->ti_rptr == s->ti_wptr) {
|
|
s->ti_rptr = 0;
|
|
s->ti_wptr = 0;
|
|
}
|
|
break;
|
|
case ESP_RINTR:
|
|
/* Clear sequence step, interrupt register and all status bits
|
|
except TC */
|
|
old_val = s->rregs[ESP_RINTR];
|
|
s->rregs[ESP_RINTR] = 0;
|
|
s->rregs[ESP_RSTAT] &= ~STAT_TC;
|
|
s->rregs[ESP_RSEQ] = SEQ_CD;
|
|
esp_lower_irq(s);
|
|
if (s->deferred_complete) {
|
|
esp_report_command_complete(s, s->deferred_status);
|
|
s->deferred_complete = false;
|
|
}
|
|
return old_val;
|
|
case ESP_TCHI:
|
|
/* Return the unique id if the value has never been written */
|
|
if (!s->tchi_written) {
|
|
return s->chip_id;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
return s->rregs[saddr];
|
|
}
|
|
|
|
void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
|
|
{
|
|
trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
|
|
switch (saddr) {
|
|
case ESP_TCHI:
|
|
s->tchi_written = true;
|
|
/* fall through */
|
|
case ESP_TCLO:
|
|
case ESP_TCMID:
|
|
s->rregs[ESP_RSTAT] &= ~STAT_TC;
|
|
break;
|
|
case ESP_FIFO:
|
|
if (s->do_cmd) {
|
|
if (s->cmdlen < ESP_CMDBUF_SZ) {
|
|
s->cmdbuf[s->cmdlen++] = val & 0xff;
|
|
} else {
|
|
trace_esp_error_fifo_overrun();
|
|
}
|
|
} else if (s->ti_wptr == TI_BUFSZ - 1) {
|
|
trace_esp_error_fifo_overrun();
|
|
} else {
|
|
s->ti_size++;
|
|
s->ti_buf[s->ti_wptr++] = val & 0xff;
|
|
}
|
|
break;
|
|
case ESP_CMD:
|
|
s->rregs[saddr] = val;
|
|
if (val & CMD_DMA) {
|
|
s->dma = 1;
|
|
/* Reload DMA counter. */
|
|
s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
|
|
s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
|
|
s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI];
|
|
} else {
|
|
s->dma = 0;
|
|
}
|
|
switch(val & CMD_CMD) {
|
|
case CMD_NOP:
|
|
trace_esp_mem_writeb_cmd_nop(val);
|
|
break;
|
|
case CMD_FLUSH:
|
|
trace_esp_mem_writeb_cmd_flush(val);
|
|
//s->ti_size = 0;
|
|
s->rregs[ESP_RINTR] = INTR_FC;
|
|
s->rregs[ESP_RSEQ] = 0;
|
|
s->rregs[ESP_RFLAGS] = 0;
|
|
break;
|
|
case CMD_RESET:
|
|
trace_esp_mem_writeb_cmd_reset(val);
|
|
esp_soft_reset(s);
|
|
break;
|
|
case CMD_BUSRESET:
|
|
trace_esp_mem_writeb_cmd_bus_reset(val);
|
|
s->rregs[ESP_RINTR] = INTR_RST;
|
|
if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
|
|
esp_raise_irq(s);
|
|
}
|
|
break;
|
|
case CMD_TI:
|
|
handle_ti(s);
|
|
break;
|
|
case CMD_ICCS:
|
|
trace_esp_mem_writeb_cmd_iccs(val);
|
|
write_response(s);
|
|
s->rregs[ESP_RINTR] = INTR_FC;
|
|
s->rregs[ESP_RSTAT] |= STAT_MI;
|
|
break;
|
|
case CMD_MSGACC:
|
|
trace_esp_mem_writeb_cmd_msgacc(val);
|
|
s->rregs[ESP_RINTR] = INTR_DC;
|
|
s->rregs[ESP_RSEQ] = 0;
|
|
s->rregs[ESP_RFLAGS] = 0;
|
|
esp_raise_irq(s);
|
|
break;
|
|
case CMD_PAD:
|
|
trace_esp_mem_writeb_cmd_pad(val);
|
|
s->rregs[ESP_RSTAT] = STAT_TC;
|
|
s->rregs[ESP_RINTR] = INTR_FC;
|
|
s->rregs[ESP_RSEQ] = 0;
|
|
break;
|
|
case CMD_SATN:
|
|
trace_esp_mem_writeb_cmd_satn(val);
|
|
break;
|
|
case CMD_RSTATN:
|
|
trace_esp_mem_writeb_cmd_rstatn(val);
|
|
break;
|
|
case CMD_SEL:
|
|
trace_esp_mem_writeb_cmd_sel(val);
|
|
handle_s_without_atn(s);
|
|
break;
|
|
case CMD_SELATN:
|
|
trace_esp_mem_writeb_cmd_selatn(val);
|
|
handle_satn(s);
|
|
break;
|
|
case CMD_SELATNS:
|
|
trace_esp_mem_writeb_cmd_selatns(val);
|
|
handle_satn_stop(s);
|
|
break;
|
|
case CMD_ENSEL:
|
|
trace_esp_mem_writeb_cmd_ensel(val);
|
|
s->rregs[ESP_RINTR] = 0;
|
|
break;
|
|
case CMD_DISSEL:
|
|
trace_esp_mem_writeb_cmd_dissel(val);
|
|
s->rregs[ESP_RINTR] = 0;
|
|
esp_raise_irq(s);
|
|
break;
|
|
default:
|
|
trace_esp_error_unhandled_command(val);
|
|
break;
|
|
}
|
|
break;
|
|
case ESP_WBUSID ... ESP_WSYNO:
|
|
break;
|
|
case ESP_CFG1:
|
|
case ESP_CFG2: case ESP_CFG3:
|
|
case ESP_RES3: case ESP_RES4:
|
|
s->rregs[saddr] = val;
|
|
break;
|
|
case ESP_WCCF ... ESP_WTEST:
|
|
break;
|
|
default:
|
|
trace_esp_error_invalid_write(val, saddr);
|
|
return;
|
|
}
|
|
s->wregs[saddr] = val;
|
|
}
|
|
|
|
static bool esp_mem_accepts(void *opaque, hwaddr addr,
|
|
unsigned size, bool is_write,
|
|
MemTxAttrs attrs)
|
|
{
|
|
return (size == 1) || (is_write && size == 4);
|
|
}
|
|
|
|
static bool esp_pdma_needed(void *opaque)
|
|
{
|
|
ESPState *s = opaque;
|
|
return s->dma_memory_read == NULL && s->dma_memory_write == NULL &&
|
|
s->dma_enabled;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_esp_pdma = {
|
|
.name = "esp/pdma",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = esp_pdma_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_BUFFER(pdma_buf, ESPState),
|
|
VMSTATE_INT32(pdma_origin, ESPState),
|
|
VMSTATE_UINT32(pdma_len, ESPState),
|
|
VMSTATE_UINT32(pdma_start, ESPState),
|
|
VMSTATE_UINT32(pdma_cur, ESPState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
const VMStateDescription vmstate_esp = {
|
|
.name ="esp",
|
|
.version_id = 4,
|
|
.minimum_version_id = 3,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_BUFFER(rregs, ESPState),
|
|
VMSTATE_BUFFER(wregs, ESPState),
|
|
VMSTATE_INT32(ti_size, ESPState),
|
|
VMSTATE_UINT32(ti_rptr, ESPState),
|
|
VMSTATE_UINT32(ti_wptr, ESPState),
|
|
VMSTATE_BUFFER(ti_buf, ESPState),
|
|
VMSTATE_UINT32(status, ESPState),
|
|
VMSTATE_UINT32(deferred_status, ESPState),
|
|
VMSTATE_BOOL(deferred_complete, ESPState),
|
|
VMSTATE_UINT32(dma, ESPState),
|
|
VMSTATE_PARTIAL_BUFFER(cmdbuf, ESPState, 16),
|
|
VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf, ESPState, 16, 4),
|
|
VMSTATE_UINT32(cmdlen, ESPState),
|
|
VMSTATE_UINT32(do_cmd, ESPState),
|
|
VMSTATE_UINT32(dma_left, ESPState),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
.subsections = (const VMStateDescription * []) {
|
|
&vmstate_esp_pdma,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
|
|
uint64_t val, unsigned int size)
|
|
{
|
|
SysBusESPState *sysbus = opaque;
|
|
uint32_t saddr;
|
|
|
|
saddr = addr >> sysbus->it_shift;
|
|
esp_reg_write(&sysbus->esp, saddr, val);
|
|
}
|
|
|
|
static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
|
|
unsigned int size)
|
|
{
|
|
SysBusESPState *sysbus = opaque;
|
|
uint32_t saddr;
|
|
|
|
saddr = addr >> sysbus->it_shift;
|
|
return esp_reg_read(&sysbus->esp, saddr);
|
|
}
|
|
|
|
static const MemoryRegionOps sysbus_esp_mem_ops = {
|
|
.read = sysbus_esp_mem_read,
|
|
.write = sysbus_esp_mem_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
.valid.accepts = esp_mem_accepts,
|
|
};
|
|
|
|
static void sysbus_esp_pdma_write(void *opaque, hwaddr addr,
|
|
uint64_t val, unsigned int size)
|
|
{
|
|
SysBusESPState *sysbus = opaque;
|
|
ESPState *s = &sysbus->esp;
|
|
uint32_t dmalen;
|
|
uint8_t *buf = get_pdma_buf(s);
|
|
|
|
dmalen = s->rregs[ESP_TCLO];
|
|
dmalen |= s->rregs[ESP_TCMID] << 8;
|
|
dmalen |= s->rregs[ESP_TCHI] << 16;
|
|
if (dmalen == 0 || s->pdma_len == 0) {
|
|
return;
|
|
}
|
|
switch (size) {
|
|
case 1:
|
|
buf[s->pdma_cur++] = val;
|
|
s->pdma_len--;
|
|
dmalen--;
|
|
break;
|
|
case 2:
|
|
buf[s->pdma_cur++] = val >> 8;
|
|
buf[s->pdma_cur++] = val;
|
|
s->pdma_len -= 2;
|
|
dmalen -= 2;
|
|
break;
|
|
}
|
|
s->rregs[ESP_TCLO] = dmalen & 0xff;
|
|
s->rregs[ESP_TCMID] = dmalen >> 8;
|
|
s->rregs[ESP_TCHI] = dmalen >> 16;
|
|
if (s->pdma_len == 0 && s->pdma_cb) {
|
|
esp_lower_drq(s);
|
|
s->pdma_cb(s);
|
|
s->pdma_cb = NULL;
|
|
}
|
|
}
|
|
|
|
static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr,
|
|
unsigned int size)
|
|
{
|
|
SysBusESPState *sysbus = opaque;
|
|
ESPState *s = &sysbus->esp;
|
|
uint8_t *buf = get_pdma_buf(s);
|
|
uint64_t val = 0;
|
|
|
|
if (s->pdma_len == 0) {
|
|
return 0;
|
|
}
|
|
switch (size) {
|
|
case 1:
|
|
val = buf[s->pdma_cur++];
|
|
s->pdma_len--;
|
|
break;
|
|
case 2:
|
|
val = buf[s->pdma_cur++];
|
|
val = (val << 8) | buf[s->pdma_cur++];
|
|
s->pdma_len -= 2;
|
|
break;
|
|
}
|
|
|
|
if (s->pdma_len == 0 && s->pdma_cb) {
|
|
esp_lower_drq(s);
|
|
s->pdma_cb(s);
|
|
s->pdma_cb = NULL;
|
|
}
|
|
return val;
|
|
}
|
|
|
|
static const MemoryRegionOps sysbus_esp_pdma_ops = {
|
|
.read = sysbus_esp_pdma_read,
|
|
.write = sysbus_esp_pdma_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
.valid.min_access_size = 1,
|
|
.valid.max_access_size = 2,
|
|
};
|
|
|
|
static const struct SCSIBusInfo esp_scsi_info = {
|
|
.tcq = false,
|
|
.max_target = ESP_MAX_DEVS,
|
|
.max_lun = 7,
|
|
|
|
.transfer_data = esp_transfer_data,
|
|
.complete = esp_command_complete,
|
|
.cancel = esp_request_cancelled
|
|
};
|
|
|
|
static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
|
|
{
|
|
SysBusESPState *sysbus = ESP_STATE(opaque);
|
|
ESPState *s = &sysbus->esp;
|
|
|
|
switch (irq) {
|
|
case 0:
|
|
parent_esp_reset(s, irq, level);
|
|
break;
|
|
case 1:
|
|
esp_dma_enable(opaque, irq, level);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void sysbus_esp_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
SysBusESPState *sysbus = ESP_STATE(dev);
|
|
ESPState *s = &sysbus->esp;
|
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
sysbus_init_irq(sbd, &s->irq_data);
|
|
assert(sysbus->it_shift != -1);
|
|
|
|
s->chip_id = TCHI_FAS100A;
|
|
memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops,
|
|
sysbus, "esp-regs", ESP_REGS << sysbus->it_shift);
|
|
sysbus_init_mmio(sbd, &sysbus->iomem);
|
|
memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops,
|
|
sysbus, "esp-pdma", 2);
|
|
sysbus_init_mmio(sbd, &sysbus->pdma);
|
|
|
|
qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
|
|
|
|
scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
|
|
}
|
|
|
|
static void sysbus_esp_hard_reset(DeviceState *dev)
|
|
{
|
|
SysBusESPState *sysbus = ESP_STATE(dev);
|
|
esp_hard_reset(&sysbus->esp);
|
|
}
|
|
|
|
static const VMStateDescription vmstate_sysbus_esp_scsi = {
|
|
.name = "sysbusespscsi",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void sysbus_esp_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = sysbus_esp_realize;
|
|
dc->reset = sysbus_esp_hard_reset;
|
|
dc->vmsd = &vmstate_sysbus_esp_scsi;
|
|
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo sysbus_esp_info = {
|
|
.name = TYPE_ESP,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(SysBusESPState),
|
|
.class_init = sysbus_esp_class_init,
|
|
};
|
|
|
|
static void esp_register_types(void)
|
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{
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type_register_static(&sysbus_esp_info);
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}
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type_init(esp_register_types)
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