359 lines
11 KiB
C
359 lines
11 KiB
C
/*
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* QEMU Sun4u/Sun4v System Emulator common routines
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/char/serial.h"
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#include "hw/sparc/sparc64.h"
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#include "qemu/timer.h"
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#include "sysemu/reset.h"
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#include "trace.h"
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#define TICK_MAX 0x7fffffffffffffffULL
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void cpu_check_irqs(CPUSPARCState *env)
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{
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CPUState *cs;
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uint32_t pil = env->pil_in |
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(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
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/* We should be holding the BQL before we mess with IRQs */
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g_assert(qemu_mutex_iothread_locked());
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/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
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if (env->ivec_status & 0x20) {
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return;
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}
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cs = env_cpu(env);
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/* check if TM or SM in SOFTINT are set
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setting these also causes interrupt 14 */
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if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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pil |= 1 << 14;
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}
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/* The bit corresponding to psrpil is (1<< psrpil), the next bit
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is (2 << psrpil). */
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if (pil < (2 << env->psrpil)) {
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if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
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trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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return;
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}
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if (cpu_interrupts_enabled(env)) {
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unsigned int i;
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for (i = 15; i > env->psrpil; i--) {
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if (pil & (1 << i)) {
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int old_interrupt = env->interrupt_index;
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int new_interrupt = TT_EXTINT | i;
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if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
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&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
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trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
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cpu_tsptr(env)->tt,
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new_interrupt);
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} else if (old_interrupt != new_interrupt) {
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env->interrupt_index = new_interrupt;
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trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
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new_interrupt);
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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break;
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}
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}
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} else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
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trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
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env->interrupt_index);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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static void cpu_kick_irq(SPARCCPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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CPUSPARCState *env = &cpu->env;
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cs->halted = 0;
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cpu_check_irqs(env);
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qemu_cpu_kick(cs);
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}
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void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level)
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{
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SPARCCPU *cpu = opaque;
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CPUSPARCState *env = &cpu->env;
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CPUState *cs;
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if (level) {
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if (!(env->ivec_status & 0x20)) {
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trace_sparc64_cpu_ivec_raise_irq(irq);
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cs = CPU(cpu);
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cs->halted = 0;
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env->interrupt_index = TT_IVEC;
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env->ivec_status |= 0x20;
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env->ivec_data[0] = (0x1f << 6) | irq;
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env->ivec_data[1] = 0;
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env->ivec_data[2] = 0;
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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} else {
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if (env->ivec_status & 0x20) {
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trace_sparc64_cpu_ivec_lower_irq(irq);
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cs = CPU(cpu);
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env->ivec_status &= ~0x20;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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}
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typedef struct ResetData {
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SPARCCPU *cpu;
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uint64_t prom_addr;
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} ResetData;
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static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
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QEMUBHFunc *cb, uint32_t frequency,
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uint64_t disabled_mask, uint64_t npt_mask)
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{
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CPUTimer *timer = g_malloc0(sizeof(CPUTimer));
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timer->name = name;
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timer->frequency = frequency;
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timer->disabled_mask = disabled_mask;
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timer->npt_mask = npt_mask;
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timer->disabled = 1;
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timer->npt = 1;
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timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu);
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return timer;
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}
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static void cpu_timer_reset(CPUTimer *timer)
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{
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timer->disabled = 1;
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timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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timer_del(timer->qtimer);
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}
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static void main_cpu_reset(void *opaque)
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{
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ResetData *s = (ResetData *)opaque;
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CPUSPARCState *env = &s->cpu->env;
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static unsigned int nr_resets;
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cpu_reset(CPU(s->cpu));
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cpu_timer_reset(env->tick);
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cpu_timer_reset(env->stick);
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cpu_timer_reset(env->hstick);
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env->gregs[1] = 0; /* Memory start */
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env->gregs[2] = ram_size; /* Memory size */
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env->gregs[3] = 0; /* Machine description XXX */
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if (nr_resets++ == 0) {
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/* Power on reset */
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env->pc = s->prom_addr + 0x20ULL;
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} else {
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env->pc = s->prom_addr + 0x40ULL;
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}
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env->npc = env->pc + 4;
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}
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static void tick_irq(void *opaque)
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{
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SPARCCPU *cpu = opaque;
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CPUSPARCState *env = &cpu->env;
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CPUTimer *timer = env->tick;
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if (timer->disabled) {
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trace_sparc64_cpu_tick_irq_disabled();
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return;
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} else {
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trace_sparc64_cpu_tick_irq_fire();
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}
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env->softint |= SOFTINT_TIMER;
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cpu_kick_irq(cpu);
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}
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static void stick_irq(void *opaque)
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{
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SPARCCPU *cpu = opaque;
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CPUSPARCState *env = &cpu->env;
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CPUTimer *timer = env->stick;
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if (timer->disabled) {
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trace_sparc64_cpu_stick_irq_disabled();
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return;
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} else {
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trace_sparc64_cpu_stick_irq_fire();
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}
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env->softint |= SOFTINT_STIMER;
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cpu_kick_irq(cpu);
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}
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static void hstick_irq(void *opaque)
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{
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SPARCCPU *cpu = opaque;
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CPUSPARCState *env = &cpu->env;
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CPUTimer *timer = env->hstick;
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if (timer->disabled) {
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trace_sparc64_cpu_hstick_irq_disabled();
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return;
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} else {
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trace_sparc64_cpu_hstick_irq_fire();
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}
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env->softint |= SOFTINT_STIMER;
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cpu_kick_irq(cpu);
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}
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static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
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{
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return muldiv64(cpu_ticks, NANOSECONDS_PER_SECOND, frequency);
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}
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static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
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{
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return muldiv64(timer_ticks, frequency, NANOSECONDS_PER_SECOND);
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}
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void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
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{
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uint64_t real_count = count & ~timer->npt_mask;
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uint64_t npt_bit = count & timer->npt_mask;
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int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
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cpu_to_timer_ticks(real_count, timer->frequency);
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trace_sparc64_cpu_tick_set_count(timer->name, real_count,
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timer->npt ? "disabled" : "enabled",
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timer);
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timer->npt = npt_bit ? 1 : 0;
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timer->clock_offset = vm_clock_offset;
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}
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uint64_t cpu_tick_get_count(CPUTimer *timer)
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{
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uint64_t real_count = timer_to_cpu_ticks(
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset,
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timer->frequency);
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trace_sparc64_cpu_tick_get_count(timer->name, real_count,
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timer->npt ? "disabled" : "enabled",
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timer);
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if (timer->npt) {
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real_count |= timer->npt_mask;
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}
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return real_count;
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}
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void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
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{
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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uint64_t real_limit = limit & ~timer->disabled_mask;
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timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
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int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
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timer->clock_offset;
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if (expires < now) {
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expires = now + 1;
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}
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trace_sparc64_cpu_tick_set_limit(timer->name, real_limit,
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timer->disabled ? "disabled" : "enabled",
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timer, limit,
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timer_to_cpu_ticks(
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now - timer->clock_offset,
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timer->frequency
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),
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timer_to_cpu_ticks(
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expires - now, timer->frequency
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));
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if (!real_limit) {
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trace_sparc64_cpu_tick_set_limit_zero(timer->name);
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timer_del(timer->qtimer);
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} else if (timer->disabled) {
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timer_del(timer->qtimer);
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} else {
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timer_mod(timer->qtimer, expires);
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}
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}
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SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr)
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{
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SPARCCPU *cpu;
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CPUSPARCState *env;
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ResetData *reset_info;
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uint32_t tick_frequency = 100 * 1000000;
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uint32_t stick_frequency = 100 * 1000000;
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uint32_t hstick_frequency = 100 * 1000000;
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cpu = SPARC_CPU(cpu_create(cpu_type));
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qdev_init_gpio_in_named(DEVICE(cpu), sparc64_cpu_set_ivec_irq,
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"ivec-irq", IVEC_MAX);
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env = &cpu->env;
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env->tick = cpu_timer_create("tick", cpu, tick_irq,
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tick_frequency, TICK_INT_DIS,
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TICK_NPT_MASK);
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env->stick = cpu_timer_create("stick", cpu, stick_irq,
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stick_frequency, TICK_INT_DIS,
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TICK_NPT_MASK);
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env->hstick = cpu_timer_create("hstick", cpu, hstick_irq,
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hstick_frequency, TICK_INT_DIS,
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TICK_NPT_MASK);
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reset_info = g_malloc0(sizeof(ResetData));
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reset_info->cpu = cpu;
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reset_info->prom_addr = prom_addr;
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qemu_register_reset(main_cpu_reset, reset_info);
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return cpu;
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}
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