583 lines
15 KiB
C
583 lines
15 KiB
C
/*
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* IMX GPT Timer
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*
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* Copyright (c) 2008 OK Labs
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* Copyright (c) 2011 NICTA Pty Ltd
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* Originally written by Hans Jiang
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* Updated by Peter Chubb
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This code is licensed under GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/timer/imx_gpt.h"
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#include "migration/vmstate.h"
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#include "qemu/module.h"
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#include "qemu/log.h"
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#ifndef DEBUG_IMX_GPT
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#define DEBUG_IMX_GPT 0
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#endif
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_GPT) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \
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__func__, ##args); \
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} \
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} while (0)
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static const char *imx_gpt_reg_name(uint32_t reg)
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{
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switch (reg) {
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case 0:
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return "CR";
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case 1:
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return "PR";
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case 2:
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return "SR";
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case 3:
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return "IR";
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case 4:
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return "OCR1";
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case 5:
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return "OCR2";
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case 6:
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return "OCR3";
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case 7:
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return "ICR1";
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case 8:
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return "ICR2";
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case 9:
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return "CNT";
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default:
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return "[?]";
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}
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}
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static const VMStateDescription vmstate_imx_timer_gpt = {
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.name = TYPE_IMX_GPT,
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.version_id = 3,
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.minimum_version_id = 3,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cr, IMXGPTState),
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VMSTATE_UINT32(pr, IMXGPTState),
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VMSTATE_UINT32(sr, IMXGPTState),
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VMSTATE_UINT32(ir, IMXGPTState),
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VMSTATE_UINT32(ocr1, IMXGPTState),
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VMSTATE_UINT32(ocr2, IMXGPTState),
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VMSTATE_UINT32(ocr3, IMXGPTState),
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VMSTATE_UINT32(icr1, IMXGPTState),
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VMSTATE_UINT32(icr2, IMXGPTState),
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VMSTATE_UINT32(cnt, IMXGPTState),
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VMSTATE_UINT32(next_timeout, IMXGPTState),
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VMSTATE_UINT32(next_int, IMXGPTState),
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VMSTATE_UINT32(freq, IMXGPTState),
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VMSTATE_PTIMER(timer, IMXGPTState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const IMXClk imx25_gpt_clocks[] = {
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CLK_NONE, /* 000 No clock source */
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CLK_IPG, /* 001 ipg_clk, 532MHz*/
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CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
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CLK_NONE, /* 011 not defined */
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CLK_32k, /* 100 ipg_clk_32k */
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CLK_32k, /* 101 ipg_clk_32k */
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CLK_32k, /* 110 ipg_clk_32k */
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CLK_32k, /* 111 ipg_clk_32k */
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};
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static const IMXClk imx31_gpt_clocks[] = {
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CLK_NONE, /* 000 No clock source */
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CLK_IPG, /* 001 ipg_clk, 532MHz*/
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CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
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CLK_NONE, /* 011 not defined */
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CLK_32k, /* 100 ipg_clk_32k */
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CLK_NONE, /* 101 not defined */
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CLK_NONE, /* 110 not defined */
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CLK_NONE, /* 111 not defined */
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};
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static const IMXClk imx6_gpt_clocks[] = {
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CLK_NONE, /* 000 No clock source */
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CLK_IPG, /* 001 ipg_clk, 532MHz*/
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CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
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CLK_EXT, /* 011 External clock */
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CLK_32k, /* 100 ipg_clk_32k */
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CLK_HIGH_DIV, /* 101 reference clock / 8 */
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CLK_NONE, /* 110 not defined */
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CLK_HIGH, /* 111 reference clock */
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};
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static const IMXClk imx7_gpt_clocks[] = {
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CLK_NONE, /* 000 No clock source */
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CLK_IPG, /* 001 ipg_clk, 532MHz*/
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CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
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CLK_EXT, /* 011 External clock */
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CLK_32k, /* 100 ipg_clk_32k */
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CLK_HIGH, /* 101 reference clock */
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CLK_NONE, /* 110 not defined */
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CLK_NONE, /* 111 not defined */
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};
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/* Must be called from within ptimer_transaction_begin/commit block */
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static void imx_gpt_set_freq(IMXGPTState *s)
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{
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uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3);
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s->freq = imx_ccm_get_clock_frequency(s->ccm,
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s->clocks[clksrc]) / (1 + s->pr);
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DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, s->freq);
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if (s->freq) {
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ptimer_set_freq(s->timer, s->freq);
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}
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}
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static void imx_gpt_update_int(IMXGPTState *s)
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{
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if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static uint32_t imx_gpt_update_count(IMXGPTState *s)
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{
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s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer);
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return s->cnt;
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}
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static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg,
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uint32_t timeout)
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{
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if ((count < reg) && (timeout > reg)) {
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timeout = reg;
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}
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return timeout;
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}
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/* Must be called from within ptimer_transaction_begin/commit block */
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static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event)
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{
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uint32_t timeout = GPT_TIMER_MAX;
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uint32_t count;
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long long limit;
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if (!(s->cr & GPT_CR_EN)) {
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/* if not enabled just return */
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return;
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}
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/* update the count */
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count = imx_gpt_update_count(s);
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if (event) {
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/*
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* This is an event (the ptimer reached 0 and stopped), and the
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* timer counter is now equal to s->next_timeout.
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*/
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if (!(s->cr & GPT_CR_FRR) && (count == s->ocr1)) {
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/* We are in restart mode and we crossed the compare channel 1
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* value. We need to reset the counter to 0.
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*/
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count = s->cnt = s->next_timeout = 0;
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} else if (count == GPT_TIMER_MAX) {
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/* We reached GPT_TIMER_MAX so we need to rollover */
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count = s->cnt = s->next_timeout = 0;
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}
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}
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/* now, find the next timeout related to count */
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if (s->ir & GPT_IR_OF1IE) {
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timeout = imx_gpt_find_limit(count, s->ocr1, timeout);
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}
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if (s->ir & GPT_IR_OF2IE) {
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timeout = imx_gpt_find_limit(count, s->ocr2, timeout);
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}
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if (s->ir & GPT_IR_OF3IE) {
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timeout = imx_gpt_find_limit(count, s->ocr3, timeout);
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}
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/* find the next set of interrupts to raise for next timer event */
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s->next_int = 0;
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if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) {
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s->next_int |= GPT_SR_OF1;
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}
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if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) {
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s->next_int |= GPT_SR_OF2;
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}
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if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) {
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s->next_int |= GPT_SR_OF3;
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}
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if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) {
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s->next_int |= GPT_SR_ROV;
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}
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/* the new range to count down from */
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limit = timeout - imx_gpt_update_count(s);
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if (limit < 0) {
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/*
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* if we reach here, then QEMU is running too slow and we pass the
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* timeout limit while computing it. Let's deliver the interrupt
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* and compute a new limit.
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*/
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s->sr |= s->next_int;
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imx_gpt_compute_next_timeout(s, event);
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imx_gpt_update_int(s);
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} else {
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/* New timeout value */
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s->next_timeout = timeout;
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/* reset the limit to the computed range */
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ptimer_set_limit(s->timer, limit, 1);
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}
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}
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static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)
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{
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IMXGPTState *s = IMX_GPT(opaque);
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uint32_t reg_value = 0;
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switch (offset >> 2) {
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case 0: /* Control Register */
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reg_value = s->cr;
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break;
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case 1: /* prescaler */
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reg_value = s->pr;
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break;
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case 2: /* Status Register */
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reg_value = s->sr;
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break;
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case 3: /* Interrupt Register */
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reg_value = s->ir;
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break;
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case 4: /* Output Compare Register 1 */
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reg_value = s->ocr1;
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break;
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case 5: /* Output Compare Register 2 */
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reg_value = s->ocr2;
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break;
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case 6: /* Output Compare Register 3 */
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reg_value = s->ocr3;
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break;
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case 7: /* input Capture Register 1 */
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qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n",
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TYPE_IMX_GPT, __func__);
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reg_value = s->icr1;
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break;
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case 8: /* input Capture Register 2 */
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qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n",
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TYPE_IMX_GPT, __func__);
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reg_value = s->icr2;
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break;
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case 9: /* cnt */
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imx_gpt_update_count(s);
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reg_value = s->cnt;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
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break;
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}
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DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset >> 2), reg_value);
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return reg_value;
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}
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static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset)
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{
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ptimer_transaction_begin(s->timer);
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/* stop timer */
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ptimer_stop(s->timer);
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/* Soft reset and hard reset differ only in their handling of the CR
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* register -- soft reset preserves the values of some bits there.
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*/
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if (is_soft_reset) {
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/* Clear all CR bits except those that are preserved by soft reset. */
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s->cr &= GPT_CR_EN | GPT_CR_ENMOD | GPT_CR_STOPEN | GPT_CR_DOZEN |
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GPT_CR_WAITEN | GPT_CR_DBGEN |
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(GPT_CR_CLKSRC_MASK << GPT_CR_CLKSRC_SHIFT);
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} else {
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s->cr = 0;
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}
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s->sr = 0;
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s->pr = 0;
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s->ir = 0;
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s->cnt = 0;
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s->ocr1 = GPT_TIMER_MAX;
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s->ocr2 = GPT_TIMER_MAX;
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s->ocr3 = GPT_TIMER_MAX;
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s->icr1 = 0;
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s->icr2 = 0;
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s->next_timeout = GPT_TIMER_MAX;
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s->next_int = 0;
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/* compute new freq */
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imx_gpt_set_freq(s);
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/* reset the limit to GPT_TIMER_MAX */
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ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
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/* if the timer is still enabled, restart it */
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if (s->freq && (s->cr & GPT_CR_EN)) {
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ptimer_run(s->timer, 1);
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}
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ptimer_transaction_commit(s->timer);
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}
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static void imx_gpt_soft_reset(DeviceState *dev)
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{
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IMXGPTState *s = IMX_GPT(dev);
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imx_gpt_reset_common(s, true);
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}
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static void imx_gpt_reset(DeviceState *dev)
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{
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IMXGPTState *s = IMX_GPT(dev);
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imx_gpt_reset_common(s, false);
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}
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static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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IMXGPTState *s = IMX_GPT(opaque);
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uint32_t oldreg;
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DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset >> 2),
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(uint32_t)value);
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switch (offset >> 2) {
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case 0:
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oldreg = s->cr;
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s->cr = value & ~0x7c14;
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if (s->cr & GPT_CR_SWR) { /* force reset */
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/* handle the reset */
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imx_gpt_soft_reset(DEVICE(s));
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} else {
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/* set our freq, as the source might have changed */
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ptimer_transaction_begin(s->timer);
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imx_gpt_set_freq(s);
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if ((oldreg ^ s->cr) & GPT_CR_EN) {
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if (s->cr & GPT_CR_EN) {
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if (s->cr & GPT_CR_ENMOD) {
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s->next_timeout = GPT_TIMER_MAX;
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ptimer_set_count(s->timer, GPT_TIMER_MAX);
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imx_gpt_compute_next_timeout(s, false);
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}
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ptimer_run(s->timer, 1);
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} else {
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/* stop timer */
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ptimer_stop(s->timer);
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}
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}
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ptimer_transaction_commit(s->timer);
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}
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break;
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case 1: /* Prescaler */
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s->pr = value & 0xfff;
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ptimer_transaction_begin(s->timer);
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imx_gpt_set_freq(s);
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ptimer_transaction_commit(s->timer);
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break;
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case 2: /* SR */
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s->sr &= ~(value & 0x3f);
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imx_gpt_update_int(s);
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break;
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case 3: /* IR -- interrupt register */
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s->ir = value & 0x3f;
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imx_gpt_update_int(s);
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ptimer_transaction_begin(s->timer);
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imx_gpt_compute_next_timeout(s, false);
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ptimer_transaction_commit(s->timer);
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break;
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case 4: /* OCR1 -- output compare register */
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s->ocr1 = value;
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ptimer_transaction_begin(s->timer);
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/* In non-freerun mode, reset count when this register is written */
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if (!(s->cr & GPT_CR_FRR)) {
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s->next_timeout = GPT_TIMER_MAX;
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ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
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}
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/* compute the new timeout */
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imx_gpt_compute_next_timeout(s, false);
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ptimer_transaction_commit(s->timer);
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break;
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case 5: /* OCR2 -- output compare register */
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s->ocr2 = value;
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/* compute the new timeout */
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ptimer_transaction_begin(s->timer);
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imx_gpt_compute_next_timeout(s, false);
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ptimer_transaction_commit(s->timer);
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break;
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case 6: /* OCR3 -- output compare register */
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s->ocr3 = value;
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/* compute the new timeout */
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ptimer_transaction_begin(s->timer);
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imx_gpt_compute_next_timeout(s, false);
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ptimer_transaction_commit(s->timer);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
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break;
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}
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}
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static void imx_gpt_timeout(void *opaque)
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{
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IMXGPTState *s = IMX_GPT(opaque);
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DPRINTF("\n");
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s->sr |= s->next_int;
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s->next_int = 0;
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imx_gpt_compute_next_timeout(s, true);
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imx_gpt_update_int(s);
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if (s->freq && (s->cr & GPT_CR_EN)) {
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ptimer_run(s->timer, 1);
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}
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}
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static const MemoryRegionOps imx_gpt_ops = {
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.read = imx_gpt_read,
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.write = imx_gpt_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void imx_gpt_realize(DeviceState *dev, Error **errp)
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{
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IMXGPTState *s = IMX_GPT(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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sysbus_init_irq(sbd, &s->irq);
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memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT,
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0x00001000);
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sysbus_init_mmio(sbd, &s->iomem);
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s->timer = ptimer_init(imx_gpt_timeout, s, PTIMER_POLICY_DEFAULT);
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}
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static void imx_gpt_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = imx_gpt_realize;
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dc->reset = imx_gpt_reset;
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dc->vmsd = &vmstate_imx_timer_gpt;
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dc->desc = "i.MX general timer";
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}
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static void imx25_gpt_init(Object *obj)
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{
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IMXGPTState *s = IMX_GPT(obj);
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|
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s->clocks = imx25_gpt_clocks;
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}
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static void imx31_gpt_init(Object *obj)
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{
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IMXGPTState *s = IMX_GPT(obj);
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|
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s->clocks = imx31_gpt_clocks;
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}
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|
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static void imx6_gpt_init(Object *obj)
|
|
{
|
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IMXGPTState *s = IMX_GPT(obj);
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|
|
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s->clocks = imx6_gpt_clocks;
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|
}
|
|
|
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static void imx7_gpt_init(Object *obj)
|
|
{
|
|
IMXGPTState *s = IMX_GPT(obj);
|
|
|
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s->clocks = imx7_gpt_clocks;
|
|
}
|
|
|
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static const TypeInfo imx25_gpt_info = {
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.name = TYPE_IMX25_GPT,
|
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.parent = TYPE_SYS_BUS_DEVICE,
|
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.instance_size = sizeof(IMXGPTState),
|
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.instance_init = imx25_gpt_init,
|
|
.class_init = imx_gpt_class_init,
|
|
};
|
|
|
|
static const TypeInfo imx31_gpt_info = {
|
|
.name = TYPE_IMX31_GPT,
|
|
.parent = TYPE_IMX25_GPT,
|
|
.instance_init = imx31_gpt_init,
|
|
};
|
|
|
|
static const TypeInfo imx6_gpt_info = {
|
|
.name = TYPE_IMX6_GPT,
|
|
.parent = TYPE_IMX25_GPT,
|
|
.instance_init = imx6_gpt_init,
|
|
};
|
|
|
|
static const TypeInfo imx7_gpt_info = {
|
|
.name = TYPE_IMX7_GPT,
|
|
.parent = TYPE_IMX25_GPT,
|
|
.instance_init = imx7_gpt_init,
|
|
};
|
|
|
|
static void imx_gpt_register_types(void)
|
|
{
|
|
type_register_static(&imx25_gpt_info);
|
|
type_register_static(&imx31_gpt_info);
|
|
type_register_static(&imx6_gpt_info);
|
|
type_register_static(&imx7_gpt_info);
|
|
}
|
|
|
|
type_init(imx_gpt_register_types)
|