304 lines
8.8 KiB
C
304 lines
8.8 KiB
C
/*
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* Copyright (c) 2018, Impinj, Inc.
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*
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* i.MX2 Watchdog IP block
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "qemu/module.h"
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#include "sysemu/watchdog.h"
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#include "migration/vmstate.h"
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#include "hw/qdev-properties.h"
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#include "hw/watchdog/wdt_imx2.h"
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static void imx2_wdt_interrupt(void *opaque)
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{
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IMX2WdtState *s = IMX2_WDT(opaque);
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s->wicr |= IMX2_WDT_WICR_WTIS;
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qemu_set_irq(s->irq, 1);
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}
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static void imx2_wdt_expired(void *opaque)
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{
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IMX2WdtState *s = IMX2_WDT(opaque);
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s->wrsr = IMX2_WDT_WRSR_TOUT;
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/* Perform watchdog action if watchdog is enabled */
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if (s->wcr & IMX2_WDT_WCR_WDE) {
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s->wrsr = IMX2_WDT_WRSR_TOUT;
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watchdog_perform_action();
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}
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}
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static void imx2_wdt_reset(DeviceState *dev)
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{
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IMX2WdtState *s = IMX2_WDT(dev);
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ptimer_transaction_begin(s->timer);
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ptimer_stop(s->timer);
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ptimer_transaction_commit(s->timer);
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if (s->pretimeout_support) {
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ptimer_transaction_begin(s->itimer);
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ptimer_stop(s->itimer);
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ptimer_transaction_commit(s->itimer);
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}
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s->wicr_locked = false;
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s->wcr_locked = false;
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s->wcr_wde_locked = false;
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s->wcr = IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS;
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s->wsr = 0;
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s->wrsr &= ~(IMX2_WDT_WRSR_TOUT | IMX2_WDT_WRSR_SFTW);
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s->wicr = IMX2_WDT_WICR_WICT_DEF;
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s->wmcr = IMX2_WDT_WMCR_PDE;
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}
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static uint64_t imx2_wdt_read(void *opaque, hwaddr addr, unsigned int size)
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{
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IMX2WdtState *s = IMX2_WDT(opaque);
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switch (addr) {
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case IMX2_WDT_WCR:
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return s->wcr;
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case IMX2_WDT_WSR:
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return s->wsr;
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case IMX2_WDT_WRSR:
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return s->wrsr;
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case IMX2_WDT_WICR:
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return s->wicr;
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case IMX2_WDT_WMCR:
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return s->wmcr;
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}
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return 0;
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}
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static void imx_wdt2_update_itimer(IMX2WdtState *s, bool start)
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{
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bool running = (s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT);
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bool enabled = s->wicr & IMX2_WDT_WICR_WIE;
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ptimer_transaction_begin(s->itimer);
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if (start || !enabled) {
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ptimer_stop(s->itimer);
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}
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if (running && enabled) {
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int count = ptimer_get_count(s->timer);
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int pretimeout = s->wicr & IMX2_WDT_WICR_WICT;
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/*
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* Only (re-)start pretimeout timer if its counter value is larger
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* than 0. Otherwise it will fire right away and we'll get an
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* interrupt loop.
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*/
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if (count > pretimeout) {
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ptimer_set_count(s->itimer, count - pretimeout);
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if (start) {
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ptimer_run(s->itimer, 1);
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}
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}
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}
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ptimer_transaction_commit(s->itimer);
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}
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static void imx_wdt2_update_timer(IMX2WdtState *s, bool start)
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{
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ptimer_transaction_begin(s->timer);
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if (start) {
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ptimer_stop(s->timer);
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}
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if ((s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT)) {
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int count = (s->wcr & IMX2_WDT_WCR_WT) >> 8;
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/* A value of 0 reflects one period (0.5s). */
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ptimer_set_count(s->timer, count + 1);
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if (start) {
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ptimer_run(s->timer, 1);
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}
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}
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ptimer_transaction_commit(s->timer);
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if (s->pretimeout_support) {
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imx_wdt2_update_itimer(s, start);
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}
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}
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static void imx2_wdt_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned int size)
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{
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IMX2WdtState *s = IMX2_WDT(opaque);
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switch (addr) {
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case IMX2_WDT_WCR:
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if (s->wcr_locked) {
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value &= ~IMX2_WDT_WCR_LOCK_MASK;
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value |= (s->wicr & IMX2_WDT_WCR_LOCK_MASK);
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}
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s->wcr_locked = true;
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if (s->wcr_wde_locked) {
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value &= ~IMX2_WDT_WCR_WDE;
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value |= (s->wicr & ~IMX2_WDT_WCR_WDE);
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} else if (value & IMX2_WDT_WCR_WDE) {
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s->wcr_wde_locked = true;
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}
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if (s->wcr_wdt_locked) {
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value &= ~IMX2_WDT_WCR_WDT;
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value |= (s->wicr & ~IMX2_WDT_WCR_WDT);
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} else if (value & IMX2_WDT_WCR_WDT) {
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s->wcr_wdt_locked = true;
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}
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s->wcr = value;
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if (!(value & IMX2_WDT_WCR_SRS)) {
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s->wrsr = IMX2_WDT_WRSR_SFTW;
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}
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if (!(value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS)) ||
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(!(value & IMX2_WDT_WCR_WT) && (value & IMX2_WDT_WCR_WDE))) {
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watchdog_perform_action();
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}
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s->wcr |= IMX2_WDT_WCR_SRS;
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imx_wdt2_update_timer(s, true);
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break;
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case IMX2_WDT_WSR:
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if (s->wsr == IMX2_WDT_SEQ1 && value == IMX2_WDT_SEQ2) {
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imx_wdt2_update_timer(s, false);
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}
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s->wsr = value;
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break;
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case IMX2_WDT_WRSR:
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break;
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case IMX2_WDT_WICR:
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if (!s->pretimeout_support) {
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return;
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}
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value &= IMX2_WDT_WICR_LOCK_MASK | IMX2_WDT_WICR_WTIS;
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if (s->wicr_locked) {
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value &= IMX2_WDT_WICR_WTIS;
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value |= (s->wicr & IMX2_WDT_WICR_LOCK_MASK);
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}
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s->wicr = value | (s->wicr & IMX2_WDT_WICR_WTIS);
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if (value & IMX2_WDT_WICR_WTIS) {
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s->wicr &= ~IMX2_WDT_WICR_WTIS;
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qemu_set_irq(s->irq, 0);
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}
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imx_wdt2_update_itimer(s, true);
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s->wicr_locked = true;
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break;
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case IMX2_WDT_WMCR:
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s->wmcr = value & IMX2_WDT_WMCR_PDE;
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break;
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}
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}
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static const MemoryRegionOps imx2_wdt_ops = {
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.read = imx2_wdt_read,
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.write = imx2_wdt_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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/*
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* Our device would not work correctly if the guest was doing
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* unaligned access. This might not be a limitation on the
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* real device but in practice there is no reason for a guest
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* to access this device unaligned.
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*/
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.min_access_size = 2,
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.max_access_size = 2,
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.unaligned = false,
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},
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};
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static const VMStateDescription vmstate_imx2_wdt = {
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.name = "imx2.wdt",
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.fields = (VMStateField[]) {
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VMSTATE_PTIMER(timer, IMX2WdtState),
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VMSTATE_PTIMER(itimer, IMX2WdtState),
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VMSTATE_BOOL(wicr_locked, IMX2WdtState),
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VMSTATE_BOOL(wcr_locked, IMX2WdtState),
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VMSTATE_BOOL(wcr_wde_locked, IMX2WdtState),
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VMSTATE_BOOL(wcr_wdt_locked, IMX2WdtState),
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VMSTATE_UINT16(wcr, IMX2WdtState),
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VMSTATE_UINT16(wsr, IMX2WdtState),
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VMSTATE_UINT16(wrsr, IMX2WdtState),
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VMSTATE_UINT16(wmcr, IMX2WdtState),
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VMSTATE_UINT16(wicr, IMX2WdtState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void imx2_wdt_realize(DeviceState *dev, Error **errp)
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{
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IMX2WdtState *s = IMX2_WDT(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init_io(&s->mmio, OBJECT(dev),
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&imx2_wdt_ops, s,
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TYPE_IMX2_WDT,
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IMX2_WDT_MMIO_SIZE);
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sysbus_init_mmio(sbd, &s->mmio);
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sysbus_init_irq(sbd, &s->irq);
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s->timer = ptimer_init(imx2_wdt_expired, s,
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PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
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PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
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PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
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ptimer_transaction_begin(s->timer);
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ptimer_set_freq(s->timer, 2);
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ptimer_set_limit(s->timer, 0xff, 1);
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ptimer_transaction_commit(s->timer);
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if (s->pretimeout_support) {
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s->itimer = ptimer_init(imx2_wdt_interrupt, s,
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PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
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PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
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PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
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ptimer_transaction_begin(s->itimer);
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ptimer_set_freq(s->itimer, 2);
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ptimer_set_limit(s->itimer, 0xff, 1);
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ptimer_transaction_commit(s->itimer);
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}
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}
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static Property imx2_wdt_properties[] = {
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DEFINE_PROP_BOOL("pretimeout-support", IMX2WdtState, pretimeout_support,
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false),
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DEFINE_PROP_END_OF_LIST()
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};
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static void imx2_wdt_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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device_class_set_props(dc, imx2_wdt_properties);
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dc->realize = imx2_wdt_realize;
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dc->reset = imx2_wdt_reset;
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dc->vmsd = &vmstate_imx2_wdt;
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dc->desc = "i.MX watchdog timer";
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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}
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static const TypeInfo imx2_wdt_info = {
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.name = TYPE_IMX2_WDT,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMX2WdtState),
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.class_init = imx2_wdt_class_init,
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};
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static WatchdogTimerModel model = {
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.wdt_name = "imx2-watchdog",
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.wdt_description = "i.MX2 Watchdog",
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};
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static void imx2_wdt_register_type(void)
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{
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watchdog_add_model(&model);
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type_register_static(&imx2_wdt_info);
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}
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type_init(imx2_wdt_register_type)
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