218 lines
7.4 KiB
C
218 lines
7.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000, 07 MIPS Technologies, Inc.
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* Copyright (C) 2016 Imagination Technologies
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*
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*/
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#ifndef MIPS_GIC_H
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#define MIPS_GIC_H
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#include "qemu/units.h"
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#include "hw/timer/mips_gictimer.h"
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#include "hw/sysbus.h"
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#include "cpu.h"
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/*
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* GIC Specific definitions
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*/
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/* The MIPS default location */
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#define GIC_BASE_ADDR 0x1bdc0000ULL
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#define GIC_ADDRSPACE_SZ (128 * KiB)
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/* Constants */
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#define GIC_POL_POS 1
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#define GIC_POL_NEG 0
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#define GIC_TRIG_EDGE 1
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#define GIC_TRIG_LEVEL 0
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#define MSK(n) ((1ULL << (n)) - 1)
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/* GIC Address Space */
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#define SHARED_SECTION_OFS 0x0000
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#define SHARED_SECTION_SIZE 0x8000
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#define VP_LOCAL_SECTION_OFS 0x8000
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#define VP_LOCAL_SECTION_SIZE 0x4000
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#define VP_OTHER_SECTION_OFS 0xc000
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#define VP_OTHER_SECTION_SIZE 0x4000
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#define USM_VISIBLE_SECTION_OFS 0x10000
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#define USM_VISIBLE_SECTION_SIZE 0x10000
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/* Register Map for Shared Section */
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#define GIC_SH_CONFIG_OFS 0x0000
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/* Shared Global Counter */
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#define GIC_SH_COUNTERLO_OFS 0x0010
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#define GIC_SH_COUNTERHI_OFS 0x0014
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#define GIC_SH_REVISIONID_OFS 0x0020
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/* Set/Clear corresponding bit in Edge Detect Register */
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#define GIC_SH_WEDGE_OFS 0x0280
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/* Reset Mask - Disables Interrupt */
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#define GIC_SH_RMASK_OFS 0x0300
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#define GIC_SH_RMASK_LAST_OFS 0x031c
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/* Set Mask (WO) - Enables Interrupt */
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#define GIC_SH_SMASK_OFS 0x0380
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#define GIC_SH_SMASK_LAST_OFS 0x039c
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/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
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#define GIC_SH_MASK_OFS 0x0400
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#define GIC_SH_MASK_LAST_OFS 0x041c
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/* Pending Global Interrupts (RO) */
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#define GIC_SH_PEND_OFS 0x0480
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#define GIC_SH_PEND_LAST_OFS 0x049c
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#define GIC_SH_MAP0_PIN_OFS 0x0500
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#define GIC_SH_MAP255_PIN_OFS 0x08fc
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#define GIC_SH_MAP0_VP_OFS 0x2000
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#define GIC_SH_MAP255_VP_LAST_OFS 0x3fe4
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/* Register Map for Local Section */
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#define GIC_VP_CTL_OFS 0x0000
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#define GIC_VP_PEND_OFS 0x0004
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#define GIC_VP_MASK_OFS 0x0008
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#define GIC_VP_RMASK_OFS 0x000c
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#define GIC_VP_SMASK_OFS 0x0010
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#define GIC_VP_WD_MAP_OFS 0x0040
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#define GIC_VP_COMPARE_MAP_OFS 0x0044
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#define GIC_VP_TIMER_MAP_OFS 0x0048
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#define GIC_VP_FDC_MAP_OFS 0x004c
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#define GIC_VP_PERFCTR_MAP_OFS 0x0050
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#define GIC_VP_SWINT0_MAP_OFS 0x0054
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#define GIC_VP_SWINT1_MAP_OFS 0x0058
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#define GIC_VP_OTHER_ADDR_OFS 0x0080
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#define GIC_VP_IDENT_OFS 0x0088
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#define GIC_VP_WD_CONFIG0_OFS 0x0090
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#define GIC_VP_WD_COUNT0_OFS 0x0094
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#define GIC_VP_WD_INITIAL0_OFS 0x0098
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#define GIC_VP_COMPARE_LO_OFS 0x00a0
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#define GIC_VP_COMPARE_HI_OFS 0x00a4
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#define GIC_VL_BRK_GROUP 0x3080
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/* User-Mode Visible Section Register */
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/* Read-only alias for GIC Shared CounterLo */
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#define GIC_USER_MODE_COUNTERLO 0x0000
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/* Read-only alias for GIC Shared CounterHi */
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#define GIC_USER_MODE_COUNTERHI 0x0004
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/* Masks */
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#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
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#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
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#define GIC_SH_CONFIG_COUNTBITS_SHF 24
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#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
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#define GIC_SH_CONFIG_NUMINTRS_SHF 16
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#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
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#define GIC_SH_CONFIG_PVPS_SHF 0
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#define GIC_SH_CONFIG_PVPS_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPS_SHF)
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#define GIC_SH_WEDGE_RW_SHF 31
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#define GIC_SH_WEDGE_RW_MSK (MSK(1) << GIC_SH_WEDGE_RW_SHF)
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#define GIC_MAP_TO_PIN_SHF 31
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#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
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#define GIC_MAP_TO_NMI_SHF 30
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#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
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#define GIC_MAP_TO_YQ_SHF 29
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#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
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#define GIC_MAP_SHF 0
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#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
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#define GIC_MAP_TO_PIN_REG_MSK \
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(GIC_MAP_TO_PIN_MSK | GIC_MAP_TO_NMI_MSK | GIC_MAP_TO_YQ_MSK | GIC_MAP_MSK)
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/* GIC_VP_CTL Masks */
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#define GIC_VP_CTL_FDC_RTBL_SHF 4
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#define GIC_VP_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VP_CTL_FDC_RTBL_SHF)
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#define GIC_VP_CTL_SWINT_RTBL_SHF 3
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#define GIC_VP_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VP_CTL_SWINT_RTBL_SHF)
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#define GIC_VP_CTL_PERFCNT_RTBL_SHF 2
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#define GIC_VP_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VP_CTL_PERFCNT_RTBL_SHF)
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#define GIC_VP_CTL_TIMER_RTBL_SHF 1
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#define GIC_VP_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VP_CTL_TIMER_RTBL_SHF)
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#define GIC_VP_CTL_EIC_MODE_SHF 0
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#define GIC_VP_CTL_EIC_MODE_MSK (MSK(1) << GIC_VP_CTL_EIC_MODE_SHF)
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/* GIC_VP_MASK Masks */
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#define GIC_VP_MASK_FDC_SHF 6
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#define GIC_VP_MASK_FDC_MSK (MSK(1) << GIC_VP_MASK_FDC_SHF)
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#define GIC_VP_MASK_SWINT1_SHF 5
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#define GIC_VP_MASK_SWINT1_MSK (MSK(1) << GIC_VP_MASK_SWINT1_SHF)
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#define GIC_VP_MASK_SWINT0_SHF 4
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#define GIC_VP_MASK_SWINT0_MSK (MSK(1) << GIC_VP_MASK_SWINT0_SHF)
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#define GIC_VP_MASK_PERFCNT_SHF 3
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#define GIC_VP_MASK_PERFCNT_MSK (MSK(1) << GIC_VP_MASK_PERFCNT_SHF)
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#define GIC_VP_MASK_TIMER_SHF 2
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#define GIC_VP_MASK_TIMER_MSK (MSK(1) << GIC_VP_MASK_TIMER_SHF)
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#define GIC_VP_MASK_CMP_SHF 1
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#define GIC_VP_MASK_CMP_MSK (MSK(1) << GIC_VP_MASK_CMP_SHF)
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#define GIC_VP_MASK_WD_SHF 0
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#define GIC_VP_MASK_WD_MSK (MSK(1) << GIC_VP_MASK_WD_SHF)
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#define GIC_VP_SET_RESET_MSK (MSK(7) << GIC_VP_MASK_WD_SHF)
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#define GIC_CPU_INT_MAX 5 /* Core Interrupt 7 */
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#define GIC_CPU_PIN_OFFSET 2
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/* Local GIC interrupts. */
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#define GIC_NUM_LOCAL_INTRS 7
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#define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */
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#define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */
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#define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */
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#define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */
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#define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */
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#define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */
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#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */
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#define TYPE_MIPS_GIC "mips-gic"
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#define MIPS_GIC(obj) OBJECT_CHECK(MIPSGICState, (obj), TYPE_MIPS_GIC)
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/* Support up to 32 VPs and 256 IRQs */
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#define GIC_MAX_VPS 32
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#define GIC_MAX_INTRS 256
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typedef struct MIPSGICState MIPSGICState;
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typedef struct MIPSGICIRQState MIPSGICIRQState;
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typedef struct MIPSGICVPState MIPSGICVPState;
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struct MIPSGICIRQState {
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uint8_t enabled;
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uint8_t pending;
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uint32_t map_pin;
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int32_t map_vp;
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qemu_irq irq;
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};
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struct MIPSGICVPState {
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uint32_t ctl;
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uint32_t pend;
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uint32_t mask;
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uint32_t compare_map;
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uint32_t other_addr;
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CPUMIPSState *env;
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};
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struct MIPSGICState {
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SysBusDevice parent_obj;
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MemoryRegion mr;
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/* Shared Section Registers */
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uint32_t sh_config;
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MIPSGICIRQState *irq_state;
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/* VP Local/Other Section Registers */
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MIPSGICVPState *vps;
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/* GIC VP Timer */
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MIPSGICTimerState *gic_timer;
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int32_t num_vps;
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int32_t num_irq;
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};
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#endif /* MIPS_GIC_H */
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