377 lines
10 KiB
C
377 lines
10 KiB
C
/** @file
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*
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* Copyright (c) 2011-2018, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <Base.h>
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#include <Library/ArmGicLib.h>
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#include <Library/ArmLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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// In GICv3, there are 2 x 64KB frames:
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// Redistributor control frame + SGI Control & Generation frame
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#define GIC_V3_REDISTRIBUTOR_GRANULARITY (ARM_GICR_CTLR_FRAME_SIZE \
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+ ARM_GICR_SGI_PPI_FRAME_SIZE)
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// In GICv4, there are 2 additional 64KB frames:
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// VLPI frame + Reserved page frame
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#define GIC_V4_REDISTRIBUTOR_GRANULARITY (GIC_V3_REDISTRIBUTOR_GRANULARITY \
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+ ARM_GICR_SGI_VLPI_FRAME_SIZE \
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+ ARM_GICR_SGI_RESERVED_FRAME_SIZE)
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#define ISENABLER_ADDRESS(base,offset) ((base) + \
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ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * offset))
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#define ICENABLER_ADDRESS(base,offset) ((base) + \
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ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + (4 * offset))
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/**
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*
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* Return whether the Source interrupt index refers to a shared interrupt (SPI)
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*/
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STATIC
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BOOLEAN
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SourceIsSpi (
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IN UINTN Source
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)
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{
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return Source >= 32 && Source < 1020;
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}
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/**
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* Return the base address of the GIC redistributor for the current CPU
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*
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* @param Revision GIC Revision. The GIC redistributor might have a different
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* granularity following the GIC revision.
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*
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* @retval Base address of the associated GIC Redistributor
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*/
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STATIC
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UINTN
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GicGetCpuRedistributorBase (
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IN UINTN GicRedistributorBase,
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IN ARM_GIC_ARCH_REVISION Revision
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)
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{
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UINTN MpId;
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UINTN CpuAffinity;
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UINTN Affinity;
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UINTN GicCpuRedistributorBase;
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UINT64 TypeRegister;
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MpId = ArmReadMpidr ();
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// Define CPU affinity as:
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// Affinity0[0:8], Affinity1[9:15], Affinity2[16:23], Affinity3[24:32]
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// whereas Affinity3 is defined at [32:39] in MPIDR
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CpuAffinity = (MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) |
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((MpId & ARM_CORE_AFF3) >> 8);
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if (Revision < ARM_GIC_ARCH_REVISION_3) {
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ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
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return 0;
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}
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GicCpuRedistributorBase = GicRedistributorBase;
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do {
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TypeRegister = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER);
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Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);
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if (Affinity == CpuAffinity) {
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return GicCpuRedistributorBase;
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}
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// Move to the next GIC Redistributor frame.
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// The GIC specification does not forbid a mixture of redistributors
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// with or without support for virtual LPIs, so we test Virtual LPIs
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// Support (VLPIS) bit for each frame to decide the granularity.
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// Note: The assumption here is that the redistributors are adjacent
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// for all CPUs. However this may not be the case for NUMA systems.
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GicCpuRedistributorBase += (((ARM_GICR_TYPER_VLPIS & TypeRegister) != 0)
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? GIC_V4_REDISTRIBUTOR_GRANULARITY
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: GIC_V3_REDISTRIBUTOR_GRANULARITY);
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} while ((TypeRegister & ARM_GICR_TYPER_LAST) == 0);
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// The Redistributor has not been found for the current CPU
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ASSERT_EFI_ERROR (EFI_NOT_FOUND);
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return 0;
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}
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UINTN
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EFIAPI
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ArmGicGetInterfaceIdentification (
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IN INTN GicInterruptInterfaceBase
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)
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{
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// Read the GIC Identification Register
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return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR);
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}
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UINTN
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EFIAPI
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ArmGicGetMaxNumInterrupts (
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IN INTN GicDistributorBase
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)
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{
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return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
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}
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VOID
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EFIAPI
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ArmGicSendSgiTo (
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IN INTN GicDistributorBase,
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IN INTN TargetListFilter,
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IN INTN CPUTargetList,
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IN INTN SgiId
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)
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{
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MmioWrite32 (
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GicDistributorBase + ARM_GIC_ICDSGIR,
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((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId
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);
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}
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/*
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* Acknowledge and return the value of the Interrupt Acknowledge Register
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*
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* InterruptId is returned separately from the register value because in
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* the GICv2 the register value contains the CpuId and InterruptId while
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* in the GICv3 the register value is only the InterruptId.
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*
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* @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface
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* @param InterruptId InterruptId read from the Interrupt
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* Acknowledge Register
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*
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* @retval value returned by the Interrupt Acknowledge Register
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*
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*/
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UINTN
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EFIAPI
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ArmGicAcknowledgeInterrupt (
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IN UINTN GicInterruptInterfaceBase,
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OUT UINTN *InterruptId
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)
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{
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UINTN Value;
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ARM_GIC_ARCH_REVISION Revision;
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Revision = ArmGicGetSupportedArchRevision ();
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if (Revision == ARM_GIC_ARCH_REVISION_2) {
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Value = ArmGicV2AcknowledgeInterrupt (GicInterruptInterfaceBase);
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// InterruptId is required for the caller to know if a valid or spurious
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// interrupt has been read
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ASSERT (InterruptId != NULL);
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if (InterruptId != NULL) {
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*InterruptId = Value & ARM_GIC_ICCIAR_ACKINTID;
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}
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} else if (Revision == ARM_GIC_ARCH_REVISION_3) {
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Value = ArmGicV3AcknowledgeInterrupt ();
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} else {
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ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
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// Report Spurious interrupt which is what the above controllers would
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// return if no interrupt was available
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Value = 1023;
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}
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return Value;
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}
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VOID
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EFIAPI
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ArmGicEndOfInterrupt (
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IN UINTN GicInterruptInterfaceBase,
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IN UINTN Source
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)
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{
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ARM_GIC_ARCH_REVISION Revision;
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Revision = ArmGicGetSupportedArchRevision ();
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if (Revision == ARM_GIC_ARCH_REVISION_2) {
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ArmGicV2EndOfInterrupt (GicInterruptInterfaceBase, Source);
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} else if (Revision == ARM_GIC_ARCH_REVISION_3) {
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ArmGicV3EndOfInterrupt (Source);
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} else {
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ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
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}
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}
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VOID
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EFIAPI
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ArmGicEnableInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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// Calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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Revision = ArmGicGetSupportedArchRevision ();
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if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
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FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
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SourceIsSpi (Source)) {
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// Write set-enable register
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MmioWrite32 (
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GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset),
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1 << RegShift
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);
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} else {
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GicCpuRedistributorBase = GicGetCpuRedistributorBase (
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GicRedistributorBase,
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Revision
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);
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if (GicCpuRedistributorBase == 0) {
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ASSERT_EFI_ERROR (EFI_NOT_FOUND);
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return;
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}
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// Write set-enable register
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MmioWrite32 (
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ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),
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1 << RegShift
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);
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}
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}
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VOID
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EFIAPI
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ArmGicDisableInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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// Calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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Revision = ArmGicGetSupportedArchRevision ();
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if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
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FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
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SourceIsSpi (Source)) {
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// Write clear-enable register
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MmioWrite32 (
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GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset),
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1 << RegShift
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);
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} else {
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GicCpuRedistributorBase = GicGetCpuRedistributorBase (
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GicRedistributorBase,
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Revision
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);
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if (GicCpuRedistributorBase == 0) {
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return;
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}
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// Write clear-enable register
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MmioWrite32 (
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ICENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),
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1 << RegShift
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);
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}
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}
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BOOLEAN
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EFIAPI
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ArmGicIsInterruptEnabled (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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UINT32 Interrupts;
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// Calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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Revision = ArmGicGetSupportedArchRevision ();
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if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
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FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
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SourceIsSpi (Source)) {
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Interrupts = ((MmioRead32 (
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GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)
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)
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& (1 << RegShift)) != 0);
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} else {
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GicCpuRedistributorBase = GicGetCpuRedistributorBase (
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GicRedistributorBase,
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Revision
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);
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if (GicCpuRedistributorBase == 0) {
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return 0;
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}
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// Read set-enable register
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Interrupts = MmioRead32 (
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ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset)
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);
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}
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return ((Interrupts & (1 << RegShift)) != 0);
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}
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VOID
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EFIAPI
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ArmGicDisableDistributor (
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IN INTN GicDistributorBase
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)
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{
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// Disable Gic Distributor
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0);
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}
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VOID
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EFIAPI
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ArmGicEnableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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)
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{
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ARM_GIC_ARCH_REVISION Revision;
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Revision = ArmGicGetSupportedArchRevision ();
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if (Revision == ARM_GIC_ARCH_REVISION_2) {
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ArmGicV2EnableInterruptInterface (GicInterruptInterfaceBase);
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} else if (Revision == ARM_GIC_ARCH_REVISION_3) {
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ArmGicV3EnableInterruptInterface ();
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} else {
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ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
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}
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}
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VOID
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EFIAPI
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ArmGicDisableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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)
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{
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ARM_GIC_ARCH_REVISION Revision;
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Revision = ArmGicGetSupportedArchRevision ();
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if (Revision == ARM_GIC_ARCH_REVISION_2) {
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ArmGicV2DisableInterruptInterface (GicInterruptInterfaceBase);
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} else if (Revision == ARM_GIC_ARCH_REVISION_3) {
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ArmGicV3DisableInterruptInterface ();
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} else {
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ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
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}
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}
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