697 lines
18 KiB
C
697 lines
18 KiB
C
/** @file
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Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi.h>
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#include <Library/BaseLib.h>
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#include <Library/CacheLib.h>
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#include <Library/CacheAsRamLib.h>
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#include "CacheLibInternal.h"
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/**
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Search the memory cache type for specific memory from MTRR.
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@param[in] MemoryAddress the address of target memory
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@param[in] MemoryLength the length of target memory
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@param[in] ValidMtrrAddressMask the MTRR address mask
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@param[out] UsedMsrNum the used MSR number
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@param[out] UsedMemoryCacheType the cache type for the target memory
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@retval EFI_SUCCESS The memory is found in MTRR and cache type is returned
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@retval EFI_NOT_FOUND The memory is not found in MTRR
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**/
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EFI_STATUS
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SearchForExactMtrr (
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IN EFI_PHYSICAL_ADDRESS MemoryAddress,
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IN UINT64 MemoryLength,
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IN UINT64 ValidMtrrAddressMask,
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OUT UINT32 *UsedMsrNum,
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OUT EFI_MEMORY_CACHE_TYPE *MemoryCacheType
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);
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/**
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Check if CacheType match current default setting.
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@param[in] MemoryCacheType input cache type to be checked.
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@retval TRUE MemoryCacheType is default MTRR setting.
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@retval FALSE MemoryCacheType is NOT default MTRR setting.
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**/
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BOOLEAN
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IsDefaultType (
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IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
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);
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/**
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Return MTRR alignment requirement for base address and size.
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@param[in] BaseAddress Base address.
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@param[in] Size Size.
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@retval Zero Alligned.
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@retval Non-Zero Not alligned.
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**/
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UINT32
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CheckMtrrAlignment (
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IN UINT64 BaseAddress,
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IN UINT64 Size
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);
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typedef struct {
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UINT32 Msr;
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UINT32 BaseAddress;
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UINT32 Length;
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} EFI_FIXED_MTRR;
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EFI_FIXED_MTRR mFixedMtrrTable[] = {
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{ EFI_MSR_IA32_MTRR_FIX64K_00000, 0, 0x10000},
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{ EFI_MSR_IA32_MTRR_FIX16K_80000, 0x80000, 0x4000},
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{ EFI_MSR_IA32_MTRR_FIX16K_A0000, 0xA0000, 0x4000},
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{ EFI_MSR_IA32_MTRR_FIX4K_C0000, 0xC0000, 0x1000},
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{ EFI_MSR_IA32_MTRR_FIX4K_C8000, 0xC8000, 0x1000},
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{ EFI_MSR_IA32_MTRR_FIX4K_D0000, 0xD0000, 0x1000},
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{ EFI_MSR_IA32_MTRR_FIX4K_D8000, 0xD8000, 0x1000},
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{ EFI_MSR_IA32_MTRR_FIX4K_E0000, 0xE0000, 0x1000},
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{ EFI_MSR_IA32_MTRR_FIX4K_E8000, 0xE8000, 0x1000},
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{ EFI_MSR_IA32_MTRR_FIX4K_F0000, 0xF0000, 0x1000},
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{ EFI_MSR_IA32_MTRR_FIX4K_F8000, 0xF8000, 0x1000}
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};
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/**
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Given the input, check if the number of MTRR is lesser.
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if positive or subtractive.
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@param[in] Input Length of Memory to program MTRR.
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@retval Zero do positive.
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@retval Non-Zero do subtractive.
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**/
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INT8
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CheckDirection (
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IN UINT64 Input
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)
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{
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return 0;
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}
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/**
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Disable cache and its mtrr.
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@param[out] OldMtrr To return the Old MTRR value
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**/
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VOID
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EfiDisableCacheMtrr (
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OUT UINT64 *OldMtrr
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)
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{
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UINT64 TempQword;
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//
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// Disable Cache MTRR
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//
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*OldMtrr = AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE);
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TempQword = (*OldMtrr) & ~B_EFI_MSR_GLOBAL_MTRR_ENABLE & ~B_EFI_MSR_FIXED_MTRR_ENABLE;
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AsmWriteMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, TempQword);
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AsmDisableCache ();
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}
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/**
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Recover cache MTRR.
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@param[in] EnableMtrr Whether to enable the MTRR
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@param[in] OldMtrr The saved old MTRR value to restore when not to enable the MTRR
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**/
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VOID
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EfiRecoverCacheMtrr (
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IN BOOLEAN EnableMtrr,
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IN UINT64 OldMtrr
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)
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{
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UINT64 TempQword;
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//
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// Enable Cache MTRR
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//
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if (EnableMtrr) {
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TempQword = AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE);
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TempQword |= (UINT64)(B_EFI_MSR_GLOBAL_MTRR_ENABLE | B_EFI_MSR_FIXED_MTRR_ENABLE);
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} else {
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TempQword = OldMtrr;
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}
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AsmWriteMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, TempQword);
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AsmEnableCache ();
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}
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/**
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Programming MTRR according to Memory address, length, and type.
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@param[in] MtrrNumber the variable MTRR index number
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@param[in] MemoryAddress the address of target memory
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@param[in] MemoryLength the length of target memory
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@param[in] MemoryCacheType the cache type of target memory
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@param[in] ValidMtrrAddressMask the MTRR address mask
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**/
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VOID
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EfiProgramMtrr (
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IN UINTN MtrrNumber,
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IN EFI_PHYSICAL_ADDRESS MemoryAddress,
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IN UINT64 MemoryLength,
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IN EFI_MEMORY_CACHE_TYPE MemoryCacheType,
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IN UINT64 ValidMtrrAddressMask
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)
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{
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UINT64 TempQword;
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UINT64 OldMtrr;
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if (MemoryLength == 0) {
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return;
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}
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EfiDisableCacheMtrr (&OldMtrr);
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//
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// MTRR Physical Base
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//
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TempQword = (MemoryAddress & ValidMtrrAddressMask) | MemoryCacheType;
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AsmWriteMsr64 (MtrrNumber, TempQword);
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//
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// MTRR Physical Mask
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//
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TempQword = ~(MemoryLength - 1);
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AsmWriteMsr64 (MtrrNumber + 1, (TempQword & ValidMtrrAddressMask) | B_EFI_MSR_CACHE_MTRR_VALID);
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EfiRecoverCacheMtrr (TRUE, OldMtrr);
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}
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/**
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Calculate the maximum value which is a power of 2, but less the MemoryLength.
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@param[in] MemoryAddress Memory address.
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@param[in] MemoryLength The number to pass in.
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@return The maximum value which is align to power of 2 and less the MemoryLength
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**/
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UINT64
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Power2MaxMemory (
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IN UINT64 MemoryAddress,
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IN UINT64 MemoryLength
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)
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{
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UINT64 Result;
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if (MemoryLength == 0) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// Compute inital power of 2 size to return
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//
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Result = GetPowerOfTwo64(MemoryLength);
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//
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// Special case base of 0 as all ranges are valid
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//
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if (MemoryAddress == 0) {
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return Result;
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}
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//
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// Loop till a value that can be mapped to this base address is found
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//
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while (CheckMtrrAlignment (MemoryAddress, Result) != 0) {
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//
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// Need to try the next smaller power of 2
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//
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Result = RShiftU64 (Result, 1);
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}
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return Result;
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}
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/**
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Return MTRR alignment requirement for base address and size.
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@param[in] BaseAddress Base address.
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@param[in] Size Size.
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@retval Zero Alligned.
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@retval Non-Zero Not alligned.
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**/
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UINT32
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CheckMtrrAlignment (
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IN UINT64 BaseAddress,
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IN UINT64 Size
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)
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{
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UINT32 ShiftedBase;
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UINT32 ShiftedSize;
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//
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// Shift base and size right 12 bits to allow for larger memory sizes. The
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// MTRRs do not use the first 12 bits so this is safe for now. Only supports
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// up to 52 bits of physical address space.
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//
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ShiftedBase = (UINT32) RShiftU64 (BaseAddress, 12);
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ShiftedSize = (UINT32) RShiftU64 (Size, 12);
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//
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// Return the results to the caller of the MOD
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//
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return ShiftedBase % ShiftedSize;
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}
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/**
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Programs fixed MTRRs registers.
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@param[in] MemoryCacheType The memory type to set.
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@param[in] Base The base address of memory range.
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@param[in] Length The length of memory range.
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@retval RETURN_SUCCESS The cache type was updated successfully
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@retval RETURN_UNSUPPORTED The requested range or cache type was invalid
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for the fixed MTRRs.
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**/
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EFI_STATUS
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ProgramFixedMtrr (
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IN EFI_MEMORY_CACHE_TYPE MemoryCacheType,
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IN UINT64 *Base,
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IN UINT64 *Len
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)
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{
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UINT32 MsrNum;
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UINT32 ByteShift;
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UINT64 TempQword;
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UINT64 OrMask;
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UINT64 ClearMask;
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TempQword = 0;
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OrMask = 0;
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ClearMask = 0;
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for (MsrNum = 0; MsrNum < V_EFI_FIXED_MTRR_NUMBER; MsrNum++) {
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if ((*Base >= mFixedMtrrTable[MsrNum].BaseAddress) &&
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(*Base < (mFixedMtrrTable[MsrNum].BaseAddress + 8 * mFixedMtrrTable[MsrNum].Length))) {
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break;
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}
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}
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if (MsrNum == V_EFI_FIXED_MTRR_NUMBER ) {
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return EFI_DEVICE_ERROR;
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}
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//
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// We found the fixed MTRR to be programmed
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//
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for (ByteShift=0; ByteShift < 8; ByteShift++) {
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if ( *Base == (mFixedMtrrTable[MsrNum].BaseAddress + ByteShift * mFixedMtrrTable[MsrNum].Length)) {
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break;
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}
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}
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if (ByteShift == 8 ) {
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return EFI_DEVICE_ERROR;
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}
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for (; ((ByteShift<8) && (*Len >= mFixedMtrrTable[MsrNum].Length));ByteShift++) {
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OrMask |= LShiftU64((UINT64) MemoryCacheType, (UINT32) (ByteShift* 8));
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ClearMask |= LShiftU64((UINT64) 0xFF, (UINT32) (ByteShift * 8));
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*Len -= mFixedMtrrTable[MsrNum].Length;
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*Base += mFixedMtrrTable[MsrNum].Length;
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}
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TempQword = (AsmReadMsr64 (mFixedMtrrTable[MsrNum].Msr) & (~ClearMask)) | OrMask;
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AsmWriteMsr64 (mFixedMtrrTable[MsrNum].Msr, TempQword);
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return EFI_SUCCESS;
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}
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/**
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Check if there is a valid variable MTRR that overlaps the given range.
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@param[in] Start Base Address of the range to check.
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@param[in] End End address of the range to check.
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@retval TRUE Mtrr overlap.
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@retval FALSE Mtrr not overlap.
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**/
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BOOLEAN
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CheckMtrrOverlap (
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IN EFI_PHYSICAL_ADDRESS Start,
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IN EFI_PHYSICAL_ADDRESS End
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)
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{
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return FALSE;
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}
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/**
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Given the memory range and cache type, programs the MTRRs.
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@param[in] MemoryAddress Base Address of Memory to program MTRR.
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@param[in] MemoryLength Length of Memory to program MTRR.
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@param[in] MemoryCacheType Cache Type.
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@retval EFI_SUCCESS Mtrr are set successfully.
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@retval EFI_LOAD_ERROR No empty MTRRs to use.
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@retval EFI_INVALID_PARAMETER The input parameter is not valid.
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@retval others An error occurs when setting MTTR.
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**/
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EFI_STATUS
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EFIAPI
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SetCacheAttributes (
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IN EFI_PHYSICAL_ADDRESS MemoryAddress,
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IN UINT64 MemoryLength,
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IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
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)
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{
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EFI_STATUS Status;
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UINT32 MsrNum, MsrNumEnd;
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UINT64 TempQword;
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UINT32 LastVariableMtrrForBios;
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UINT64 OldMtrr;
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UINT32 UsedMsrNum;
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EFI_MEMORY_CACHE_TYPE UsedMemoryCacheType;
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UINT64 ValidMtrrAddressMask;
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UINT32 Cpuid_RegEax;
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AsmCpuid (CPUID_EXTENDED_FUNCTION, &Cpuid_RegEax, NULL, NULL, NULL);
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if (Cpuid_RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {
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AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Cpuid_RegEax, NULL, NULL, NULL);
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ValidMtrrAddressMask = (LShiftU64((UINT64) 1, (Cpuid_RegEax & 0xFF)) - 1) & (~(UINT64)0x0FFF);
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} else {
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ValidMtrrAddressMask = (LShiftU64((UINT64) 1, 36) - 1) & (~(UINT64)0x0FFF);
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}
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//
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// Check for invalid parameter
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//
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if ((MemoryAddress & ~ValidMtrrAddressMask) != 0 || (MemoryLength & ~ValidMtrrAddressMask) != 0) {
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return EFI_INVALID_PARAMETER;
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}
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if (MemoryLength == 0) {
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return EFI_INVALID_PARAMETER;
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}
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switch (MemoryCacheType) {
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case EFI_CACHE_UNCACHEABLE:
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case EFI_CACHE_WRITECOMBINING:
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case EFI_CACHE_WRITETHROUGH:
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case EFI_CACHE_WRITEPROTECTED:
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case EFI_CACHE_WRITEBACK:
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break;
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default:
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return EFI_INVALID_PARAMETER;
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}
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//
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// Check if Fixed MTRR
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//
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if ((MemoryAddress + MemoryLength) <= (1 << 20)) {
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Status = EFI_SUCCESS;
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EfiDisableCacheMtrr (&OldMtrr);
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while ((MemoryLength > 0) && (Status == EFI_SUCCESS)) {
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Status = ProgramFixedMtrr (MemoryCacheType, &MemoryAddress, &MemoryLength);
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}
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EfiRecoverCacheMtrr (TRUE, OldMtrr);
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return Status;
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}
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//
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// Search if the range attribute has been set before
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//
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Status = SearchForExactMtrr(
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MemoryAddress,
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MemoryLength,
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ValidMtrrAddressMask,
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&UsedMsrNum,
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&UsedMemoryCacheType
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);
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if (!EFI_ERROR(Status)) {
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//
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// Compare if it has the same type as current setting
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//
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if (UsedMemoryCacheType == MemoryCacheType) {
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return EFI_SUCCESS;
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} else {
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//
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// Different type
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//
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//
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// Check if the set type is the same as Default Type
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//
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if (IsDefaultType(MemoryCacheType)) {
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//
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// Clear the MTRR
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//
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AsmWriteMsr64(UsedMsrNum, 0);
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AsmWriteMsr64(UsedMsrNum + 1, 0);
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return EFI_SUCCESS;
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} else {
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//
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// Modify the MTRR type
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//
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EfiProgramMtrr(UsedMsrNum,
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MemoryAddress,
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MemoryLength,
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MemoryCacheType,
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ValidMtrrAddressMask
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);
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return EFI_SUCCESS;
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}
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}
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}
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#if 0
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//
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// @bug - Need to create memory map so that when checking for overlap we
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// can determine if an overlap exists based on all caching requests.
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//
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// Don't waste a variable MTRR if the caching attrib is same as default in MTRR_DEF_TYPE
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//
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if (MemoryCacheType == (AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE)) {
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if (!CheckMtrrOverlap (MemoryAddress, MemoryAddress+MemoryLength-1)) {
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return EFI_SUCCESS;
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}
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}
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#endif
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//
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// Find first unused MTRR
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//
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MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));
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for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum +=2) {
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if ((AsmReadMsr64(MsrNum+1) & B_EFI_MSR_CACHE_MTRR_VALID) == 0 ) {
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break;
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}
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}
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//
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// Reserve 1 MTRR pair for OS.
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//
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LastVariableMtrrForBios = MsrNumEnd - 1 - (EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS * 2);
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if (MsrNum > LastVariableMtrrForBios) {
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return EFI_LOAD_ERROR;
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}
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//
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// Special case for 1 MB base address
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//
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if (MemoryAddress == BASE_1MB) {
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MemoryAddress = 0;
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}
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//
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// Program MTRRs
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//
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TempQword = MemoryLength;
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if (TempQword == Power2MaxMemory(MemoryAddress, TempQword)) {
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EfiProgramMtrr(MsrNum,
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MemoryAddress,
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MemoryLength,
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MemoryCacheType,
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ValidMtrrAddressMask
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);
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} else {
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//
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// Fill in MTRRs with values. Direction can not be checked for this method
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// as we are using WB as the default cache type and only setting areas to UC.
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//
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do {
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//
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// Do boundary check so we don't go past last MTRR register
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|
// for BIOS use. Leave one MTRR pair for OS use.
|
|
//
|
|
if (MsrNum > LastVariableMtrrForBios) {
|
|
return EFI_LOAD_ERROR;
|
|
}
|
|
|
|
//
|
|
// Set next power of 2 region
|
|
//
|
|
MemoryLength = Power2MaxMemory(MemoryAddress, TempQword);
|
|
EfiProgramMtrr(MsrNum,
|
|
MemoryAddress,
|
|
MemoryLength,
|
|
MemoryCacheType,
|
|
ValidMtrrAddressMask
|
|
);
|
|
MemoryAddress += MemoryLength;
|
|
TempQword -= MemoryLength;
|
|
MsrNum += 2;
|
|
} while (TempQword != 0);
|
|
}
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
Reset all the MTRRs to a known state.
|
|
|
|
@retval EFI_SUCCESS All MTRRs have been reset successfully.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
ResetCacheAttributes (
|
|
VOID
|
|
)
|
|
{
|
|
UINT32 MsrNum, MsrNumEnd;
|
|
UINT16 Index;
|
|
UINT64 OldMtrr;
|
|
UINT64 CacheType;
|
|
BOOLEAN DisableCar;
|
|
Index = 0;
|
|
DisableCar = TRUE;
|
|
|
|
//
|
|
// Determine default cache type
|
|
//
|
|
CacheType = EFI_CACHE_UNCACHEABLE;
|
|
|
|
//
|
|
// Set default cache type
|
|
//
|
|
AsmWriteMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, CacheType);
|
|
|
|
//
|
|
// Disable CAR
|
|
//
|
|
DisableCacheAsRam (DisableCar);
|
|
|
|
EfiDisableCacheMtrr (&OldMtrr);
|
|
|
|
//
|
|
// Reset Fixed MTRRs
|
|
//
|
|
for (Index = 0; Index < V_EFI_FIXED_MTRR_NUMBER; Index++) {
|
|
AsmWriteMsr64 (mFixedMtrrTable[Index].Msr, 0);
|
|
}
|
|
|
|
//
|
|
// Reset Variable MTRRs
|
|
//
|
|
MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));
|
|
for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum++) {
|
|
AsmWriteMsr64 (MsrNum, 0);
|
|
}
|
|
|
|
//
|
|
// Enable Fixed and Variable MTRRs
|
|
//
|
|
EfiRecoverCacheMtrr (TRUE, OldMtrr);
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
Search the memory cache type for specific memory from MTRR.
|
|
|
|
@param[in] MemoryAddress the address of target memory
|
|
@param[in] MemoryLength the length of target memory
|
|
@param[in] ValidMtrrAddressMask the MTRR address mask
|
|
@param[out] UsedMsrNum the used MSR number
|
|
@param[out] UsedMemoryCacheType the cache type for the target memory
|
|
|
|
@retval EFI_SUCCESS The memory is found in MTRR and cache type is returned
|
|
@retval EFI_NOT_FOUND The memory is not found in MTRR
|
|
|
|
**/
|
|
EFI_STATUS
|
|
SearchForExactMtrr (
|
|
IN EFI_PHYSICAL_ADDRESS MemoryAddress,
|
|
IN UINT64 MemoryLength,
|
|
IN UINT64 ValidMtrrAddressMask,
|
|
OUT UINT32 *UsedMsrNum,
|
|
OUT EFI_MEMORY_CACHE_TYPE *UsedMemoryCacheType
|
|
)
|
|
{
|
|
UINT32 MsrNum, MsrNumEnd;
|
|
UINT64 TempQword;
|
|
|
|
if (MemoryLength == 0) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
|
|
MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));
|
|
for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum +=2) {
|
|
TempQword = AsmReadMsr64(MsrNum+1);
|
|
if ((TempQword & B_EFI_MSR_CACHE_MTRR_VALID) == 0) {
|
|
continue;
|
|
}
|
|
|
|
if ((TempQword & ValidMtrrAddressMask) != ((~(MemoryLength - 1)) & ValidMtrrAddressMask)) {
|
|
continue;
|
|
}
|
|
|
|
TempQword = AsmReadMsr64 (MsrNum);
|
|
if ((TempQword & ValidMtrrAddressMask) != (MemoryAddress & ValidMtrrAddressMask)) {
|
|
continue;
|
|
}
|
|
|
|
*UsedMemoryCacheType = (EFI_MEMORY_CACHE_TYPE)(TempQword & B_EFI_MSR_CACHE_MEMORY_TYPE);
|
|
*UsedMsrNum = MsrNum;
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
return EFI_NOT_FOUND;
|
|
}
|
|
|
|
/**
|
|
Check if CacheType match current default setting.
|
|
|
|
@param[in] MemoryCacheType input cache type to be checked.
|
|
|
|
@retval TRUE MemoryCacheType is default MTRR setting.
|
|
@retval TRUE MemoryCacheType is NOT default MTRR setting.
|
|
**/
|
|
BOOLEAN
|
|
IsDefaultType (
|
|
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
|
|
)
|
|
{
|
|
if ((AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE) != MemoryCacheType) {
|
|
return FALSE;
|
|
}
|
|
|
|
return TRUE;
|
|
}
|
|
|