1238 lines
41 KiB
C
1238 lines
41 KiB
C
/** @file
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The CPU specific programming for PiSmmCpuDxeSmm module.
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Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/MemEncryptSevLib.h>
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#include <Library/SmmCpuFeaturesLib.h>
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#include <Library/SmmServicesTableLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <PiSmm.h>
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#include <Register/QemuSmramSaveStateMap.h>
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//
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// EFER register LMA bit
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//
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#define LMA BIT10
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/**
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The constructor function
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@param[in] ImageHandle The firmware allocated handle for the EFI image.
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@param[in] SystemTable A pointer to the EFI System Table.
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@retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
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**/
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EFI_STATUS
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EFIAPI
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SmmCpuFeaturesLibConstructor (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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//
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// No need to program SMRRs on our virtual platform.
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//
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return EFI_SUCCESS;
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}
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/**
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Called during the very first SMI into System Management Mode to initialize
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CPU features, including SMBASE, for the currently executing CPU. Since this
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is the first SMI, the SMRAM Save State Map is at the default address of
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SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
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CPU is specified by CpuIndex and CpuIndex can be used to access information
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about the currently executing CPU in the ProcessorInfo array and the
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HotPlugCpuData data structure.
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@param[in] CpuIndex The index of the CPU to initialize. The value
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must be between 0 and the NumberOfCpus field in
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the System Management System Table (SMST).
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@param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
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was elected as monarch during System Management
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Mode initialization.
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FALSE if the CpuIndex is not the index of the CPU
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that was elected as monarch during System
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Management Mode initialization.
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@param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
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structures. ProcessorInfo[CpuIndex] contains the
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information for the currently executing CPU.
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@param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
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contains the ApidId and SmBase arrays.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesInitializeProcessor (
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IN UINTN CpuIndex,
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IN BOOLEAN IsMonarch,
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IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,
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IN CPU_HOT_PLUG_DATA *CpuHotPlugData
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)
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{
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QEMU_SMRAM_SAVE_STATE_MAP *CpuState;
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//
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// Configure SMBASE.
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//
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CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(
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SMM_DEFAULT_SMBASE +
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SMRAM_SAVE_STATE_MAP_OFFSET
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);
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if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {
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CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
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} else {
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CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
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}
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//
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// No need to program SMRRs on our virtual platform.
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//
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}
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/**
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This function updates the SMRAM save state on the currently executing CPU
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to resume execution at a specific address after an RSM instruction. This
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function must evaluate the SMRAM save state to determine the execution mode
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the RSM instruction resumes and update the resume execution address with
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either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
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flag in the SMRAM save state must always be cleared. This function returns
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the value of the instruction pointer from the SMRAM save state that was
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replaced. If this function returns 0, then the SMRAM save state was not
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modified.
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This function is called during the very first SMI on each CPU after
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SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
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to signal that the SMBASE of each CPU has been updated before the default
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SMBASE address is used for the first SMI to the next CPU.
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@param[in] CpuIndex The index of the CPU to hook. The value
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must be between 0 and the NumberOfCpus
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field in the System Management System
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Table (SMST).
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@param[in] CpuState Pointer to SMRAM Save State Map for the
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currently executing CPU.
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@param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
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32-bit execution mode from 64-bit SMM.
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@param[in] NewInstructionPointer Instruction pointer to use if resuming to
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same execution mode as SMM.
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@retval 0 This function did modify the SMRAM save state.
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@retval > 0 The original instruction pointer value from the SMRAM save state
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before it was replaced.
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**/
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UINT64
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EFIAPI
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SmmCpuFeaturesHookReturnFromSmm (
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IN UINTN CpuIndex,
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IN SMRAM_SAVE_STATE_MAP *CpuState,
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IN UINT64 NewInstructionPointer32,
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IN UINT64 NewInstructionPointer
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)
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{
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UINT64 OriginalInstructionPointer;
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QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
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CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;
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if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
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OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;
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CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;
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//
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// Clear the auto HALT restart flag so the RSM instruction returns
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// program control to the instruction following the HLT instruction.
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//
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if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != 0) {
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CpuSaveState->x86.AutoHALTRestart &= ~BIT0;
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}
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} else {
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OriginalInstructionPointer = CpuSaveState->x64._RIP;
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if ((CpuSaveState->x64.IA32_EFER & LMA) == 0) {
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CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer32;
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} else {
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CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer;
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}
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//
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// Clear the auto HALT restart flag so the RSM instruction returns
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// program control to the instruction following the HLT instruction.
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//
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if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != 0) {
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CpuSaveState->x64.AutoHALTRestart &= ~BIT0;
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}
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}
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return OriginalInstructionPointer;
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}
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/**
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Hook point in normal execution mode that allows the one CPU that was elected
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as monarch during System Management Mode initialization to perform additional
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initialization actions immediately after all of the CPUs have processed their
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first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
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into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesSmmRelocationComplete (
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VOID
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)
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{
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EFI_STATUS Status;
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UINTN MapPagesBase;
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UINTN MapPagesCount;
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if (!MemEncryptSevIsEnabled ()) {
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return;
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}
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//
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// Now that SMBASE relocation is complete, re-encrypt the original SMRAM save
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// state map's container pages, and release the pages to DXE. (The pages were
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// allocated in PlatformPei.)
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//
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Status = MemEncryptSevLocateInitialSmramSaveStateMapPages (
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&MapPagesBase,
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&MapPagesCount
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);
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ASSERT_EFI_ERROR (Status);
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Status = MemEncryptSevSetPageEncMask (
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0, // Cr3BaseAddress -- use current CR3
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MapPagesBase, // BaseAddress
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MapPagesCount, // NumPages
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TRUE // Flush
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "%a: MemEncryptSevSetPageEncMask(): %r\n",
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__FUNCTION__, Status));
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ASSERT (FALSE);
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CpuDeadLoop ();
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}
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ZeroMem ((VOID *)MapPagesBase, EFI_PAGES_TO_SIZE (MapPagesCount));
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Status = gBS->FreePages (MapPagesBase, MapPagesCount);
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ASSERT_EFI_ERROR (Status);
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}
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/**
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Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
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returned, then a custom SMI handler is not provided by this library,
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and the default SMI handler must be used.
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@retval 0 Use the default SMI handler.
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@retval > 0 Use the SMI handler installed by
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SmmCpuFeaturesInstallSmiHandler(). The caller is required to
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allocate enough SMRAM for each CPU to support the size of the
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custom SMI handler.
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**/
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UINTN
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EFIAPI
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SmmCpuFeaturesGetSmiHandlerSize (
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VOID
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)
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{
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return 0;
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}
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/**
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Install a custom SMI handler for the CPU specified by CpuIndex. This
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function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size
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is greater than zero and is called by the CPU that was elected as monarch
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during System Management Mode initialization.
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@param[in] CpuIndex The index of the CPU to install the custom SMI handler.
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The value must be between 0 and the NumberOfCpus field
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in the System Management System Table (SMST).
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@param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
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@param[in] SmiStack The stack to use when an SMI is processed by the
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the CPU specified by CpuIndex.
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@param[in] StackSize The size, in bytes, if the stack used when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] GdtBase The base address of the GDT to use when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] IdtBase The base address of the IDT to use when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] Cr3 The base address of the page tables to use when an SMI
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is processed by the CPU specified by CpuIndex.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesInstallSmiHandler (
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IN UINTN CpuIndex,
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IN UINT32 SmBase,
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IN VOID *SmiStack,
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IN UINTN StackSize,
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IN UINTN GdtBase,
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IN UINTN GdtSize,
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IN UINTN IdtBase,
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IN UINTN IdtSize,
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IN UINT32 Cr3
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)
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{
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}
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/**
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Determines if MTRR registers must be configured to set SMRAM cache-ability
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when executing in System Management Mode.
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@retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
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@retval FALSE MTRR registers do not need to be configured to set SMRAM
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cache-ability.
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**/
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BOOLEAN
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EFIAPI
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SmmCpuFeaturesNeedConfigureMtrrs (
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VOID
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)
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{
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return FALSE;
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}
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/**
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Disable SMRR register if SMRR is supported and
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SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesDisableSmrr (
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VOID
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)
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{
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//
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// No SMRR support, nothing to do
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//
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}
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/**
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Enable SMRR register if SMRR is supported and
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SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesReenableSmrr (
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VOID
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)
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{
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//
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// No SMRR support, nothing to do
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//
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}
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/**
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Processor specific hook point each time a CPU enters System Management Mode.
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@param[in] CpuIndex The index of the CPU that has entered SMM. The value
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must be between 0 and the NumberOfCpus field in the
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System Management System Table (SMST).
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesRendezvousEntry (
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IN UINTN CpuIndex
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)
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{
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//
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// No SMRR support, nothing to do
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//
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}
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/**
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Processor specific hook point each time a CPU exits System Management Mode.
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@param[in] CpuIndex The index of the CPU that is exiting SMM. The value
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must be between 0 and the NumberOfCpus field in the
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System Management System Table (SMST).
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesRendezvousExit (
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IN UINTN CpuIndex
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)
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{
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}
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/**
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Check to see if an SMM register is supported by a specified CPU.
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@param[in] CpuIndex The index of the CPU to check for SMM register support.
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The value must be between 0 and the NumberOfCpus field
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in the System Management System Table (SMST).
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@param[in] RegName Identifies the SMM register to check for support.
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@retval TRUE The SMM register specified by RegName is supported by the CPU
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specified by CpuIndex.
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@retval FALSE The SMM register specified by RegName is not supported by the
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CPU specified by CpuIndex.
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**/
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BOOLEAN
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EFIAPI
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SmmCpuFeaturesIsSmmRegisterSupported (
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IN UINTN CpuIndex,
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IN SMM_REG_NAME RegName
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)
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{
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ASSERT (RegName == SmmRegFeatureControl);
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return FALSE;
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}
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/**
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Returns the current value of the SMM register for the specified CPU.
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If the SMM register is not supported, then 0 is returned.
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@param[in] CpuIndex The index of the CPU to read the SMM register. The
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value must be between 0 and the NumberOfCpus field in
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the System Management System Table (SMST).
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@param[in] RegName Identifies the SMM register to read.
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@return The value of the SMM register specified by RegName from the CPU
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specified by CpuIndex.
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**/
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UINT64
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EFIAPI
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SmmCpuFeaturesGetSmmRegister (
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IN UINTN CpuIndex,
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IN SMM_REG_NAME RegName
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)
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{
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//
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// This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.
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// The last of these should actually be SmmRegSmmDisable, so we can just
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// return FALSE.
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//
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return 0;
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}
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/**
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Sets the value of an SMM register on a specified CPU.
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If the SMM register is not supported, then no action is performed.
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@param[in] CpuIndex The index of the CPU to write the SMM register. The
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value must be between 0 and the NumberOfCpus field in
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the System Management System Table (SMST).
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@param[in] RegName Identifies the SMM register to write.
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registers are read-only.
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@param[in] Value The value to write to the SMM register.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesSetSmmRegister (
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IN UINTN CpuIndex,
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IN SMM_REG_NAME RegName,
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IN UINT64 Value
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)
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{
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ASSERT (FALSE);
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}
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///
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/// Macro used to simplify the lookup table entries of type
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/// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
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///
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#define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)
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///
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/// Macro used to simplify the lookup table entries of type
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/// CPU_SMM_SAVE_STATE_REGISTER_RANGE
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///
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#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
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|
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///
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/// Structure used to describe a range of registers
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///
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typedef struct {
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EFI_SMM_SAVE_STATE_REGISTER Start;
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EFI_SMM_SAVE_STATE_REGISTER End;
|
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UINTN Length;
|
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} CPU_SMM_SAVE_STATE_REGISTER_RANGE;
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|
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///
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/// Structure used to build a lookup table to retrieve the widths and offsets
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/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
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///
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#define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1
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|
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typedef struct {
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UINT8 Width32;
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UINT8 Width64;
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UINT16 Offset32;
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UINT16 Offset64Lo;
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UINT16 Offset64Hi;
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BOOLEAN Writeable;
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} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
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|
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///
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/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
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/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
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///
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STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
|
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SMM_REGISTER_RANGE (
|
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EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,
|
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EFI_SMM_SAVE_STATE_REGISTER_LDTINFO
|
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),
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SMM_REGISTER_RANGE (
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EFI_SMM_SAVE_STATE_REGISTER_ES,
|
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EFI_SMM_SAVE_STATE_REGISTER_RIP
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),
|
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SMM_REGISTER_RANGE (
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EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,
|
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EFI_SMM_SAVE_STATE_REGISTER_CR4
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),
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{ (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }
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};
|
|
|
|
///
|
|
/// Lookup table used to retrieve the widths and offsets associated with each
|
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/// supported EFI_SMM_SAVE_STATE_REGISTER value
|
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///
|
|
STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
|
|
{
|
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0, // Width32
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0, // Width64
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0, // Offset32
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0, // Offset64Lo
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0, // Offset64Hi
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FALSE // Writeable
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}, // Reserved
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|
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//
|
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// CPU Save State registers defined in PI SMM CPU Protocol.
|
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//
|
|
{
|
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0, // Width32
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8, // Width64
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0, // Offset32
|
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SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo
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SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi
|
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FALSE // Writeable
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}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
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|
|
{
|
|
0, // Width32
|
|
8, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._IDTRBase), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._IDTRBase) + 4, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
|
|
|
|
{
|
|
0, // Width32
|
|
8, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._LDTRBase), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._LDTRBase) + 4, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
|
|
|
|
{
|
|
0, // Width32
|
|
0, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._GDTRLimit), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._GDTRLimit) + 4, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
|
|
|
|
{
|
|
0, // Width32
|
|
0, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._IDTRLimit), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._IDTRLimit) + 4, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
|
|
|
|
{
|
|
0, // Width32
|
|
0, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._LDTRLimit), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._LDTRLimit) + 4, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
|
|
|
|
{
|
|
0, // Width32
|
|
0, // Width64
|
|
0, // Offset32
|
|
0, // Offset64Lo
|
|
0 + 4, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
|
|
|
|
{
|
|
4, // Width32
|
|
4, // Width64
|
|
SMM_CPU_OFFSET (x86._ES), // Offset32
|
|
SMM_CPU_OFFSET (x64._ES), // Offset64Lo
|
|
0, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
|
|
|
|
{
|
|
4, // Width32
|
|
4, // Width64
|
|
SMM_CPU_OFFSET (x86._CS), // Offset32
|
|
SMM_CPU_OFFSET (x64._CS), // Offset64Lo
|
|
0, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
|
|
|
|
{
|
|
4, // Width32
|
|
4, // Width64
|
|
SMM_CPU_OFFSET (x86._SS), // Offset32
|
|
SMM_CPU_OFFSET (x64._SS), // Offset64Lo
|
|
0, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
|
|
|
|
{
|
|
4, // Width32
|
|
4, // Width64
|
|
SMM_CPU_OFFSET (x86._DS), // Offset32
|
|
SMM_CPU_OFFSET (x64._DS), // Offset64Lo
|
|
0, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
|
|
|
|
{
|
|
4, // Width32
|
|
4, // Width64
|
|
SMM_CPU_OFFSET (x86._FS), // Offset32
|
|
SMM_CPU_OFFSET (x64._FS), // Offset64Lo
|
|
0, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
|
|
|
|
{
|
|
4, // Width32
|
|
4, // Width64
|
|
SMM_CPU_OFFSET (x86._GS), // Offset32
|
|
SMM_CPU_OFFSET (x64._GS), // Offset64Lo
|
|
0, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
|
|
|
|
{
|
|
0, // Width32
|
|
4, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._LDTR), // Offset64Lo
|
|
0, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
|
|
|
|
{
|
|
4, // Width32
|
|
4, // Width64
|
|
SMM_CPU_OFFSET (x86._TR), // Offset32
|
|
SMM_CPU_OFFSET (x64._TR), // Offset64Lo
|
|
0, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
|
|
|
|
{
|
|
4, // Width32
|
|
8, // Width64
|
|
SMM_CPU_OFFSET (x86._DR7), // Offset32
|
|
SMM_CPU_OFFSET (x64._DR7), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._DR7) + 4, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
|
|
|
|
{
|
|
4, // Width32
|
|
8, // Width64
|
|
SMM_CPU_OFFSET (x86._DR6), // Offset32
|
|
SMM_CPU_OFFSET (x64._DR6), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._DR6) + 4, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
|
|
|
|
{
|
|
0, // Width32
|
|
8, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._R8), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._R8) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
|
|
|
|
{
|
|
0, // Width32
|
|
8, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._R9), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._R9) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
|
|
|
|
{
|
|
0, // Width32
|
|
8, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._R10), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._R10) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
|
|
|
|
{
|
|
0, // Width32
|
|
8, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._R11), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._R11) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
|
|
|
|
{
|
|
0, // Width32
|
|
8, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._R12), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._R12) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
|
|
|
|
{
|
|
0, // Width32
|
|
8, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._R13), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._R13) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
|
|
|
|
{
|
|
0, // Width32
|
|
8, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._R14), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._R14) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
|
|
|
|
{
|
|
0, // Width32
|
|
8, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._R15), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._R15) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
|
|
|
|
{
|
|
4, // Width32
|
|
8, // Width64
|
|
SMM_CPU_OFFSET (x86._EAX), // Offset32
|
|
SMM_CPU_OFFSET (x64._RAX), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._RAX) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
|
|
|
|
{
|
|
4, // Width32
|
|
8, // Width64
|
|
SMM_CPU_OFFSET (x86._EBX), // Offset32
|
|
SMM_CPU_OFFSET (x64._RBX), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._RBX) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
|
|
|
|
{
|
|
4, // Width32
|
|
8, // Width64
|
|
SMM_CPU_OFFSET (x86._ECX), // Offset32
|
|
SMM_CPU_OFFSET (x64._RCX), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._RCX) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
|
|
|
|
{
|
|
4, // Width32
|
|
8, // Width64
|
|
SMM_CPU_OFFSET (x86._EDX), // Offset32
|
|
SMM_CPU_OFFSET (x64._RDX), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._RDX) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
|
|
|
|
{
|
|
4, // Width32
|
|
8, // Width64
|
|
SMM_CPU_OFFSET (x86._ESP), // Offset32
|
|
SMM_CPU_OFFSET (x64._RSP), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._RSP) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
|
|
|
|
{
|
|
4, // Width32
|
|
8, // Width64
|
|
SMM_CPU_OFFSET (x86._EBP), // Offset32
|
|
SMM_CPU_OFFSET (x64._RBP), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._RBP) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
|
|
|
|
{
|
|
4, // Width32
|
|
8, // Width64
|
|
SMM_CPU_OFFSET (x86._ESI), // Offset32
|
|
SMM_CPU_OFFSET (x64._RSI), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._RSI) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
|
|
|
|
{
|
|
4, // Width32
|
|
8, // Width64
|
|
SMM_CPU_OFFSET (x86._EDI), // Offset32
|
|
SMM_CPU_OFFSET (x64._RDI), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._RDI) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
|
|
|
|
{
|
|
4, // Width32
|
|
8, // Width64
|
|
SMM_CPU_OFFSET (x86._EIP), // Offset32
|
|
SMM_CPU_OFFSET (x64._RIP), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._RIP) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
|
|
|
|
{
|
|
4, // Width32
|
|
8, // Width64
|
|
SMM_CPU_OFFSET (x86._EFLAGS), // Offset32
|
|
SMM_CPU_OFFSET (x64._RFLAGS), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._RFLAGS) + 4, // Offset64Hi
|
|
TRUE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
|
|
|
|
{
|
|
4, // Width32
|
|
8, // Width64
|
|
SMM_CPU_OFFSET (x86._CR0), // Offset32
|
|
SMM_CPU_OFFSET (x64._CR0), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._CR0) + 4, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
|
|
|
|
{
|
|
4, // Width32
|
|
8, // Width64
|
|
SMM_CPU_OFFSET (x86._CR3), // Offset32
|
|
SMM_CPU_OFFSET (x64._CR3), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._CR3) + 4, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
|
|
|
|
{
|
|
0, // Width32
|
|
4, // Width64
|
|
0, // Offset32
|
|
SMM_CPU_OFFSET (x64._CR4), // Offset64Lo
|
|
SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi
|
|
FALSE // Writeable
|
|
}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
|
|
};
|
|
|
|
//
|
|
// No support for I/O restart
|
|
//
|
|
|
|
/**
|
|
Read information from the CPU save state.
|
|
|
|
@param Register Specifies the CPU register to read form the save state.
|
|
|
|
@retval 0 Register is not valid
|
|
@retval >0 Index into mSmmCpuWidthOffset[] associated with Register
|
|
|
|
**/
|
|
STATIC
|
|
UINTN
|
|
GetRegisterIndex (
|
|
IN EFI_SMM_SAVE_STATE_REGISTER Register
|
|
)
|
|
{
|
|
UINTN Index;
|
|
UINTN Offset;
|
|
|
|
for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX;
|
|
mSmmCpuRegisterRanges[Index].Length != 0;
|
|
Index++) {
|
|
if (Register >= mSmmCpuRegisterRanges[Index].Start &&
|
|
Register <= mSmmCpuRegisterRanges[Index].End) {
|
|
return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
|
|
}
|
|
Offset += mSmmCpuRegisterRanges[Index].Length;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
Read a CPU Save State register on the target processor.
|
|
|
|
This function abstracts the differences that whether the CPU Save State
|
|
register is in the IA32 CPU Save State Map or X64 CPU Save State Map.
|
|
|
|
This function supports reading a CPU Save State register in SMBase relocation
|
|
handler.
|
|
|
|
@param[in] CpuIndex Specifies the zero-based index of the CPU save
|
|
state.
|
|
@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
|
|
@param[in] Width The number of bytes to read from the CPU save
|
|
state.
|
|
@param[out] Buffer Upon return, this holds the CPU register value
|
|
read from the save state.
|
|
|
|
@retval EFI_SUCCESS The register was read from Save State.
|
|
@retval EFI_NOT_FOUND The register is not defined for the Save State
|
|
of Processor.
|
|
@retval EFI_INVALID_PARAMTER This or Buffer is NULL.
|
|
|
|
**/
|
|
STATIC
|
|
EFI_STATUS
|
|
ReadSaveStateRegisterByIndex (
|
|
IN UINTN CpuIndex,
|
|
IN UINTN RegisterIndex,
|
|
IN UINTN Width,
|
|
OUT VOID *Buffer
|
|
)
|
|
{
|
|
QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
|
|
|
|
CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
|
|
|
|
if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
|
|
//
|
|
// If 32-bit mode width is zero, then the specified register can not be
|
|
// accessed
|
|
//
|
|
if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
|
|
return EFI_NOT_FOUND;
|
|
}
|
|
|
|
//
|
|
// If Width is bigger than the 32-bit mode width, then the specified
|
|
// register can not be accessed
|
|
//
|
|
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
|
|
//
|
|
// Write return buffer
|
|
//
|
|
ASSERT(CpuSaveState != NULL);
|
|
CopyMem (
|
|
Buffer,
|
|
(UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,
|
|
Width
|
|
);
|
|
} else {
|
|
//
|
|
// If 64-bit mode width is zero, then the specified register can not be
|
|
// accessed
|
|
//
|
|
if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
|
|
return EFI_NOT_FOUND;
|
|
}
|
|
|
|
//
|
|
// If Width is bigger than the 64-bit mode width, then the specified
|
|
// register can not be accessed
|
|
//
|
|
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
|
|
//
|
|
// Write lower 32-bits of return buffer
|
|
//
|
|
CopyMem (
|
|
Buffer,
|
|
(UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,
|
|
MIN (4, Width)
|
|
);
|
|
if (Width >= 4) {
|
|
//
|
|
// Write upper 32-bits of return buffer
|
|
//
|
|
CopyMem (
|
|
(UINT8 *)Buffer + 4,
|
|
(UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,
|
|
Width - 4
|
|
);
|
|
}
|
|
}
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
Read an SMM Save State register on the target processor. If this function
|
|
returns EFI_UNSUPPORTED, then the caller is responsible for reading the
|
|
SMM Save Sate register.
|
|
|
|
@param[in] CpuIndex The index of the CPU to read the SMM Save State. The
|
|
value must be between 0 and the NumberOfCpus field in
|
|
the System Management System Table (SMST).
|
|
@param[in] Register The SMM Save State register to read.
|
|
@param[in] Width The number of bytes to read from the CPU save state.
|
|
@param[out] Buffer Upon return, this holds the CPU register value read
|
|
from the save state.
|
|
|
|
@retval EFI_SUCCESS The register was read from Save State.
|
|
@retval EFI_INVALID_PARAMTER Buffer is NULL.
|
|
@retval EFI_UNSUPPORTED This function does not support reading
|
|
Register.
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
SmmCpuFeaturesReadSaveStateRegister (
|
|
IN UINTN CpuIndex,
|
|
IN EFI_SMM_SAVE_STATE_REGISTER Register,
|
|
IN UINTN Width,
|
|
OUT VOID *Buffer
|
|
)
|
|
{
|
|
UINTN RegisterIndex;
|
|
QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
|
|
|
|
//
|
|
// Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
|
|
//
|
|
if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
|
|
//
|
|
// Only byte access is supported for this register
|
|
//
|
|
if (Width != 1) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
|
|
CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
|
|
|
|
//
|
|
// Check CPU mode
|
|
//
|
|
if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
|
|
*(UINT8 *)Buffer = 32;
|
|
} else {
|
|
*(UINT8 *)Buffer = 64;
|
|
}
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
//
|
|
// Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
|
|
//
|
|
if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
|
|
return EFI_NOT_FOUND;
|
|
}
|
|
|
|
//
|
|
// Convert Register to a register lookup table index. Let
|
|
// PiSmmCpuDxeSmm implement other special registers (currently
|
|
// there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
|
|
//
|
|
RegisterIndex = GetRegisterIndex (Register);
|
|
if (RegisterIndex == 0) {
|
|
return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?
|
|
EFI_NOT_FOUND :
|
|
EFI_UNSUPPORTED);
|
|
}
|
|
|
|
return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);
|
|
}
|
|
|
|
/**
|
|
Writes an SMM Save State register on the target processor. If this function
|
|
returns EFI_UNSUPPORTED, then the caller is responsible for writing the
|
|
SMM Save Sate register.
|
|
|
|
@param[in] CpuIndex The index of the CPU to write the SMM Save State. The
|
|
value must be between 0 and the NumberOfCpus field in
|
|
the System Management System Table (SMST).
|
|
@param[in] Register The SMM Save State register to write.
|
|
@param[in] Width The number of bytes to write to the CPU save state.
|
|
@param[in] Buffer Upon entry, this holds the new CPU register value.
|
|
|
|
@retval EFI_SUCCESS The register was written to Save State.
|
|
@retval EFI_INVALID_PARAMTER Buffer is NULL.
|
|
@retval EFI_UNSUPPORTED This function does not support writing
|
|
Register.
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
SmmCpuFeaturesWriteSaveStateRegister (
|
|
IN UINTN CpuIndex,
|
|
IN EFI_SMM_SAVE_STATE_REGISTER Register,
|
|
IN UINTN Width,
|
|
IN CONST VOID *Buffer
|
|
)
|
|
{
|
|
UINTN RegisterIndex;
|
|
QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
|
|
|
|
//
|
|
// Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
|
|
//
|
|
if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
//
|
|
// Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
|
|
//
|
|
if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
|
|
return EFI_NOT_FOUND;
|
|
}
|
|
|
|
//
|
|
// Convert Register to a register lookup table index. Let
|
|
// PiSmmCpuDxeSmm implement other special registers (currently
|
|
// there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
|
|
//
|
|
RegisterIndex = GetRegisterIndex (Register);
|
|
if (RegisterIndex == 0) {
|
|
return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?
|
|
EFI_NOT_FOUND :
|
|
EFI_UNSUPPORTED);
|
|
}
|
|
|
|
CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
|
|
|
|
//
|
|
// Do not write non-writable SaveState, because it will cause exception.
|
|
//
|
|
if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
|
|
return EFI_UNSUPPORTED;
|
|
}
|
|
|
|
//
|
|
// Check CPU mode
|
|
//
|
|
if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
|
|
//
|
|
// If 32-bit mode width is zero, then the specified register can not be
|
|
// accessed
|
|
//
|
|
if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
|
|
return EFI_NOT_FOUND;
|
|
}
|
|
|
|
//
|
|
// If Width is bigger than the 32-bit mode width, then the specified
|
|
// register can not be accessed
|
|
//
|
|
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
//
|
|
// Write SMM State register
|
|
//
|
|
ASSERT (CpuSaveState != NULL);
|
|
CopyMem (
|
|
(UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,
|
|
Buffer,
|
|
Width
|
|
);
|
|
} else {
|
|
//
|
|
// If 64-bit mode width is zero, then the specified register can not be
|
|
// accessed
|
|
//
|
|
if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
|
|
return EFI_NOT_FOUND;
|
|
}
|
|
|
|
//
|
|
// If Width is bigger than the 64-bit mode width, then the specified
|
|
// register can not be accessed
|
|
//
|
|
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
|
|
//
|
|
// Write lower 32-bits of SMM State register
|
|
//
|
|
CopyMem (
|
|
(UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,
|
|
Buffer,
|
|
MIN (4, Width)
|
|
);
|
|
if (Width >= 4) {
|
|
//
|
|
// Write upper 32-bits of SMM State register
|
|
//
|
|
CopyMem (
|
|
(UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,
|
|
(UINT8 *)Buffer + 4,
|
|
Width - 4
|
|
);
|
|
}
|
|
}
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
|
|
notification is completely processed.
|
|
**/
|
|
VOID
|
|
EFIAPI
|
|
SmmCpuFeaturesCompleteSmmReadyToLock (
|
|
VOID
|
|
)
|
|
{
|
|
}
|
|
|
|
/**
|
|
This API provides a method for a CPU to allocate a specific region for
|
|
storing page tables.
|
|
|
|
This API can be called more once to allocate memory for page tables.
|
|
|
|
Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns
|
|
a pointer to the allocated buffer. The buffer returned is aligned on a 4KB
|
|
boundary. If Pages is 0, then NULL is returned. If there is not enough
|
|
memory remaining to satisfy the request, then NULL is returned.
|
|
|
|
This function can also return NULL if there is no preference on where the
|
|
page tables are allocated in SMRAM.
|
|
|
|
@param Pages The number of 4 KB pages to allocate.
|
|
|
|
@return A pointer to the allocated buffer for page tables.
|
|
@retval NULL Fail to allocate a specific region for storing page tables,
|
|
Or there is no preference on where the page tables are
|
|
allocated in SMRAM.
|
|
|
|
**/
|
|
VOID *
|
|
EFIAPI
|
|
SmmCpuFeaturesAllocatePageTableMemory (
|
|
IN UINTN Pages
|
|
)
|
|
{
|
|
return NULL;
|
|
}
|
|
|