737 lines
20 KiB
C
737 lines
20 KiB
C
/** @file
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Debug Port Library implementation based on usb3 debug port.
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Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__
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#define __USB3_DEBUG_PORT_LIB_INTERNAL__
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#include <Uefi.h>
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#include <Base.h>
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#include <IndustryStandard/Usb.h>
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#include <Library/IoLib.h>
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#include <IndustryStandard/Pci.h>
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#include <Library/PcdLib.h>
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#include <Library/UefiLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/BaseLib.h>
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#include <Library/TimerLib.h>
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#include <Library/DebugCommunicationLib.h>
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#include <Library/PciLib.h>
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//
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// USB Debug GUID value
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//
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#define USB3_DBG_GUID \
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{ \
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0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \
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}
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//
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// The state machine of usb debug port
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//
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#define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability
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#define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability
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#define USB3DBG_ENABLED 2 // The XHCI debug device is enabled
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#define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled
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#define USB3DBG_UNINITIALIZED 255 // The XHCI debug device is uninitialized
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#define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08
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//
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// MaxPacketSize for DbC Endpoint Descriptor IN and OUT
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//
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#define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400
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#define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525
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#define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A
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#define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF
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#define XHCI_DEBUG_DEVICE_REVISION 0x00
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#define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL
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#define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000
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#define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A
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#define XHC_HCCPARAMS_OFFSET 0x10
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#define XHC_CAPABILITY_ID_MASK 0xFF
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#define XHC_NEXT_CAPABILITY_MASK 0xFF00
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#define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1
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#define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset
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#define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset
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#define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset
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#define XHC_USBCMD_RUN BIT0 // Run/Stop
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#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
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#define XHC_USBSTS_HALT BIT0
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//
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// Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.
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//
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#define DATA_TRANSFER_WRITE_TIMEOUT 0
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#define DATA_TRANSFER_READ_TIMEOUT 50000
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#define DATA_TRANSFER_POLL_TIMEOUT 1000
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#define XHC_DEBUG_PORT_1_MILLISECOND 1000
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//
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// XHCI port power off/on delay
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//
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#define XHC_DEBUG_PORT_ON_OFF_DELAY 100000
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//
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// USB debug device string descritpor (header size + unicode string length)
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//
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#define STRING0_DESC_LEN 4
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#define MANU_DESC_LEN 12
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#define PRODUCT_DESC_LEN 40
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#define SERIAL_DESC_LEN 4
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//
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// Debug Capability Register Offset
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//
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#define XHC_DC_DCID 0x0
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#define XHC_DC_DCDB 0x4
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#define XHC_DC_DCERSTSZ 0x8
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#define XHC_DC_DCERSTBA 0x10
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#define XHC_DC_DCERDP 0x18
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#define XHC_DC_DCCTRL 0x20
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#define XHC_DC_DCST 0x24
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#define XHC_DC_DCPORTSC 0x28
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#define XHC_DC_DCCP 0x30
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#define XHC_DC_DCDDI1 0x38
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#define XHC_DC_DCDDI2 0x3C
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#define TRB_TYPE_LINK 6
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#define ERST_NUMBER 0x01
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#define TR_RING_TRB_NUMBER 0x100
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#define EVENT_RING_TRB_NUMBER 0x200
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#define ED_BULK_OUT 2
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#define ED_BULK_IN 6
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#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
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#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
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#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
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//
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// Endpoint Type (EP Type).
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//
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#define ED_NOT_VALID 0
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#define ED_ISOCH_OUT 1
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#define ED_BULK_OUT 2
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#define ED_INTERRUPT_OUT 3
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#define ED_CONTROL_BIDIR 4
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#define ED_ISOCH_IN 5
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#define ED_BULK_IN 6
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#define ED_INTERRUPT_IN 7
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//
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// 6.4.5 TRB Completion Codes
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//
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#define TRB_COMPLETION_INVALID 0
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#define TRB_COMPLETION_SUCCESS 1
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#define TRB_COMPLETION_DATA_BUFFER_ERROR 2
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#define TRB_COMPLETION_BABBLE_ERROR 3
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#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
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#define TRB_COMPLETION_TRB_ERROR 5
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#define TRB_COMPLETION_STALL_ERROR 6
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#define TRB_COMPLETION_SHORT_PACKET 13
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//
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// 6.4.6 TRB Types
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//
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#define TRB_TYPE_NORMAL 1
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#define TRB_TYPE_SETUP_STAGE 2
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#define TRB_TYPE_DATA_STAGE 3
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#define TRB_TYPE_STATUS_STAGE 4
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#define TRB_TYPE_ISOCH 5
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#define TRB_TYPE_LINK 6
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#define TRB_TYPE_EVENT_DATA 7
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#define TRB_TYPE_NO_OP 8
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#define TRB_TYPE_EN_SLOT 9
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#define TRB_TYPE_DIS_SLOT 10
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#define TRB_TYPE_ADDRESS_DEV 11
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#define TRB_TYPE_CON_ENDPOINT 12
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#define TRB_TYPE_EVALU_CONTXT 13
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#define TRB_TYPE_RESET_ENDPOINT 14
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#define TRB_TYPE_STOP_ENDPOINT 15
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#define TRB_TYPE_SET_TR_DEQUE 16
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#define TRB_TYPE_RESET_DEV 17
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#define TRB_TYPE_GET_PORT_BANW 21
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#define TRB_TYPE_FORCE_HEADER 22
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#define TRB_TYPE_NO_OP_COMMAND 23
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#define TRB_TYPE_TRANS_EVENT 32
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#define TRB_TYPE_COMMAND_COMPLT_EVENT 33
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#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
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#define TRB_TYPE_HOST_CONTROLLER_EVENT 37
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#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
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#define TRB_TYPE_MFINDEX_WRAP_EVENT 39
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//
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// Convert millisecond to microsecond.
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//
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#define XHC_1_MILLISECOND (1000)
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#define XHC_POLL_DELAY (1000)
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#define XHC_GENERIC_TIMEOUT (10 * 1000)
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#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.
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#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.
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#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.
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#define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.
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//
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// Transfer types, used in URB to identify the transfer type
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//
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#define XHC_CTRL_TRANSFER 0x01
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#define XHC_BULK_TRANSFER 0x02
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#define XHC_INT_TRANSFER_SYNC 0x04
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#define XHC_INT_TRANSFER_ASYNC 0x08
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#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
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//
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// USB Transfer Results
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//
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#define EFI_USB_NOERROR 0x00
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#define EFI_USB_ERR_NOTEXECUTE 0x01
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#define EFI_USB_ERR_STALL 0x02
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#define EFI_USB_ERR_BUFFER 0x04
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#define EFI_USB_ERR_BABBLE 0x08
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#define EFI_USB_ERR_NAK 0x10
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#define EFI_USB_ERR_CRC 0x20
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#define EFI_USB_ERR_TIMEOUT 0x40
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#define EFI_USB_ERR_BITSTUFF 0x80
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#define EFI_USB_ERR_SYSTEM 0x100
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#pragma pack(1)
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//
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// 7.6.9 OUT/IN EP Context: 64 bytes
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// 7.6.9.2 When used by the DbC it is always a 64 byte data structure
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//
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typedef struct _ENDPOINT_CONTEXT_64 {
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UINT32 EPState:3;
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UINT32 RsvdZ1:5;
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UINT32 Mult:2; // set to 0
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UINT32 MaxPStreams:5; // set to 0
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UINT32 LSA:1; // set to 0
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UINT32 Interval:8; // set to 0
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UINT32 RsvdZ2:8;
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UINT32 RsvdZ3:1;
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UINT32 CErr:2;
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UINT32 EPType:3;
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UINT32 RsvdZ4:1;
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UINT32 HID:1; // set to 0
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UINT32 MaxBurstSize:8;
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UINT32 MaxPacketSize:16;
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UINT32 PtrLo;
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UINT32 PtrHi;
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UINT32 AverageTRBLength:16;
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UINT32 MaxESITPayload:16; // set to 0
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UINT32 RsvdZ5; // Reserved
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UINT32 RsvdZ6;
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UINT32 RsvdZ7;
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UINT32 RsvdZ8;
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UINT32 RsvdZ9;
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UINT32 RsvdZ10;
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UINT32 RsvdZ11;
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UINT32 RsvdZ12;
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UINT32 RsvdZ13;
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UINT32 RsvdZ14;
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UINT32 RsvdZ15;
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} ENDPOINT_CONTEXT_64;
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//
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// 6.4.1.1 Normal TRB: 16 bytes
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// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
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// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
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// Rings, and to define the Data stage information for Control Transfer Rings.
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//
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typedef struct _TRANSFER_TRB_NORMAL {
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UINT32 TRBPtrLo;
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UINT32 TRBPtrHi;
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UINT32 Length:17;
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UINT32 TDSize:5;
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UINT32 IntTarget:10;
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UINT32 CycleBit:1;
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UINT32 ENT:1;
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UINT32 ISP:1;
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UINT32 NS:1;
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UINT32 CH:1;
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UINT32 IOC:1;
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UINT32 IDT:1;
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UINT32 RsvdZ1:2;
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UINT32 BEI:1;
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UINT32 Type:6;
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UINT32 RsvdZ2:16;
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} TRANSFER_TRB_NORMAL;
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//
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// 6.4.2.1 Transfer Event TRB: 16 bytes
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// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
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// for more information on the use and operation of Transfer Events.
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//
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typedef struct _EVT_TRB_TRANSFER {
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UINT32 TRBPtrLo;
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UINT32 TRBPtrHi;
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UINT32 Length:24;
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UINT32 Completecode:8;
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UINT32 CycleBit:1;
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UINT32 RsvdZ1:1;
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UINT32 ED:1;
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UINT32 RsvdZ2:7;
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UINT32 Type:6;
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UINT32 EndpointId:5;
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UINT32 RsvdZ3:3;
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UINT32 SlotId:8;
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} EVT_TRB_TRANSFER;
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//
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// 6.4.4.1 Link TRB: 16 bytes
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// A Link TRB provides support for non-contiguous TRB Rings.
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//
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typedef struct _LINK_TRB {
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UINT32 PtrLo;
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UINT32 PtrHi;
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UINT32 RsvdZ1:22;
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UINT32 InterTarget:10;
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UINT32 CycleBit:1;
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UINT32 TC:1;
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UINT32 RsvdZ2:2;
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UINT32 CH:1;
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UINT32 IOC:1;
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UINT32 RsvdZ3:4;
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UINT32 Type:6;
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UINT32 RsvdZ4:16;
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} LINK_TRB;
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//
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// TRB Template: 16 bytes
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//
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typedef struct _TRB_TEMPLATE {
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UINT32 Parameter1;
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UINT32 Parameter2;
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UINT32 Status;
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UINT32 CycleBit:1;
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UINT32 RsvdZ1:9;
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UINT32 Type:6;
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UINT32 Control:16;
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} TRB_TEMPLATE;
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//
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// Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes
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//
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typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
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UINT32 PtrLo;
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UINT32 PtrHi;
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UINT32 RingTrbSize:16;
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UINT32 RsvdZ1:16;
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UINT32 RsvdZ2;
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} EVENT_RING_SEG_TABLE_ENTRY;
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//
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// Size: 40 bytes
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//
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typedef struct _EVENT_RING {
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EFI_PHYSICAL_ADDRESS ERSTBase;
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EFI_PHYSICAL_ADDRESS EventRingSeg0;
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UINT32 TrbNumber;
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EFI_PHYSICAL_ADDRESS EventRingEnqueue;
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EFI_PHYSICAL_ADDRESS EventRingDequeue;
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UINT32 EventRingCCS;
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} EVENT_RING;
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// Size: 32 bytes
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typedef struct _TRANSFER_RING {
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EFI_PHYSICAL_ADDRESS RingSeg0;
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UINT32 TrbNumber;
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EFI_PHYSICAL_ADDRESS RingEnqueue;
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EFI_PHYSICAL_ADDRESS RingDequeue;
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UINT32 RingPCS;
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} TRANSFER_RING;
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//
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// Size: 64 bytes
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//
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typedef struct _DBC_INFO_CONTEXT {
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UINT64 String0DescAddress;
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UINT64 ManufacturerStrDescAddress;
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UINT64 ProductStrDescAddress;
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UINT64 SerialNumberStrDescAddress;
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UINT64 String0Length:8;
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UINT64 ManufacturerStrLength:8;
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UINT64 ProductStrLength:8;
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UINT64 SerialNumberStrLength:8;
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UINT64 RsvdZ1:32;
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UINT64 RsvdZ2;
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UINT64 RsvdZ3;
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UINT64 RsvdZ4;
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} DBC_INFO_CONTEXT;
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//
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// Debug Capability Context Data Structure: 192 bytes
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//
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typedef struct _XHC_DC_CONTEXT {
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DBC_INFO_CONTEXT DbcInfoContext;
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ENDPOINT_CONTEXT_64 EpOutContext;
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ENDPOINT_CONTEXT_64 EpInContext;
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} XHC_DC_CONTEXT;
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//
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// Size: 16 bytes
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//
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typedef union _TRB {
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TRB_TEMPLATE TrbTemplate;
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TRANSFER_TRB_NORMAL TrbNormal;
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} TRB;
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///
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/// USB data transfer direction
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///
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typedef enum {
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EfiUsbDataIn,
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EfiUsbDataOut,
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EfiUsbNoData
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} EFI_USB_DATA_DIRECTION;
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//
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// URB (Usb Request Block) contains information for all kinds of
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// usb requests.
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//
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typedef struct _URB {
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//
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// Transfer data buffer
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//
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EFI_PHYSICAL_ADDRESS Data;
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UINT32 DataLen;
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//
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// Execute result
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//
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UINT32 Result;
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//
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// Completed data length
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//
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UINT32 Completed;
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//
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// Tranfer Ring info
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//
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EFI_PHYSICAL_ADDRESS Ring;
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EFI_PHYSICAL_ADDRESS Trb;
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BOOLEAN Finished;
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EFI_USB_DATA_DIRECTION Direction;
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} URB;
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typedef struct _USB3_DEBUG_PORT_INSTANCE {
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UINT8 Initialized;
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//
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// The flag indicates debug capability is supported
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//
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BOOLEAN DebugSupport;
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//
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// The flag indicates debug device is ready
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//
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BOOLEAN Ready;
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//
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// The flag indicates the instance is from HOB
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//
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BOOLEAN FromHob;
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//
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// Prevent notification being interrupted by debug timer
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//
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BOOLEAN InNotify;
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//
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// PciIo protocol event
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//
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EFI_PHYSICAL_ADDRESS PciIoEvent;
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//
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// The flag indicates if USB 3.0 ports has been turn off/on power
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//
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BOOLEAN ChangePortPower;
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//
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// XHCI MMIO Base address
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//
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EFI_PHYSICAL_ADDRESS XhciMmioBase;
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//
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// XHCI OP RegisterBase address
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//
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EFI_PHYSICAL_ADDRESS XhciOpRegister;
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//
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// XHCI Debug Register Base Address
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//
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EFI_PHYSICAL_ADDRESS DebugCapabilityBase;
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//
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// XHCI Debug Capability offset
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//
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UINT64 DebugCapabilityOffset;
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//
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// XHCI Debug Context Address
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//
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EFI_PHYSICAL_ADDRESS DebugCapabilityContext;
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//
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// Transfer Ring
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//
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TRANSFER_RING TransferRingOut;
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TRANSFER_RING TransferRingIn;
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//
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// EventRing
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//
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EVENT_RING EventRing;
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//
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// URB - Read
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//
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URB UrbOut;
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//
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// URB - Write
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//
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URB UrbIn;
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|
|
//
|
|
// The available data length in the following data buffer.
|
|
//
|
|
UINT8 DataCount;
|
|
//
|
|
// The data buffer address for data read and poll.
|
|
//
|
|
EFI_PHYSICAL_ADDRESS Data;
|
|
} USB3_DEBUG_PORT_HANDLE;
|
|
|
|
#pragma pack()
|
|
|
|
/**
|
|
Read XHCI debug register.
|
|
|
|
@param Handle Debug port handle.
|
|
@param Offset The offset of the debug register.
|
|
|
|
@return The register content read
|
|
|
|
**/
|
|
UINT32
|
|
XhcReadDebugReg (
|
|
IN USB3_DEBUG_PORT_HANDLE *Handle,
|
|
IN UINT32 Offset
|
|
);
|
|
|
|
/**
|
|
Set one bit of the debug register while keeping other bits.
|
|
|
|
@param Handle Debug port handle.
|
|
@param Offset The offset of the debug register.
|
|
@param Bit The bit mask of the register to set.
|
|
|
|
**/
|
|
VOID
|
|
XhcSetDebugRegBit (
|
|
IN USB3_DEBUG_PORT_HANDLE *Handle,
|
|
IN UINT32 Offset,
|
|
IN UINT32 Bit
|
|
);
|
|
|
|
/**
|
|
Write the data to the debug register.
|
|
|
|
@param Handle Debug port handle.
|
|
@param Offset The offset of the debug register.
|
|
@param Data The data to write.
|
|
|
|
**/
|
|
VOID
|
|
XhcWriteDebugReg (
|
|
IN USB3_DEBUG_PORT_HANDLE *Handle,
|
|
IN UINT32 Offset,
|
|
IN UINT32 Data
|
|
);
|
|
|
|
/**
|
|
Verifies if the bit positions specified by a mask are set in a register.
|
|
|
|
@param[in, out] Register UNITN register
|
|
@param[in] BitMask 32-bit mask
|
|
|
|
@return BOOLEAN - TRUE if all bits specified by the mask are enabled.
|
|
- FALSE even if one of the bits specified by the mask
|
|
is not enabled.
|
|
**/
|
|
BOOLEAN
|
|
XhcIsBitSet(
|
|
UINTN Register,
|
|
UINT32 BitMask
|
|
);
|
|
|
|
/**
|
|
Sets bits as per the enabled bit positions in the mask.
|
|
|
|
@param[in, out] Register UINTN register
|
|
@param[in] BitMask 32-bit mask
|
|
**/
|
|
VOID
|
|
XhcSetR32Bit(
|
|
UINTN Register,
|
|
UINT32 BitMask
|
|
);
|
|
|
|
/**
|
|
Clears bits as per the enabled bit positions in the mask.
|
|
|
|
@param[in, out] Register UINTN register
|
|
@param[in] BitMask 32-bit mask
|
|
**/
|
|
VOID
|
|
XhcClearR32Bit(
|
|
IN OUT UINTN Register,
|
|
IN UINT32 BitMask
|
|
);
|
|
|
|
/**
|
|
Initialize USB3 debug port.
|
|
|
|
This method invokes various internal functions to facilitate
|
|
detection and initialization of USB3 debug port.
|
|
|
|
@retval RETURN_SUCCESS The serial device was initialized.
|
|
**/
|
|
RETURN_STATUS
|
|
EFIAPI
|
|
USB3Initialize (
|
|
VOID
|
|
);
|
|
|
|
/**
|
|
Return command register value in XHCI controller.
|
|
|
|
**/
|
|
UINT16
|
|
GetXhciPciCommand (
|
|
VOID
|
|
);
|
|
|
|
/**
|
|
Allocate aligned memory for XHC's usage.
|
|
|
|
@param BufferSize The size, in bytes, of the Buffer.
|
|
|
|
@return A pointer to the allocated buffer or NULL if allocation fails.
|
|
|
|
**/
|
|
VOID*
|
|
AllocateAlignBuffer (
|
|
IN UINTN BufferSize
|
|
);
|
|
|
|
/**
|
|
The real function to initialize USB3 debug port.
|
|
|
|
This method invokes various internal functions to facilitate
|
|
detection and initialization of USB3 debug port.
|
|
|
|
@retval RETURN_SUCCESS The serial device was initialized.
|
|
**/
|
|
RETURN_STATUS
|
|
EFIAPI
|
|
USB3InitializeReal (
|
|
VOID
|
|
);
|
|
|
|
/**
|
|
Submits bulk transfer to a bulk endpoint of a USB device.
|
|
|
|
@param Handle The instance of debug device.
|
|
@param Direction The direction of data transfer.
|
|
@param Data Array of pointers to the buffers of data to transmit
|
|
from or receive into.
|
|
@param DataLength The lenght of the data buffer.
|
|
@param Timeout Indicates the maximum time, in millisecond, which
|
|
the transfer is allowed to complete.
|
|
|
|
@retval EFI_SUCCESS The transfer was completed successfully.
|
|
@retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.
|
|
@retval EFI_INVALID_PARAMETER Some parameters are invalid.
|
|
@retval EFI_TIMEOUT The transfer failed due to timeout.
|
|
@retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
XhcDataTransfer (
|
|
IN USB3_DEBUG_PORT_HANDLE *Handle,
|
|
IN EFI_USB_DATA_DIRECTION Direction,
|
|
IN OUT VOID *Data,
|
|
IN OUT UINTN *DataLength,
|
|
IN UINTN Timeout
|
|
);
|
|
|
|
/**
|
|
Initialize usb debug port hardware.
|
|
|
|
@param Handle Debug port handle.
|
|
|
|
@retval TRUE The usb debug port hardware configuration is changed.
|
|
@retval FALSE The usb debug port hardware configuration is not changed.
|
|
|
|
**/
|
|
RETURN_STATUS
|
|
EFIAPI
|
|
InitializeUsbDebugHardware (
|
|
IN USB3_DEBUG_PORT_HANDLE *Handle
|
|
);
|
|
|
|
/**
|
|
Return USB3 debug instance address pointer.
|
|
|
|
**/
|
|
EFI_PHYSICAL_ADDRESS *
|
|
GetUsb3DebugPortInstanceAddrPtr (
|
|
VOID
|
|
);
|
|
|
|
/**
|
|
Return USB3 debug instance address.
|
|
|
|
**/
|
|
USB3_DEBUG_PORT_HANDLE *
|
|
GetUsb3DebugPortInstance (
|
|
VOID
|
|
);
|
|
|
|
#endif //__SERIAL_PORT_LIB_USB__
|