577 lines
15 KiB
C
577 lines
15 KiB
C
/** @file
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Debug Port Library implementation based on usb3 debug port.
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Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "DebugCommunicationLibUsb3Internal.h"
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/**
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Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
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@param Handle Debug port handle.
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@param TrsRing The transfer ring to sync.
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@retval EFI_SUCCESS The transfer ring is synchronized successfully.
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**/
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EFI_STATUS
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EFIAPI
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XhcSyncTrsRing (
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IN USB3_DEBUG_PORT_HANDLE *Handle,
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IN TRANSFER_RING *TrsRing
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)
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{
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UINTN Index;
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TRB_TEMPLATE *TrsTrb;
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UINT32 CycleBit;
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ASSERT (TrsRing != NULL);
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//
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// Calculate the latest RingEnqueue and RingPCS
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//
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TrsTrb = (TRB_TEMPLATE *)(UINTN) TrsRing->RingEnqueue;
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ASSERT (TrsTrb != NULL);
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for (Index = 0; Index < TrsRing->TrbNumber; Index++) {
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if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
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break;
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}
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TrsTrb++;
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if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
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ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);
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//
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// set cycle bit in Link TRB as normal
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//
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((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
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//
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// Toggle PCS maintained by software
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//
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TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
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TrsTrb = (TRB_TEMPLATE *)(UINTN)((TrsTrb->Parameter1 | LShiftU64 ((UINT64)TrsTrb->Parameter2, 32)) & ~0x0F);
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}
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}
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ASSERT (Index != TrsRing->TrbNumber);
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if ((EFI_PHYSICAL_ADDRESS)(UINTN) TrsTrb != TrsRing->RingEnqueue) {
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TrsRing->RingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN) TrsTrb;
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}
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//
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// Clear the Trb context for enqueue, but reserve the PCS bit which indicates free Trb.
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//
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CycleBit = TrsTrb->CycleBit;
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ZeroMem (TrsTrb, sizeof (TRB_TEMPLATE));
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TrsTrb->CycleBit = CycleBit;
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return EFI_SUCCESS;
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}
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/**
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Synchronize the specified event ring to update the enqueue and dequeue pointer.
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@param Handle Debug port handle.
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@param EvtRing The event ring to sync.
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@retval EFI_SUCCESS The event ring is synchronized successfully.
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**/
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EFI_STATUS
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EFIAPI
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XhcSyncEventRing (
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IN USB3_DEBUG_PORT_HANDLE *Handle,
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IN EVENT_RING *EvtRing
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)
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{
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UINTN Index;
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TRB_TEMPLATE *EvtTrb1;
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ASSERT (EvtRing != NULL);
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//
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// Calculate the EventRingEnqueue and EventRingCCS.
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// Note: only support single Segment
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//
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EvtTrb1 = (TRB_TEMPLATE *)(UINTN) EvtRing->EventRingDequeue;
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for (Index = 0; Index < EvtRing->TrbNumber; Index++) {
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if (EvtTrb1->CycleBit != EvtRing->EventRingCCS) {
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break;
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}
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EvtTrb1++;
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if ((UINTN)EvtTrb1 >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
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EvtTrb1 = (TRB_TEMPLATE *)(UINTN) EvtRing->EventRingSeg0;
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EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;
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}
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}
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if (Index < EvtRing->TrbNumber) {
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EvtRing->EventRingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN)EvtTrb1;
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} else {
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ASSERT (FALSE);
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}
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return EFI_SUCCESS;
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}
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/**
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Check if there is a new generated event.
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@param Handle Debug port handle.
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@param EvtRing The event ring to check.
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@param NewEvtTrb The new event TRB found.
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@retval EFI_SUCCESS Found a new event TRB at the event ring.
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@retval EFI_NOT_READY The event ring has no new event.
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**/
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EFI_STATUS
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EFIAPI
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XhcCheckNewEvent (
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IN USB3_DEBUG_PORT_HANDLE *Handle,
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IN EVENT_RING *EvtRing,
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OUT TRB_TEMPLATE **NewEvtTrb
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)
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{
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EFI_STATUS Status;
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ASSERT (EvtRing != NULL);
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*NewEvtTrb = (TRB_TEMPLATE *)(UINTN) EvtRing->EventRingDequeue;
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if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {
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return EFI_NOT_READY;
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}
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Status = EFI_SUCCESS;
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EvtRing->EventRingDequeue += sizeof (TRB_TEMPLATE);
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//
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// If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
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//
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if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
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EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
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}
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return Status;
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}
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/**
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Check if the Trb is a transaction of the URB.
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@param Ring The transfer ring to be checked.
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@param Trb The TRB to be checked.
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@retval TRUE It is a transaction of the URB.
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@retval FALSE It is not any transaction of the URB.
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**/
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BOOLEAN
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IsTrbInTrsRing (
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IN TRANSFER_RING *Ring,
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IN TRB_TEMPLATE *Trb
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)
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{
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TRB_TEMPLATE *CheckedTrb;
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UINTN Index;
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CheckedTrb = (TRB_TEMPLATE *)(UINTN) Ring->RingSeg0;
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ASSERT (Ring->TrbNumber == TR_RING_TRB_NUMBER);
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for (Index = 0; Index < Ring->TrbNumber; Index++) {
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if (Trb == CheckedTrb) {
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return TRUE;
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}
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CheckedTrb++;
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}
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return FALSE;
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}
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/**
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Check the URB's execution result and update the URB's
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result accordingly.
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@param Handle Debug port handle.
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@param Urb The URB to check result.
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**/
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VOID
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XhcCheckUrbResult (
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IN USB3_DEBUG_PORT_HANDLE *Handle,
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IN URB *Urb
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)
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{
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EVT_TRB_TRANSFER *EvtTrb;
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TRB_TEMPLATE *TRBPtr;
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UINTN Index;
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EFI_STATUS Status;
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URB *CheckedUrb;
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UINT64 XhcDequeue;
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UINT32 High;
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UINT32 Low;
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ASSERT ((Handle != NULL) && (Urb != NULL));
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if (Urb->Finished) {
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goto EXIT;
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}
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EvtTrb = NULL;
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//
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// Traverse the event ring to find out all new events from the previous check.
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//
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XhcSyncEventRing (Handle, &Handle->EventRing);
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for (Index = 0; Index < Handle->EventRing.TrbNumber; Index++) {
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Status = XhcCheckNewEvent (Handle, &Handle->EventRing, ((TRB_TEMPLATE **)&EvtTrb));
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if (Status == EFI_NOT_READY) {
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//
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// All new events are handled, return directly.
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//
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goto EXIT;
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}
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if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {
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continue;
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}
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TRBPtr = (TRB_TEMPLATE *)(UINTN)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
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if (IsTrbInTrsRing ((TRANSFER_RING *)(UINTN)(Urb->Ring), TRBPtr)) {
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CheckedUrb = Urb;
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} else if (IsTrbInTrsRing ((TRANSFER_RING *)(UINTN)(Handle->UrbIn.Ring), TRBPtr)) {
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//
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// If it is read event and it should be generated by poll, and current operation is write, we need save data into internal buffer.
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// Internal buffer is used by next read.
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//
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Handle->DataCount = (UINT8) (Handle->UrbIn.DataLen - EvtTrb->Length);
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CopyMem ((VOID *)(UINTN)Handle->Data, (VOID *)(UINTN)Handle->UrbIn.Data, Handle->DataCount);
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//
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// Fill this TRB complete with CycleBit, otherwise next read will fail with old TRB.
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//
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TRBPtr->CycleBit = (TRBPtr->CycleBit & BIT0) ? 0 : 1;
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continue;
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} else {
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continue;
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}
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if ((EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) ||
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(EvtTrb->Completecode == TRB_COMPLETION_SUCCESS)) {
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//
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// The length of data which were transferred.
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//
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CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);
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} else {
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CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
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}
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//
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// This Urb has been processed
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//
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CheckedUrb->Finished = TRUE;
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}
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EXIT:
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//
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// Advance event ring to last available entry
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//
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// Some 3rd party XHCI external cards don't support single 64-bytes width register access,
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// So divide it to two 32-bytes width register access.
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//
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Low = XhcReadDebugReg (Handle, XHC_DC_DCERDP);
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High = XhcReadDebugReg (Handle, XHC_DC_DCERDP + 4);
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XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);
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if ((XhcDequeue & (~0x0F)) != ((UINT64)(UINTN)Handle->EventRing.EventRingDequeue & (~0x0F))) {
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//
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// Some 3rd party XHCI external cards don't support single 64-bytes width register access,
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// So divide it to two 32-bytes width register access.
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//
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XhcWriteDebugReg (Handle, XHC_DC_DCERDP, XHC_LOW_32BIT (Handle->EventRing.EventRingDequeue));
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XhcWriteDebugReg (Handle, XHC_DC_DCERDP + 4, XHC_HIGH_32BIT (Handle->EventRing.EventRingDequeue));
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}
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}
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/**
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Ring the door bell to notify XHCI there is a transaction to be executed.
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@param Handle Debug port handle.
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@param Urb The pointer to URB.
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@retval EFI_SUCCESS Successfully ring the door bell.
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**/
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EFI_STATUS
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EFIAPI
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XhcRingDoorBell (
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IN USB3_DEBUG_PORT_HANDLE *Handle,
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IN URB *Urb
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)
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{
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UINT32 Dcdb;
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//
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// 7.6.8.2 DCDB Register
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//
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Dcdb = (Urb->Direction == EfiUsbDataIn) ? 0x100 : 0x0;
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XhcWriteDebugReg (
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Handle,
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XHC_DC_DCDB,
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Dcdb
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);
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return EFI_SUCCESS;
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}
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/**
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Execute the transfer by polling the URB. This is a synchronous operation.
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@param Handle Debug port handle.
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@param Urb The URB to execute.
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@param Timeout The time to wait before abort, in microsecond.
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**/
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VOID
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XhcExecTransfer (
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IN USB3_DEBUG_PORT_HANDLE *Handle,
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IN URB *Urb,
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IN UINTN Timeout
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)
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{
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TRANSFER_RING *Ring;
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TRB_TEMPLATE *Trb;
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UINTN Loop;
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UINTN Index;
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Loop = Timeout / XHC_DEBUG_PORT_1_MILLISECOND;
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if (Timeout == 0) {
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Loop = 0xFFFFFFFF;
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}
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XhcRingDoorBell (Handle, Urb);
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//
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// Event Ring Not Empty bit can only be set to 1 by XHC after ringing door bell with some delay.
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//
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for (Index = 0; Index < Loop; Index++) {
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XhcCheckUrbResult (Handle, Urb);
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if (Urb->Finished) {
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break;
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}
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MicroSecondDelay (XHC_DEBUG_PORT_1_MILLISECOND);
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}
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if (Index == Loop) {
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//
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// If time out occurs.
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//
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Urb->Result |= EFI_USB_ERR_TIMEOUT;
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}
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//
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// If URB transfer is error, restore transfer ring to original value before URB transfer
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// This will make the current transfer TRB is always at the latest unused one in transfer ring.
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//
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Ring = (TRANSFER_RING *)(UINTN) Urb->Ring;
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if ((Urb->Result != EFI_USB_NOERROR) && (Urb->Direction == EfiUsbDataIn)) {
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//
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// Adjust Enqueue pointer
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//
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Ring->RingEnqueue = Urb->Trb;
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//
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// Clear CCS flag for next use
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//
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Trb = (TRB_TEMPLATE *)(UINTN) Urb->Trb;
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Trb->CycleBit = ((~Ring->RingPCS) & BIT0);
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} else {
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//
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// Update transfer ring for next transfer.
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//
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XhcSyncTrsRing (Handle, Ring);
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}
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}
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/**
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Create a transfer TRB.
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@param Handle Debug port handle.
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@param Urb The urb used to construct the transfer TRB.
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@return Created TRB or NULL
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**/
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EFI_STATUS
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XhcCreateTransferTrb (
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IN USB3_DEBUG_PORT_HANDLE *Handle,
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IN URB *Urb
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)
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{
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TRANSFER_RING *EPRing;
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TRB *Trb;
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if (Urb->Direction == EfiUsbDataIn) {
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EPRing = &Handle->TransferRingIn;
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} else {
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EPRing = &Handle->TransferRingOut;
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}
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Urb->Ring = (EFI_PHYSICAL_ADDRESS)(UINTN) EPRing;
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XhcSyncTrsRing (Handle, EPRing);
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Urb->Trb = EPRing->RingEnqueue;
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Trb = (TRB *)(UINTN)EPRing->RingEnqueue;
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Trb->TrbNormal.TRBPtrLo = XHC_LOW_32BIT (Urb->Data);
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Trb->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT (Urb->Data);
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Trb->TrbNormal.Length = Urb->DataLen;
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Trb->TrbNormal.TDSize = 0;
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Trb->TrbNormal.IntTarget = 0;
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Trb->TrbNormal.ISP = 1;
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Trb->TrbNormal.IOC = 1;
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Trb->TrbNormal.Type = TRB_TYPE_NORMAL;
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//
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// Update the cycle bit to indicate this TRB has been consumed.
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//
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Trb->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;
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return EFI_SUCCESS;
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}
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/**
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Create a new URB for a new transaction.
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@param Handle Debug port handle.
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@param Direction The direction of data flow.
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@param Data The user data to transfer
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@param DataLen The length of data buffer
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@return Created URB or NULL
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**/
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URB*
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XhcCreateUrb (
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IN USB3_DEBUG_PORT_HANDLE *Handle,
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IN EFI_USB_DATA_DIRECTION Direction,
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IN VOID *Data,
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IN UINTN DataLen
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)
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{
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EFI_STATUS Status;
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URB *Urb;
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EFI_PHYSICAL_ADDRESS UrbData;
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if (Direction == EfiUsbDataIn) {
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Urb = &Handle->UrbIn;
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} else {
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Urb = &Handle->UrbOut;
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}
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UrbData = Urb->Data;
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ZeroMem (Urb, sizeof (URB));
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Urb->Direction = Direction;
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//
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// Allocate memory to move data from CAR or SMRAM to normal memory
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// to make XHCI DMA successfully
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// re-use the pre-allocate buffer in PEI to avoid DXE memory service or gBS are not ready
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//
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Urb->Data = UrbData;
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if (Direction == EfiUsbDataIn) {
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//
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// Do not break URB data in buffer as it may contain the data which were just put in via DMA by XHC
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//
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Urb->DataLen = (UINT32) DataLen;
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} else {
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//
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// Put data into URB data out buffer which will create TRBs
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//
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ZeroMem ((VOID*)(UINTN) Urb->Data, DataLen);
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CopyMem ((VOID*)(UINTN) Urb->Data, Data, DataLen);
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Urb->DataLen = (UINT32) DataLen;
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}
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Status = XhcCreateTransferTrb (Handle, Urb);
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ASSERT_EFI_ERROR (Status);
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return Urb;
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}
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/**
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Submits bulk transfer to a bulk endpoint of a USB device.
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@param Handle Debug port handle.
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@param Direction The direction of data transfer.
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@param Data Array of pointers to the buffers of data to transmit
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from or receive into.
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@param DataLength The lenght of the data buffer.
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@param Timeout Indicates the maximum time, in microsecond, which
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the transfer is allowed to complete.
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@retval EFI_SUCCESS The transfer was completed successfully.
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@retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.
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@retval EFI_INVALID_PARAMETER Some parameters are invalid.
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@retval EFI_TIMEOUT The transfer failed due to timeout.
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@retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
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**/
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EFI_STATUS
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EFIAPI
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XhcDataTransfer (
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IN USB3_DEBUG_PORT_HANDLE *Handle,
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IN EFI_USB_DATA_DIRECTION Direction,
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IN OUT VOID *Data,
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IN OUT UINTN *DataLength,
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IN UINTN Timeout
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)
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{
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URB *Urb;
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EFI_STATUS Status;
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//
|
|
// Validate the parameters
|
|
//
|
|
if ((DataLength == NULL) || (*DataLength == 0) || (Data == NULL)) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
|
|
//
|
|
// Create a new URB, insert it into the asynchronous
|
|
// schedule list, then poll the execution status.
|
|
//
|
|
Urb = XhcCreateUrb (Handle, Direction, Data, *DataLength);
|
|
ASSERT (Urb != NULL);
|
|
|
|
XhcExecTransfer (Handle, Urb, Timeout);
|
|
|
|
//
|
|
// Make sure the data received from HW can fit in the received buffer.
|
|
//
|
|
if (Urb->Completed > *DataLength) {
|
|
return EFI_DEVICE_ERROR;
|
|
}
|
|
|
|
*DataLength = Urb->Completed;
|
|
|
|
Status = EFI_TIMEOUT;
|
|
if (Urb->Result == EFI_USB_NOERROR) {
|
|
Status = EFI_SUCCESS;
|
|
}
|
|
|
|
if (Direction == EfiUsbDataIn) {
|
|
//
|
|
// Move data from internal buffer to outside buffer (outside buffer may be in SMRAM...)
|
|
// SMRAM does not allow to do DMA, so we create an internal buffer.
|
|
//
|
|
CopyMem (Data, (VOID *)(UINTN)Urb->Data, *DataLength);
|
|
}
|
|
|
|
return Status;
|
|
}
|
|
|