204 lines
6.6 KiB
C
204 lines
6.6 KiB
C
/** @file
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SMM CPU misc functions for Ia32 arch specific.
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Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PiSmmCpuDxeSmm.h"
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extern UINT64 gTaskGateDescriptor;
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EFI_PHYSICAL_ADDRESS mGdtBuffer;
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UINTN mGdtBufferSize;
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extern BOOLEAN mCetSupported;
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extern UINTN mSmmShadowStackSize;
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X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp;
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X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp;
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UINT32 mCetPl0Ssp;
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UINT32 mCetInterruptSsp;
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/**
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Initialize IDT for SMM Stack Guard.
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**/
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VOID
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EFIAPI
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InitializeIDTSmmStackGuard (
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VOID
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)
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{
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IA32_IDT_GATE_DESCRIPTOR *IdtGate;
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//
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// If SMM Stack Guard feature is enabled, the Page Fault Exception entry in IDT
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// is a Task Gate Descriptor so that when a Page Fault Exception occurs,
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// the processors can use a known good stack in case stack is ran out.
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//
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IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
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IdtGate += EXCEPT_IA32_PAGE_FAULT;
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IdtGate->Uint64 = gTaskGateDescriptor;
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}
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/**
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Initialize Gdt for all processors.
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@param[in] Cr3 CR3 value.
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@param[out] GdtStepSize The step size for GDT table.
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@return GdtBase for processor 0.
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GdtBase for processor X is: GdtBase + (GdtStepSize * X)
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**/
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VOID *
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InitGdt (
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IN UINTN Cr3,
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OUT UINTN *GdtStepSize
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)
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{
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UINTN Index;
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IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;
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UINTN TssBase;
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UINTN GdtTssTableSize;
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UINT8 *GdtTssTables;
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UINTN GdtTableStepSize;
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UINTN InterruptShadowStack;
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if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
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//
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// For IA32 SMM, if SMM Stack Guard feature is enabled, we use 2 TSS.
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// in this case, we allocate separate GDT/TSS for each CPUs to avoid TSS load contention
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// on each SMI entry.
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//
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//
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// Enlarge GDT to contain 2 TSS descriptors
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//
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gcSmiGdtr.Limit += (UINT16)(2 * sizeof (IA32_SEGMENT_DESCRIPTOR));
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GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE + 7) & ~7; // 8 bytes aligned
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mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
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//
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// IA32 Stack Guard need use task switch to switch stack that need
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// write GDT and TSS, so AllocateCodePages() could not be used here
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// as code pages will be set to RO.
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//
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GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
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ASSERT (GdtTssTables != NULL);
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mGdtBuffer = (UINTN)GdtTssTables;
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GdtTableStepSize = GdtTssTableSize;
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for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
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CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE);
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//
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// Fixup TSS descriptors
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//
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TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);
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GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;
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GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;
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GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);
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GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24);
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TssBase += TSS_SIZE;
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GdtDescriptor++;
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GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;
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GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);
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GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24);
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//
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// Fixup TSS segments
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//
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// ESP as known good stack
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//
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*(UINTN *)(TssBase + TSS_IA32_ESP_OFFSET) = mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize;
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*(UINT32 *)(TssBase + TSS_IA32_CR3_OFFSET) = Cr3;
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//
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// Setup ShadowStack for stack switch
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//
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if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {
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InterruptShadowStack = (UINTN)(mSmmStackArrayBase + mSmmStackSize + EFI_PAGES_TO_SIZE (1) - sizeof(UINT64) + (mSmmStackSize + mSmmShadowStackSize) * Index);
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*(UINT32 *)(TssBase + TSS_IA32_SSP_OFFSET) = (UINT32)InterruptShadowStack;
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}
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}
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} else {
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//
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// Just use original table, AllocatePage and copy them here to make sure GDTs are covered in page memory.
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//
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GdtTssTableSize = gcSmiGdtr.Limit + 1;
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mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
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GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
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ASSERT (GdtTssTables != NULL);
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mGdtBuffer = (UINTN)GdtTssTables;
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GdtTableStepSize = GdtTssTableSize;
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for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
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CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1);
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}
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}
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*GdtStepSize = GdtTableStepSize;
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return GdtTssTables;
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}
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/**
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Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.
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@param[in] ApHltLoopCode The address of the safe hlt-loop function.
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@param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.
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@param[in] NumberToFinishAddress Address of Semaphore of APs finish count.
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**/
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VOID
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TransferApToSafeState (
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IN UINTN ApHltLoopCode,
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IN UINTN TopOfStack,
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IN UINTN NumberToFinishAddress
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)
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{
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SwitchStack (
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(SWITCH_STACK_ENTRY_POINT)ApHltLoopCode,
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(VOID *)NumberToFinishAddress,
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NULL,
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(VOID *)TopOfStack
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);
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//
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// It should never reach here
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//
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ASSERT (FALSE);
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}
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/**
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Initialize the shadow stack related data structure.
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@param CpuIndex The index of CPU.
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@param ShadowStack The bottom of the shadow stack for this CPU.
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**/
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VOID
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InitShadowStack (
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IN UINTN CpuIndex,
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IN VOID *ShadowStack
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)
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{
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UINTN SmmShadowStackSize;
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if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {
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SmmShadowStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize)));
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if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
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SmmShadowStackSize += EFI_PAGES_TO_SIZE (2);
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}
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mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof(UINT64));
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PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4);
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DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp));
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DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack));
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DEBUG ((DEBUG_INFO, " SmmShadowStackSize - 0x%x\n", SmmShadowStackSize));
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if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
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mCetInterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - sizeof(UINT64));
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PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4);
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DEBUG ((DEBUG_INFO, "mCetInterruptSsp - 0x%x\n", mCetInterruptSsp));
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}
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}
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}
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