205 lines
6.2 KiB
C
205 lines
6.2 KiB
C
/** @file
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SMM CPU misc functions for x64 arch specific.
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Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PiSmmCpuDxeSmm.h"
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EFI_PHYSICAL_ADDRESS mGdtBuffer;
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UINTN mGdtBufferSize;
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extern BOOLEAN mCetSupported;
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extern UINTN mSmmShadowStackSize;
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X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp;
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X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp;
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X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSspTable;
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UINT32 mCetPl0Ssp;
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UINT32 mCetInterruptSsp;
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UINT32 mCetInterruptSspTable;
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UINTN mSmmInterruptSspTables;
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/**
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Initialize IDT for SMM Stack Guard.
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**/
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VOID
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EFIAPI
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InitializeIDTSmmStackGuard (
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VOID
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)
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{
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IA32_IDT_GATE_DESCRIPTOR *IdtGate;
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//
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// If SMM Stack Guard feature is enabled, set the IST field of
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// the interrupt gate for Page Fault Exception to be 1
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//
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IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
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IdtGate += EXCEPT_IA32_PAGE_FAULT;
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IdtGate->Bits.Reserved_0 = 1;
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}
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/**
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Initialize Gdt for all processors.
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@param[in] Cr3 CR3 value.
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@param[out] GdtStepSize The step size for GDT table.
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@return GdtBase for processor 0.
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GdtBase for processor X is: GdtBase + (GdtStepSize * X)
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**/
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VOID *
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InitGdt (
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IN UINTN Cr3,
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OUT UINTN *GdtStepSize
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)
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{
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UINTN Index;
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IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;
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UINTN TssBase;
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UINTN GdtTssTableSize;
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UINT8 *GdtTssTables;
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UINTN GdtTableStepSize;
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//
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// For X64 SMM, we allocate separate GDT/TSS for each CPUs to avoid TSS load contention
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// on each SMI entry.
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//
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GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + 7) & ~7; // 8 bytes aligned
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mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
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GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
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ASSERT (GdtTssTables != NULL);
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mGdtBuffer = (UINTN)GdtTssTables;
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GdtTableStepSize = GdtTssTableSize;
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for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
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CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE);
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//
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// Fixup TSS descriptors
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//
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TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);
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GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;
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GdtDescriptor->Bits.BaseLow = (UINT16)(UINTN)TssBase;
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GdtDescriptor->Bits.BaseMid = (UINT8)((UINTN)TssBase >> 16);
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GdtDescriptor->Bits.BaseHigh = (UINT8)((UINTN)TssBase >> 24);
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if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
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//
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// Setup top of known good stack as IST1 for each processor.
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//
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*(UINTN *)(TssBase + TSS_X64_IST1_OFFSET) = (mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize);
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}
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}
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*GdtStepSize = GdtTableStepSize;
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return GdtTssTables;
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}
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/**
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Get Protected mode code segment from current GDT table.
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@return Protected mode code segment value.
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**/
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UINT16
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GetProtectedModeCS (
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VOID
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)
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{
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IA32_DESCRIPTOR GdtrDesc;
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IA32_SEGMENT_DESCRIPTOR *GdtEntry;
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UINTN GdtEntryCount;
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UINT16 Index;
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AsmReadGdtr (&GdtrDesc);
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GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
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GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;
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for (Index = 0; Index < GdtEntryCount; Index++) {
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if (GdtEntry->Bits.L == 0) {
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if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.L == 0) {
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break;
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}
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}
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GdtEntry++;
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}
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ASSERT (Index != GdtEntryCount);
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return Index * 8;
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}
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/**
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Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.
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@param[in] ApHltLoopCode The address of the safe hlt-loop function.
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@param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.
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@param[in] NumberToFinishAddress Address of Semaphore of APs finish count.
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**/
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VOID
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TransferApToSafeState (
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IN UINTN ApHltLoopCode,
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IN UINTN TopOfStack,
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IN UINTN NumberToFinishAddress
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)
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{
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AsmDisablePaging64 (
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GetProtectedModeCS (),
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(UINT32)ApHltLoopCode,
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(UINT32)NumberToFinishAddress,
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0,
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(UINT32)TopOfStack
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);
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//
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// It should never reach here
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//
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ASSERT (FALSE);
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}
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/**
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Initialize the shadow stack related data structure.
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@param CpuIndex The index of CPU.
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@param ShadowStack The bottom of the shadow stack for this CPU.
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**/
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VOID
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InitShadowStack (
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IN UINTN CpuIndex,
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IN VOID *ShadowStack
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)
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{
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UINTN SmmShadowStackSize;
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UINT64 *InterruptSspTable;
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if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {
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SmmShadowStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize)));
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if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
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SmmShadowStackSize += EFI_PAGES_TO_SIZE (2);
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}
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mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof(UINT64));
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PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4);
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DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp));
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DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack));
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DEBUG ((DEBUG_INFO, " SmmShadowStackSize - 0x%x\n", SmmShadowStackSize));
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if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
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if (mSmmInterruptSspTables == 0) {
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mSmmInterruptSspTables = (UINTN)AllocateZeroPool(sizeof(UINT64) * 8 * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);
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ASSERT (mSmmInterruptSspTables != 0);
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DEBUG ((DEBUG_INFO, "mSmmInterruptSspTables - 0x%x\n", mSmmInterruptSspTables));
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}
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mCetInterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - sizeof(UINT64));
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mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof(UINT64) * 8 * CpuIndex);
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InterruptSspTable = (UINT64 *)(UINTN)mCetInterruptSspTable;
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InterruptSspTable[1] = mCetInterruptSsp;
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PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4);
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PatchInstructionX86 (mPatchCetInterruptSspTable, mCetInterruptSspTable, 4);
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DEBUG ((DEBUG_INFO, "mCetInterruptSsp - 0x%x\n", mCetInterruptSsp));
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DEBUG ((DEBUG_INFO, "mCetInterruptSspTable - 0x%x\n", mCetInterruptSspTable));
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}
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}
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}
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