313 lines
8.7 KiB
C
313 lines
8.7 KiB
C
/** @file
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X64 processor specific functions to enable SMM profile.
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Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PiSmmCpuDxeSmm.h"
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#include "SmmProfileInternal.h"
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//
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// Current page index.
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//
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UINTN mPFPageIndex;
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//
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// Pool for dynamically creating page table in page fault handler.
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//
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UINT64 mPFPageBuffer;
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//
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// Store the uplink information for each page being used.
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//
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UINT64 *mPFPageUplink[MAX_PF_PAGE_COUNT];
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/**
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Create SMM page table for S3 path.
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**/
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VOID
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InitSmmS3Cr3 (
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VOID
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)
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{
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EFI_PHYSICAL_ADDRESS Pages;
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UINT64 *PTEntry;
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//
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// Generate PAE page table for the first 4GB memory space
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//
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Pages = Gen4GPageTable (FALSE);
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//
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// Fill Page-Table-Level4 (PML4) entry
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//
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PTEntry = (UINT64*)AllocatePageTableMemory (1);
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ASSERT (PTEntry != NULL);
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*PTEntry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
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ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));
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//
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// Return the address of PML4 (to set CR3)
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//
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mSmmS3ResumeState->SmmS3Cr3 = (UINT32)(UINTN)PTEntry;
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return ;
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}
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/**
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Allocate pages for creating 4KB-page based on 2MB-page when page fault happens.
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**/
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VOID
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InitPagesForPFHandler (
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VOID
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)
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{
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VOID *Address;
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//
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// Pre-Allocate memory for page fault handler
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//
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Address = NULL;
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Address = AllocatePages (MAX_PF_PAGE_COUNT);
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ASSERT (Address != NULL);
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mPFPageBuffer = (UINT64)(UINTN) Address;
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mPFPageIndex = 0;
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ZeroMem ((VOID *) (UINTN) mPFPageBuffer, EFI_PAGE_SIZE * MAX_PF_PAGE_COUNT);
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ZeroMem (mPFPageUplink, sizeof (mPFPageUplink));
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return;
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}
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/**
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Allocate one page for creating 4KB-page based on 2MB-page.
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@param Uplink The address of Page-Directory entry.
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**/
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VOID
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AcquirePage (
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UINT64 *Uplink
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)
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{
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UINT64 Address;
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//
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// Get the buffer
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//
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Address = mPFPageBuffer + EFI_PAGES_TO_SIZE (mPFPageIndex);
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ZeroMem ((VOID *) (UINTN) Address, EFI_PAGE_SIZE);
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//
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// Cut the previous uplink if it exists and wasn't overwritten
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//
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if ((mPFPageUplink[mPFPageIndex] != NULL) && ((*mPFPageUplink[mPFPageIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK) == Address)) {
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*mPFPageUplink[mPFPageIndex] = 0;
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}
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//
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// Link & Record the current uplink
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//
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*Uplink = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
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mPFPageUplink[mPFPageIndex] = Uplink;
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mPFPageIndex = (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT;
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}
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/**
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Update page table to map the memory correctly in order to make the instruction
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which caused page fault execute successfully. And it also save the original page
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table to be restored in single-step exception.
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@param PageTable PageTable Address.
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@param PFAddress The memory address which caused page fault exception.
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@param CpuIndex The index of the processor.
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@param ErrorCode The Error code of exception.
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@param IsValidPFAddress The flag indicates if SMM profile data need be added.
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**/
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VOID
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RestorePageTableAbove4G (
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UINT64 *PageTable,
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UINT64 PFAddress,
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UINTN CpuIndex,
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UINTN ErrorCode,
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BOOLEAN *IsValidPFAddress
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)
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{
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UINTN PTIndex;
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UINT64 Address;
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BOOLEAN Nx;
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BOOLEAN Existed;
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UINTN Index;
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UINTN PFIndex;
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ASSERT ((PageTable != NULL) && (IsValidPFAddress != NULL));
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//
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// If page fault address is 4GB above.
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//
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//
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// Check if page fault address has existed in page table.
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// If it exists in page table but page fault is generated,
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// there are 2 possible reasons: 1. present flag is set to 0; 2. instruction fetch in protected memory range.
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//
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Existed = FALSE;
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PageTable = (UINT64*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);
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PTIndex = BitFieldRead64 (PFAddress, 39, 47);
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if ((PageTable[PTIndex] & IA32_PG_P) != 0) {
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// PML4E
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PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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PTIndex = BitFieldRead64 (PFAddress, 30, 38);
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if ((PageTable[PTIndex] & IA32_PG_P) != 0) {
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// PDPTE
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PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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PTIndex = BitFieldRead64 (PFAddress, 21, 29);
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// PD
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if ((PageTable[PTIndex] & IA32_PG_PS) != 0) {
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//
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// 2MB page
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//
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Address = (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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if ((Address & ~((1ull << 21) - 1)) == ((PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 21) - 1)))) {
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Existed = TRUE;
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}
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} else {
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//
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// 4KB page
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//
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PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask& PHYSICAL_ADDRESS_MASK);
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if (PageTable != 0) {
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//
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// When there is a valid entry to map to 4KB page, need not create a new entry to map 2MB.
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//
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PTIndex = BitFieldRead64 (PFAddress, 12, 20);
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Address = (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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if ((Address & ~((1ull << 12) - 1)) == (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) {
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Existed = TRUE;
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}
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}
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}
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}
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}
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//
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// If page entry does not existed in page table at all, create a new entry.
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//
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if (!Existed) {
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if (IsAddressValid (PFAddress, &Nx)) {
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//
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// If page fault address above 4GB is in protected range but it causes a page fault exception,
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// Will create a page entry for this page fault address, make page table entry as present/rw and execution-disable.
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// this access is not saved into SMM profile data.
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//
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*IsValidPFAddress = TRUE;
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}
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//
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// Create one entry in page table for page fault address.
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//
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SmiDefaultPFHandler ();
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//
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// Find the page table entry created just now.
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//
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PageTable = (UINT64*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);
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PFAddress = AsmReadCr2 ();
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// PML4E
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PTIndex = BitFieldRead64 (PFAddress, 39, 47);
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PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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// PDPTE
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PTIndex = BitFieldRead64 (PFAddress, 30, 38);
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PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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// PD
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PTIndex = BitFieldRead64 (PFAddress, 21, 29);
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Address = PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK;
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//
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// Check if 2MB-page entry need be changed to 4KB-page entry.
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//
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if (IsAddressSplit (Address)) {
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AcquirePage (&PageTable[PTIndex]);
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// PTE
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PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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for (Index = 0; Index < 512; Index++) {
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PageTable[Index] = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
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if (!IsAddressValid (Address, &Nx)) {
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PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
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}
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if (Nx && mXdSupported) {
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PageTable[Index] = PageTable[Index] | IA32_PG_NX;
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}
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if (Address == (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) {
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PTIndex = Index;
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}
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Address += SIZE_4KB;
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} // end for PT
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} else {
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//
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// Update 2MB page entry.
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//
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if (!IsAddressValid (Address, &Nx)) {
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//
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// Patch to remove present flag and rw flag.
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//
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PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
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}
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//
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// Set XD bit to 1
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//
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if (Nx && mXdSupported) {
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PageTable[PTIndex] = PageTable[PTIndex] | IA32_PG_NX;
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}
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}
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}
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//
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// Record old entries with non-present status
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// Old entries include the memory which instruction is at and the memory which instruction access.
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//
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//
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ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT);
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if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) {
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PFIndex = mPFEntryCount[CpuIndex];
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mLastPFEntryValue[CpuIndex][PFIndex] = PageTable[PTIndex];
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mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex];
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mPFEntryCount[CpuIndex]++;
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}
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//
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// Add present flag or clear XD flag to make page fault handler succeed.
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//
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PageTable[PTIndex] |= (UINT64)(PAGE_ATTRIBUTE_BITS);
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if ((ErrorCode & IA32_PF_EC_ID) != 0) {
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//
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// If page fault is caused by instruction fetch, clear XD bit in the entry.
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//
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PageTable[PTIndex] &= ~IA32_PG_NX;
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}
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return;
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}
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/**
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Clear TF in FLAGS.
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@param SystemContext A pointer to the processor context when
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the interrupt occurred on the processor.
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**/
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VOID
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ClearTrapFlag (
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IN OUT EFI_SYSTEM_CONTEXT SystemContext
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)
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{
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SystemContext.SystemContextX64->Rflags &= (UINTN) ~BIT8;
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}
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