533 lines
15 KiB
ArmAsm
533 lines
15 KiB
ArmAsm
/**
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** Standalone startup code for Linux PROM emulator.
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** Copyright 1999 Pete A. Zaitcev
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** This code is licensed under GNU General Public License.
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**/
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/*
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* $Id: head.S,v 1.12 2002/07/23 05:47:09 zaitcev Exp $
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*/
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#define __ASSEMBLY
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#include "psr.h"
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#include "asm/asi.h"
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#include "asm/crs.h"
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#include "cpustate.h"
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#define NO_QEMU_PROTOS
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#define NO_OPENBIOS_PROTOS
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#include "arch/common/fw_cfg.h"
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#define CFG_ADDR 0x00000510
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#define CFG_ASI 0x2d
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#define PHYS_JJ_INTR0 0x71E00000 /* CPU0 interrupt control registers */
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#define PHYS_SS10_INTR0 0xf1400000
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#define PHYS_SS2_INTR0 0xf5000000
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#define SER_ADDR2 0xf1000004
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#define PHYS_SS1000_SBI 0x02800000
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#define SER_ADDR1000 0x00200004
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#define WRITE_PAUSE nop; nop; nop; /* Have to do this after %wim/%psr chg */
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.globl entry, _entry, nwindows
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.section ".text", "ax"
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.align 8
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/* Memory map:
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*
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* Top +-------------------------+
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* | SMP CPU table |
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* | s + 0x1f00 ... 0x1f0f |
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* | s + 0x1f0c valid |
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* | s + 0x1f08 entry |
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* | s + 0x1f04 ctxtbl |
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* | s + 0x1f00 ctx |
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* +-------------------------+
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* | Bootstrap |
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* | MMU L3 tables 8 * 0x100 |
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* | s + 0xa00 ... 0x11ff |
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* +-------------------------+
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* | Bootstrap |
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* | MMU L2 tables 2 * 0x100 |
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* | s + 0x800 ... 0x9ff |
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* +-------------------------+
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* | Bootstrap |
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* | MMU L1 table 0x400 |
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* | s + 0x400 ... 0x7ff |
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* +-------------------------+
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* | Bootstrap |
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* | MMU L0/ctx table 0x400 |
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* | s + 0x000 ... 0x3ff |
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* +-------------------------+
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* | |
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* | ROM into RAM |
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* | |
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* +-------------------------+
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* : :
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* Bottom
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*/
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nwindows:
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.word 0
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/*
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* Entry point
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* We start execution from here.
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*/
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_entry:
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entry:
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/* Switch to our main context.
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* Main context is statically defined in C.
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*/
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! Check signature "QEMU"
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set CFG_ADDR, %g5
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mov FW_CFG_SIGNATURE, %g2
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stha %g2, [%g5] CFG_ASI
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add %g5, 2, %g5
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lduba [%g5] CFG_ASI, %g2
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cmp %g2, 'Q'
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bne bad_conf
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nop
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lduba [%g5] CFG_ASI, %g2
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cmp %g2, 'E'
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bne bad_conf
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nop
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lduba [%g5] CFG_ASI, %g2
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cmp %g2, 'M'
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bne bad_conf
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nop
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lduba [%g5] CFG_ASI, %g2
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cmp %g2, 'U'
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bne bad_conf
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nop
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! Get memory size from configuration device
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! NB: little endian format
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mov FW_CFG_RAM_SIZE, %g2
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sub %g5, 2, %g5
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stha %g2, [%g5] CFG_ASI
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add %g5, 2, %g5
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lduba [%g5] CFG_ASI, %g4
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lduba [%g5] CFG_ASI, %g3
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sll %g3, 8, %g3
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or %g3, %g4, %g4
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lduba [%g5] CFG_ASI, %g3
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sll %g3, 16, %g3
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or %g3, %g4, %g4
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lduba [%g5] CFG_ASI, %g3
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sll %g3, 24, %g3
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or %g3, %g4, %g1
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! %g1 contains end of memory
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! Get CPU number
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! XXX: not all CPUs should have MXCC
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set 0x1c00f00, %g2
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ldda [%g2] ASI_CONTROL, %g2
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srl %g3, 24, %g7
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subcc %g7, 8, %g7
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! Only the first CPU clears memory
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bnz clear_done
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nop
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! Get kernel address from configuration device
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! NB: little endian format
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mov FW_CFG_KERNEL_ADDR, %g2
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sub %g5, 2, %g5
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stha %g2, [%g5] CFG_ASI
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add %g5, 2, %g5
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lduba [%g5] CFG_ASI, %g4
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lduba [%g5] CFG_ASI, %g3
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sll %g3, 8, %g3
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or %g3, %g4, %g4
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lduba [%g5] CFG_ASI, %g3
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sll %g3, 16, %g3
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or %g3, %g4, %g4
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lduba [%g5] CFG_ASI, %g3
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sll %g3, 24, %g3
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or %g3, %g4, %g4
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! If kernel address is set, don't clear from base of RAM in order to
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! leave the kernel image intact
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mov 0, %g6
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cmp %g4, 0
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beq clear_mem
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nop
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! Start from 16M
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set 0x1000000, %g6
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clear_mem:
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sta %g0, [%g6] ASI_M_BYPASS
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add %g6, 0x4, %g6
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cmp %g6, %g1
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bl clear_mem
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nop
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clear_done:
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! Start of private memory in %g6
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set 0x2000, %g3
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sub %g1, %g3, %g6
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! Get machine ID from configuration device
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mov FW_CFG_MACHINE_ID, %g2
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sub %g5, 2, %g5
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stha %g2, [%g5] CFG_ASI
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add %g5, 2, %g5
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lduba [%g5] CFG_ASI, %g4
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lduba [%g5] CFG_ASI, %g3
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sll %g3, 8, %g3
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or %g3, %g4, %g4
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mov %g4, %y
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cmp %g4, 96
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bgeu ss1000
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cmp %g4, 64
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bgeu ss10
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cmp %g4, 32
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blu ss2
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nop
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! Ok, this is SS-5, uniprocessor
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ba first_cpu
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nop
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ss10:
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! Ok, this is SS-10/20 or SS-600MP
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tst %g7
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bz first_cpu
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nop
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! Clear softints used for SMP CPU startup
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set PHYS_SS10_INTR0 + 0x04, %g1
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sll %g7, 12, %g2
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add %g1, %g2, %g2
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set 0xffffffff, %g1
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sta %g1, [%g2] ASI_M_CTL ! clear softints
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add %g2, 4, %g2
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sta %g0, [%g2] ASI_M_CTL ! clear softints
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! SMP init, jump to user specified address
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set 0x1f04, %g5
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add %g6, %g5, %g5 ! ctxtbl
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lda [%g5] ASI_M_BYPASS, %g2
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sta %g0, [%g5] ASI_M_BYPASS
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set AC_M_CTPR, %g1
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sta %g2, [%g1] ASI_M_MMUREGS ! set ctx table ptr
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set 0x1f00, %g5
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add %g6, %g5, %g5 ! ctx
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lda [%g5] ASI_M_BYPASS, %g2
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sta %g0, [%g5] ASI_M_BYPASS
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set AC_M_CXR, %g1
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sta %g2, [%g1] ASI_M_MMUREGS ! set context
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set 0x1f08, %g5
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add %g6, %g5, %g5 ! entry
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lda [%g5] ASI_M_BYPASS, %g2
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sta %g0, [%g5] ASI_M_BYPASS
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set 1, %g1
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jmp %g2 ! jump to kernel
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sta %g1, [%g0] ASI_M_MMUREGS ! enable mmu
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ss2:
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! Ok, this is SS-2
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set ss2_error, %o2
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b ss2_ss1000_halt
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nop
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ss1000:
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! Ok, this is SS-1000 or SS-2000
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set ss1000_error, %o2
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b ss2_ss1000_halt
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nop
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first_cpu:
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/* Create temporary page tables and map the ROM area to end of
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RAM. This will be done properly in iommu.c later. */
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! Calculate start of page tables etc. to %g6
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set 0x2000, %g4
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sub %g1, %g4, %g6 ! start of private memory
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mov %g6, %g2 ! ctx table at s+0x0
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add %g2, 0x400, %g3 ! l1 table at s+0x400
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 0x400, %g2 ! s+0x400
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add %g2, 0x400, %g3 ! l2 table for ram (00xxxxxx) at s+0x800
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 0x500, %g3 ! l2 table for rom (ffxxxxxx) at s+0x900
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add %g2, 0x3fc, %g2 ! s+0x7fc
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 0x4, %g2 ! s+0x800
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#if 0
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set 0x40, %g6
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set ((7 << 2) | 2), %g3 ! 7 = U: --- S: RWX (main memory)
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1: sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2
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deccc %g6
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bne 1b
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nop
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#else
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add %g2, 0x100, %g2
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#endif
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! s+0x900
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add %g2, 0xa00 - 0x900, %g3 ! l3 table for rom at s+0xa00
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add %g2, 0x0d0, %g2 ! s+0x9d0
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2 ! s+0x9d4
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add %g2, 0xb00 - 0x9d4, %g3 ! 2nd l3 table for rom at s+0xb00
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2 ! s+0x9d8
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add %g2, 0xc00 - 0x9d8, %g3 ! 3rd l3 table for rom at s+0xc00
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2 ! s+0x9dc
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add %g2, 0xd00 - 0x9dc, %g3 ! 4th l3 table for rom at s+0xd00
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2 ! s+0x9e0
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add %g2, 0xe00 - 0x9e0, %g3 ! 5th l3 table for rom at s+0xe00
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2 ! s+0x9e4
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add %g2, 0xf00 - 0x9e4, %g3 ! 6th l3 table for rom at s+0xf00
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2 ! s+0x9e8
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add %g2, 0x1000 - 0x9e8, %g3 ! 7th l3 table for rom at s+0x1000
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2 ! s+0x9ec
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add %g2, 0x1100 - 0x9ec, %g3 ! 8th l3 table for rom at s+0x1100
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 0xa00-0x9ec, %g2 ! s+0xa00
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/* Use end of ram for code, rodata, data, and bss
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sections. SunOS wants to write to trap table... */
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set _end, %g6
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set _start, %g4
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sub %g6, %g4, %g6
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sub %g1, %g6, %g3
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set 0x1000, %g5
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sub %g3, %g5, %g3
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sub %g3, %g5, %g3 ! start of ROM copy
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mov %g3, %g7 ! save in %g7
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srl %g6, 12, %g6 ! # of all pages
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1: srl %g3, 0x4, %g4
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or %g4, ((7 << 2) | 2), %g4 ! 7 = U: --- S: RWX
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sta %g4, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2
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add %g3, %g5, %g3
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deccc %g6
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bne 1b
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nop
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mov %g1, %g6 ! %g6 = memory size
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/* Copy the code, rodata and data sections from ROM. */
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sub %g7, 4, %g3
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set _start - 4, %g4 ! First address of TEXT - 4
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set _bss, %g5 ! Last address of DATA
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ba 2f
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nop
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1:
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lda [%g4] ASI_M_KERNELTXT, %g1
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sta %g1, [%g3] ASI_M_BYPASS
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2:
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cmp %g4, %g5
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add %g3, 0x4, %g3
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bl 1b
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add %g4, 0x4, %g4
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set 0x2000, %g3
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sub %g6, %g3, %g7 ! ctx table at s+0x0
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set AC_M_CTPR, %g2
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srl %g7, 4, %g7
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sta %g7, [%g2] ASI_M_MMUREGS ! set ctx table ptr
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set AC_M_CXR, %g2
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sta %g0, [%g2] ASI_M_MMUREGS ! context 0
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set highmem, %g2
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set 1, %g1
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jmp %g2
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sta %g1, [%g0] ASI_M_MMUREGS ! enable mmu
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highmem:
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/*
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* The code which enables traps is a simplified version of
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* kernel head.S.
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*
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* We know number of windows as 8 so we do not calculate them.
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* The deadwood is here for any case.
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*/
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/* Turn on Supervisor, EnableFloating, and all the PIL bits.
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* Also puts us in register window zero with traps off.
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*/
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set (PSR_PS | PSR_S | PSR_PIL | PSR_EF), %g2
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wr %g2, 0x0, %psr
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WRITE_PAUSE
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/* Zero out our BSS section. */
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set _bss - 4, %o0 ! First address of BSS
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set _estack - 4, %o1 ! Last address of BSS
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ba 2f
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nop
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1:
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st %g0, [%o0]
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2:
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subcc %o0, %o1, %g0
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bl 1b
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add %o0, 0x4, %o0
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set trap_table, %g1
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wr %g1, 0x0, %tbr
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set qemu_mem_size, %g1
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st %g6, [%g1]
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set _end, %o0 ! Store va->pa conversion factor
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set _start, %o2
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sub %o0, %o2, %o0
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sub %g6, %o0, %o0
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set 0x2000, %o1
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sub %o0, %o1, %o0 ! start of ROM copy
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sub %o2, %o0, %o0 ! start of ROM copy
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set va_shift, %g1
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st %o0, [%g1]
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set qemu_machine_type, %g1
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mov %y, %g2
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st %g2, [%g1]
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/* Compute NWINDOWS and stash it away. Now uses %wim trick explained
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* in the V8 manual. Ok, this method seems to work, Sparc is cool...
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* No, it doesn't work, have to play the save/readCWP/restore trick.
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*/
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wr %g0, 0x0, %wim ! so we do not get a trap
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WRITE_PAUSE
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save
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rd %psr, %g3
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restore
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and %g3, 0x1f, %g3
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add %g3, 0x1, %g3
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mov 2, %g1
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wr %g1, 0x0, %wim ! make window 1 invalid
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WRITE_PAUSE
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set nwindows, %g2 ! store nwindows
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st %g3, [%g2]
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cmp %g3, 0x7
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bne 1f
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nop
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/* Adjust our window handling routines to
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* do things correctly on 7 window Sparcs.
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*/
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#define PATCH_INSN(src, dest) \
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set src, %g5; \
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set dest, %g2; \
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ld [%g5], %g4; \
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st %g4, [%g2];
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/* Patch for window spills... */
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PATCH_INSN(spnwin_patch1_7win, spnwin_patch1)
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PATCH_INSN(spnwin_patch2_7win, spnwin_patch2)
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/* Patch for window fills... */
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PATCH_INSN(fnwin_patch1_7win, fnwin_patch1)
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PATCH_INSN(fnwin_patch2_7win, fnwin_patch2)
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1:
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/* Finally, turn on traps so that we can call c-code. */
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rd %psr, %g3
|
|
wr %g3, 0x0, %psr
|
|
WRITE_PAUSE
|
|
|
|
wr %g3, PSR_ET, %psr
|
|
WRITE_PAUSE
|
|
|
|
/* Set up a default context */
|
|
set __context, %g1
|
|
ld [%g1], %g1
|
|
|
|
SAVE_CPU_GENERAL_STATE(entry)
|
|
SAVE_CPU_WINDOW_STATE(entry)
|
|
|
|
/* Set up local stack pointer */
|
|
set _estack - 0x40, %sp
|
|
|
|
/* And for the main context */
|
|
add %sp, -0x260, %g2
|
|
st %g2, [%g1 + 0x48]
|
|
|
|
call __switch_context
|
|
nop
|
|
|
|
/* We get here when the main context switches back to
|
|
* the boot context.
|
|
* Return to previous bootloader.
|
|
*/
|
|
ret
|
|
nop
|
|
|
|
ss2_ss1000_halt:
|
|
set SER_ADDR2, %o0
|
|
set SER_ADDR1000, %o1
|
|
mov 0x05, %o3 /* Reg 5, TXCTRL2 */
|
|
stba %o3, [%o0] ASI_M_BYPASS
|
|
stba %o3, [%o1] ASI_M_CTL
|
|
mov 0x68, %o3 /* 8 bits, Tx enabled */
|
|
stba %o3, [%o0] ASI_M_BYPASS
|
|
stba %o3, [%o1] ASI_M_CTL
|
|
add %o0, 2, %o0
|
|
add %o1, 2, %o1
|
|
|
|
1: lduba [%o2] ASI_M_KERNELTXT, %o3
|
|
cmp %o3, 0
|
|
be 2f
|
|
nop
|
|
stba %o3, [%o0] ASI_M_BYPASS
|
|
stba %o3, [%o1] ASI_M_CTL
|
|
b 1b
|
|
inc %o2
|
|
bad_conf:
|
|
2: b 2b
|
|
nop
|
|
|
|
.section .rodata
|
|
ss2_error:
|
|
.string "Sun4c machines are not supported by OpenBIOS yet, freezing\r\n"
|
|
ss1000_error:
|
|
.string "Sun4d machines are not supported by OpenBIOS yet, freezing\r\n"
|