485 lines
12 KiB
C
485 lines
12 KiB
C
// Standard VGA driver code
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//
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// Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
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// Copyright (C) 2001-2008 the LGPL VGABios developers Team
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//
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// This file may be distributed under the terms of the GNU LGPLv3 license.
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#include "biosvar.h" // GET_GLOBAL
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#include "farptr.h" // SET_FARVAR
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#include "stdvga.h" // stdvga_setup
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#include "string.h" // memset_far
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#include "vgabios.h" // struct vgamode_s
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#include "vgautil.h" // stdvga_attr_write
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#include "x86.h" // outb
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/****************************************************************
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* Attribute control
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****************************************************************/
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void
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stdvga_set_border_color(u8 color)
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{
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u8 v1 = color & 0x0f;
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if (v1 & 0x08)
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v1 += 0x08;
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stdvga_attr_write(0x00, v1);
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int i;
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for (i = 1; i < 4; i++)
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stdvga_attr_mask(i, 0x10, color & 0x10);
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}
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void
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stdvga_set_overscan_border_color(u8 color)
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{
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stdvga_attr_write(0x11, color);
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}
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u8
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stdvga_get_overscan_border_color(void)
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{
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return stdvga_attr_read(0x11);
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}
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void
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stdvga_set_palette(u8 palid)
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{
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int i;
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for (i = 1; i < 4; i++)
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stdvga_attr_mask(i, 0x01, palid & 0x01);
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}
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void
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stdvga_set_all_palette_reg(u16 seg, u8 *data_far)
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{
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int i;
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for (i = 0; i < 0x10; i++) {
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stdvga_attr_write(i, GET_FARVAR(seg, *data_far));
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data_far++;
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}
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stdvga_attr_write(0x11, GET_FARVAR(seg, *data_far));
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}
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void
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stdvga_get_all_palette_reg(u16 seg, u8 *data_far)
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{
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int i;
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for (i = 0; i < 0x10; i++) {
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SET_FARVAR(seg, *data_far, stdvga_attr_read(i));
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data_far++;
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}
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SET_FARVAR(seg, *data_far, stdvga_attr_read(0x11));
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}
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void
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stdvga_toggle_intensity(u8 flag)
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{
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stdvga_attr_mask(0x10, 0x08, (flag & 0x01) << 3);
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}
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void
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stdvga_select_video_dac_color_page(u8 flag, u8 data)
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{
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if (!(flag & 0x01)) {
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// select paging mode
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stdvga_attr_mask(0x10, 0x80, data << 7);
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return;
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}
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// select page
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u8 val = stdvga_attr_read(0x10);
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if (!(val & 0x80))
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data <<= 2;
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data &= 0x0f;
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stdvga_attr_write(0x14, data);
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}
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void
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stdvga_read_video_dac_state(u8 *pmode, u8 *curpage)
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{
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u8 val1 = stdvga_attr_read(0x10) >> 7;
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u8 val2 = stdvga_attr_read(0x14) & 0x0f;
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if (!(val1 & 0x01))
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val2 >>= 2;
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*pmode = val1;
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*curpage = val2;
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}
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/****************************************************************
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* DAC control
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****************************************************************/
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void
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stdvga_perform_gray_scale_summing(u16 start, u16 count)
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{
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stdvga_attrindex_write(0x00);
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int i;
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for (i = start; i < start+count; i++) {
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u8 rgb[3];
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stdvga_dac_read(GET_SEG(SS), rgb, i, 1);
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// intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
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u16 intensity = ((77 * rgb[0] + 151 * rgb[1] + 28 * rgb[2]) + 0x80) >> 8;
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if (intensity > 0x3f)
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intensity = 0x3f;
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rgb[0] = rgb[1] = rgb[2] = intensity;
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stdvga_dac_write(GET_SEG(SS), rgb, i, 1);
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}
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stdvga_attrindex_write(0x20);
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}
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/****************************************************************
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* Memory control
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****************************************************************/
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void
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stdvga_set_text_block_specifier(u8 spec)
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{
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stdvga_sequ_write(0x03, spec);
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}
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// Enable reads and writes to the given "plane" when in planar4 mode.
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void
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stdvga_planar4_plane(int plane)
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{
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if (plane < 0) {
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// Return to default mode (read plane0, write all planes)
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stdvga_sequ_write(0x02, 0x0f);
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stdvga_grdc_write(0x04, 0);
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} else {
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stdvga_sequ_write(0x02, 1<<plane);
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stdvga_grdc_write(0x04, plane);
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}
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}
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/****************************************************************
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* Font loading
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****************************************************************/
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static void
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get_font_access(void)
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{
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stdvga_sequ_write(0x00, 0x01);
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stdvga_sequ_write(0x02, 0x04);
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stdvga_sequ_write(0x04, 0x07);
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stdvga_sequ_write(0x00, 0x03);
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stdvga_grdc_write(0x04, 0x02);
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stdvga_grdc_write(0x05, 0x00);
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stdvga_grdc_write(0x06, 0x04);
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}
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static void
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release_font_access(void)
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{
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stdvga_sequ_write(0x00, 0x01);
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stdvga_sequ_write(0x02, 0x03);
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stdvga_sequ_write(0x04, 0x03);
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stdvga_sequ_write(0x00, 0x03);
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u16 v = (stdvga_misc_read() & 0x01) ? 0x0e : 0x0a;
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stdvga_grdc_write(0x06, v);
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stdvga_grdc_write(0x04, 0x00);
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stdvga_grdc_write(0x05, 0x10);
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}
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void
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stdvga_load_font(u16 seg, void *src_far, u16 count
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, u16 start, u8 destflags, u8 fontsize)
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{
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get_font_access();
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u16 blockaddr = ((destflags & 0x03) << 14) + ((destflags & 0x04) << 11);
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void *dest_far = (void*)(blockaddr + start*32);
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u16 i;
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for (i = 0; i < count; i++)
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memcpy_far(SEG_GRAPH, dest_far + i*32
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, seg, src_far + i*fontsize, fontsize);
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release_font_access();
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}
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/****************************************************************
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* CRTC registers
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****************************************************************/
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u16
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stdvga_get_crtc(void)
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{
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if (stdvga_misc_read() & 1)
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return VGAREG_VGA_CRTC_ADDRESS;
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return VGAREG_MDA_CRTC_ADDRESS;
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}
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// Ratio between system visible framebuffer ram and the actual videoram used.
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int
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stdvga_vram_ratio(struct vgamode_s *vmode_g)
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{
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switch (GET_GLOBAL(vmode_g->memmodel)) {
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case MM_TEXT:
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return 2;
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case MM_CGA:
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return 4 / GET_GLOBAL(vmode_g->depth);
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case MM_PLANAR:
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return 4;
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default:
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return 1;
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}
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}
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void
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stdvga_set_cursor_shape(u16 cursor_type)
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{
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u16 crtc_addr = stdvga_get_crtc();
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stdvga_crtc_write(crtc_addr, 0x0a, cursor_type >> 8);
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stdvga_crtc_write(crtc_addr, 0x0b, cursor_type);
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}
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void
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stdvga_set_cursor_pos(int address)
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{
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u16 crtc_addr = stdvga_get_crtc();
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address /= 2; // Assume we're in text mode.
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stdvga_crtc_write(crtc_addr, 0x0e, address >> 8);
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stdvga_crtc_write(crtc_addr, 0x0f, address);
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}
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void
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stdvga_set_scan_lines(u8 lines)
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{
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stdvga_crtc_mask(stdvga_get_crtc(), 0x09, 0x1f, lines - 1);
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}
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// Get vertical display end
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u16
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stdvga_get_vde(void)
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{
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u16 crtc_addr = stdvga_get_crtc();
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u16 vde = stdvga_crtc_read(crtc_addr, 0x12);
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u8 ovl = stdvga_crtc_read(crtc_addr, 0x07);
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vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
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return vde;
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}
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int
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stdvga_get_window(struct vgamode_s *vmode_g, int window)
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{
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return -1;
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}
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int
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stdvga_set_window(struct vgamode_s *vmode_g, int window, int val)
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{
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return -1;
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}
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int
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stdvga_get_linelength(struct vgamode_s *vmode_g)
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{
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u8 val = stdvga_crtc_read(stdvga_get_crtc(), 0x13);
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return val * 8 / stdvga_vram_ratio(vmode_g);
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}
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int
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stdvga_set_linelength(struct vgamode_s *vmode_g, int val)
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{
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val = DIV_ROUND_UP(val * stdvga_vram_ratio(vmode_g), 8);
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stdvga_crtc_write(stdvga_get_crtc(), 0x13, val);
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return 0;
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}
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int
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stdvga_get_displaystart(struct vgamode_s *vmode_g)
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{
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u16 crtc_addr = stdvga_get_crtc();
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int addr = (stdvga_crtc_read(crtc_addr, 0x0c) << 8
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| stdvga_crtc_read(crtc_addr, 0x0d));
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return addr * 4 / stdvga_vram_ratio(vmode_g);
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}
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int
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stdvga_set_displaystart(struct vgamode_s *vmode_g, int val)
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{
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u16 crtc_addr = stdvga_get_crtc();
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val = val * stdvga_vram_ratio(vmode_g) / 4;
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stdvga_crtc_write(crtc_addr, 0x0c, val >> 8);
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stdvga_crtc_write(crtc_addr, 0x0d, val);
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return 0;
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}
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int
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stdvga_get_dacformat(struct vgamode_s *vmode_g)
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{
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return -1;
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}
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int
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stdvga_set_dacformat(struct vgamode_s *vmode_g, int val)
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{
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return -1;
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}
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int
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stdvga_get_linesize(struct vgamode_s *vmode_g)
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{
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return DIV_ROUND_UP(GET_GLOBAL(vmode_g->width) * vga_bpp(vmode_g), 8);
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}
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/****************************************************************
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* Save/Restore state
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****************************************************************/
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struct saveVideoHardware {
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u8 sequ_index;
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u8 crtc_index;
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u8 grdc_index;
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u8 actl_index;
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u8 feature;
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u8 sequ_regs[4];
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u8 sequ0;
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u8 crtc_regs[25];
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u8 actl_regs[20];
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u8 grdc_regs[9];
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u16 crtc_addr;
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u8 plane_latch[4];
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} PACKED;
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static void
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stdvga_save_hw_state(u16 seg, struct saveVideoHardware *info)
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{
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u16 crtc_addr = stdvga_get_crtc();
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SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
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SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
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SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
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SET_FARVAR(seg, info->actl_index, stdvga_attrindex_read());
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SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
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int i;
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for (i=0; i<4; i++)
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SET_FARVAR(seg, info->sequ_regs[i], stdvga_sequ_read(i+1));
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SET_FARVAR(seg, info->sequ0, stdvga_sequ_read(0));
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for (i=0; i<25; i++)
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SET_FARVAR(seg, info->crtc_regs[i], stdvga_crtc_read(crtc_addr, i));
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for (i=0; i<20; i++)
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SET_FARVAR(seg, info->actl_regs[i], stdvga_attr_read(i));
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for (i=0; i<9; i++)
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SET_FARVAR(seg, info->grdc_regs[i], stdvga_grdc_read(i));
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SET_FARVAR(seg, info->crtc_addr, crtc_addr);
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/* XXX: read plane latches */
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for (i=0; i<4; i++)
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SET_FARVAR(seg, info->plane_latch[i], 0);
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}
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static void
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stdvga_restore_hw_state(u16 seg, struct saveVideoHardware *info)
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{
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int i;
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for (i=0; i<4; i++)
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stdvga_sequ_write(i+1, GET_FARVAR(seg, info->sequ_regs[i]));
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stdvga_sequ_write(0x00, GET_FARVAR(seg, info->sequ0));
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// Disable CRTC write protection
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u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr);
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stdvga_crtc_write(crtc_addr, 0x11, 0x00);
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// Set CRTC regs
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for (i=0; i<25; i++)
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if (i != 0x11)
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stdvga_crtc_write(crtc_addr, i, GET_FARVAR(seg, info->crtc_regs[i]));
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// select crtc base address
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stdvga_misc_mask(0x01, crtc_addr == VGAREG_VGA_CRTC_ADDRESS ? 0x01 : 0x00);
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// enable write protection if needed
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stdvga_crtc_write(crtc_addr, 0x11, GET_FARVAR(seg, info->crtc_regs[0x11]));
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// Set Attribute Ctl
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for (i=0; i<20; i++)
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stdvga_attr_write(i, GET_FARVAR(seg, info->actl_regs[i]));
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stdvga_attrindex_write(GET_FARVAR(seg, info->actl_index));
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for (i=0; i<9; i++)
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stdvga_grdc_write(i, GET_FARVAR(seg, info->grdc_regs[i]));
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outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS);
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outb(GET_FARVAR(seg, info->crtc_index), crtc_addr);
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outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
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outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
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}
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struct saveDACcolors {
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u8 rwmode;
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u8 peladdr;
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u8 pelmask;
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u8 dac[768];
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u8 color_select;
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} PACKED;
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static void
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stdvga_save_dac_state(u16 seg, struct saveDACcolors *info)
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{
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/* XXX: check this */
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SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE));
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SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS));
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SET_FARVAR(seg, info->pelmask, stdvga_pelmask_read());
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stdvga_dac_read(seg, info->dac, 0, 256);
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SET_FARVAR(seg, info->color_select, 0);
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}
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static void
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stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info)
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{
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stdvga_pelmask_write(GET_FARVAR(seg, info->pelmask));
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stdvga_dac_write(seg, info->dac, 0, 256);
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outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS);
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}
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int
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stdvga_save_restore(int cmd, u16 seg, void *data)
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{
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void *pos = data;
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if (cmd & SR_HARDWARE) {
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if (cmd & SR_SAVE)
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stdvga_save_hw_state(seg, pos);
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if (cmd & SR_RESTORE)
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stdvga_restore_hw_state(seg, pos);
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pos += sizeof(struct saveVideoHardware);
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}
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pos += bda_save_restore(cmd, seg, pos);
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if (cmd & SR_DAC) {
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if (cmd & SR_SAVE)
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stdvga_save_dac_state(seg, pos);
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if (cmd & SR_RESTORE)
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stdvga_restore_dac_state(seg, pos);
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pos += sizeof(struct saveDACcolors);
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}
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return pos - data;
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}
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/****************************************************************
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* Misc
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****************************************************************/
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void
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stdvga_enable_video_addressing(u8 disable)
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{
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u8 v = (disable & 1) ? 0x00 : 0x02;
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stdvga_misc_mask(0x02, v);
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}
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int
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stdvga_setup(void)
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{
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// switch to color mode and enable CPU access 480 lines
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stdvga_misc_write(0xc3);
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// more than 64k 3C4/04
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stdvga_sequ_write(0x04, 0x02);
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return 0;
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}
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