76 lines
3.6 KiB
ReStructuredText
76 lines
3.6 KiB
ReStructuredText
.. _skiboot-5.4.4:
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=============
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skiboot-5.4.4
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=============
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skiboot-5.4.4 was released on Wednesday May 3rd, 2017. It replaces
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:ref:`skiboot-5.4.3` as the current stable release in the 5.4.x series.
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Over :ref:`skiboot-5.4.3`, we have a small number of bug fixes:
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- hw/fsp: Do not queue SP and SPCN class messages during reset/reload
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In certain cases of communicating with the FSP (e.g. sensors), the OPAL FSP
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driver returns a default code (async
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completion) even though there is no known bound from the time of this error
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return to the actual data being available. The kernel driver keeps waiting
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leading to soft-lockup on the host side.
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Mitigate both these (known) cases by returning OPAL_BUSY so the host driver
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knows to retry later.
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- core/pci: Fix PCIe slot's presence
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According to PCIe spec, the presence bit is hardcoded to 1 if PCIe
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switch downstream port doesn't support slot capability. The register
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used for the check in pcie_slot_get_presence_state() is wrong. It
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should be PCIe capability register instead of PCIe slot capability
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register. Otherwise, we always have present bit on the PCI topology.
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The issue is found on Supermicro's p8dtu2u machine: ::
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# lspci -t
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-+-[0022:00]---00.0-[01-08]----00.0-[02-08]--+-01.0-[03]----00.0
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| \-02.0-[04-08]--
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# cat /sys/bus/pci/slots/S002204/adapter
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1
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# lspci -vvs 0022:02:02.0
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# lspci -vvs 0022:02:02.0
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0022:02:02.0 PCI bridge: PLX Technology, Inc. PEX 8718 16-Lane, \
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5-Port PCI Express Gen 3 (8.0 GT/s) Switch (rev ab) (prog-if 00 [Normal decode])
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:
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Capabilities: [68] Express (v2) Downstream Port (Slot+), MSI 00
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:
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SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
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Changed: MRL- PresDet- LinkState-
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This fixes the issue by checking the correct register (PCIe capability).
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Also, the register's value is cached in advance as we did for slot and
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link capability.
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- core/pci: More reliable way to update PCI slot power state
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The power control bit (SLOT_CTL, offset: PCIe cap + 0x18) isn't
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reliable enough to reflect the PCI slot's power state. Instead,
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the power indication bits are more reliable comparatively. This
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leads to mismatch between the cached power state and PCI slot's
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presence state, resulting in the hotplug driver in kernel refuses
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to unplug the devices properly on the request. The issue was
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found on below NVMe card on "supermicro,p8dtu2u" machine. We don't
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have this issue on the integrated PLX 8718 switch. ::
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# lspci
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0022:01:00.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane, \
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9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa)
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0022:02:01.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane, \
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9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa)
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0022:02:04.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane, \
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9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa)
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0022:02:05.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane, \
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9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa)
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0022:02:06.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane, \
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9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa)
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0022:02:07.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane, \
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9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa)
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0022:17:00.0 Non-Volatile memory controller: Device 19e5:0123 (rev 45)
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This updates the cached PCI slot's power state using the power
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indication bits instead of power control bit, to fix above issue.
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- core/pci: Avoid hreset after freset
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