80 lines
2.7 KiB
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80 lines
2.7 KiB
ReStructuredText
.. _skiboot-5.9.2:
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=============
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skiboot-5.9.2
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=============
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skiboot 5.9.2 was released on Thursday November 16th, 2017. It replaces
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:ref:`skiboot-5.9.1` as the current stable release in the 5.9.x series.
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Over :ref:`skiboot-5.9.1`, we have a few PHB4 (PCI) fixes, an i2c fix for
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POWER9 platforms to avoid conflicting with the OCC use and an important
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NPU2 (NVLink2) fix.
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- phb4: Fix lane equalisation setting
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Fix cut and paste from phb3. The sizes have changes now we have GEN4,
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so the check here needs to change also
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Without this we end up with the default settings (all '7') rather
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than what's in HDAT.
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- phb4: Fix PE mapping of M32 BAR
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The M32 BAR is the PHB4 region used to map all the non-prefetchable
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or 32-bit device BARs. It's supposed to have its segments remapped
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via the MDT and Linux relies on that to assign them individual PE#.
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However, we weren't configuring that properly and instead used the
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mode where PE# == segment#, thus causing EEH to freeze the wrong
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device or PE#.
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- phb4: Fix lost bit in PE number on config accesses
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A PE number can be up to 9 bits, using a uint8_t won't fly..
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That was causing error on config accesses to freeze the
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wrong PE.
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- phb4: Update inits
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New init value from HW folks for the fence enable register.
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This clears bit 17 (CFG Write Error CA or UR response) and bit 22 (MMIO Write
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DAT_ERR Indication) and sets bit 21 (MMIO CFG Pending Error)
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- npu2: Move to new GPU memory map
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There are three different ways we configure the MCD and memory map.
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1) Old way (current way)
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Skiboot configures the MCD and puts GPUs at 4TB and below
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2) New way with MCD
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Hostboot configures the MCD and skiboot puts GPU at 4TB and above
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3) New way without MCD
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No one configures the MCD and skiboot puts GPU at 4TB and below
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The change keeps option 1 and adds options 2 and 3.
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The different configurations are detected using certain scoms (see
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patch).
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Option 1 will go away eventually as it's a configuration that can
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cause xstops or data integrity problems. We are keeping it around to
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support existing hostboot.
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Option 2 supports only 4 GPUs and 512GB of memory per socket.
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Option 3 supports 6 GPUs and 4TB of memory but may have some
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performance impact.
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- p8-i2c: Don't write the watermark register at init
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On P9 the I2C master is shared with the OCC. Currently the watermark
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values are set once at init time which is bad for two reasons:
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a) We don't take the OCC master lock before setting it. Which
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may cause issues if the OCC is currently using the master.
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b) The OCC might change the watermark levels and we need to reset
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them.
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Change this so that we set the watermark value when a new transaction
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is started rather than at init time.
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