127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
/* Copyright 2016 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <skiboot.h>
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#include <chip.h>
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#include <xscom.h>
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#include <io.h>
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#include <cpu.h>
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#include <nx.h>
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#define EE (1) /* enable gzip engine */
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static int nx_cfg_gzip_umac(struct dt_node *node, u32 gcid, u32 pb_base)
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{
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int rc;
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u64 umac_bar, umac_notify;
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struct dt_node *nx_node;
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static u32 nxgzip_tid = 1; /* tid counter within coprocessor type */
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nx_node = dt_new(node, "ibm,gzip-high-fifo");
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umac_bar = pb_base + NX_P9_GZIP_HIGH_PRI_RX_FIFO_BAR;
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umac_notify = pb_base + NX_P9_GZIP_HIGH_PRI_RX_FIFO_NOTIFY_MATCH;
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rc = nx_cfg_rx_fifo(nx_node, "ibm,p9-nx-gzip", "High", gcid,
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NX_CT_GZIP, nxgzip_tid++, umac_bar,
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umac_notify);
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if (rc)
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return rc;
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nx_node = dt_new(node, "ibm,gzip-normal-fifo");
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umac_bar = pb_base + NX_P9_GZIP_NORMAL_PRI_RX_FIFO_BAR;
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umac_notify = pb_base + NX_P9_GZIP_NORMAL_PRI_RX_FIFO_NOTIFY_MATCH;
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rc = nx_cfg_rx_fifo(nx_node, "ibm,p9-nx-gzip", "Normal", gcid,
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NX_CT_GZIP, nxgzip_tid++, umac_bar,
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umac_notify);
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return rc;
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}
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static int nx_cfg_gzip_dma(u32 gcid, u64 xcfg)
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{
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u64 cfg;
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int rc;
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rc = xscom_read(gcid, xcfg, &cfg);
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if (rc)
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return rc;
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cfg = SETFIELD(NX_DMA_CFG_GZIP_COMPRESS_PREFETCH, cfg,
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DMA_COMPRESS_PREFETCH);
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cfg = SETFIELD(NX_DMA_CFG_GZIP_DECOMPRESS_PREFETCH, cfg,
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DMA_DECOMPRESS_PREFETCH);
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cfg = SETFIELD(NX_DMA_CFG_GZIP_COMPRESS_MAX_RR, cfg,
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DMA_COMPRESS_MAX_RR);
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cfg = SETFIELD(NX_DMA_CFG_GZIP_DECOMPRESS_MAX_RR, cfg,
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DMA_DECOMPRESS_MAX_RR);
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rc = xscom_write(gcid, xcfg, cfg);
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if (rc)
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prerror("NX%d: ERROR: DMA config failure %d\n", gcid, rc);
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else
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prlog(PR_DEBUG, "NX%d: DMA 0x%016lx\n", gcid,
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(unsigned long)cfg);
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return rc;
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}
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static int nx_cfg_gzip_ee(u32 gcid, u64 xcfg)
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{
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u64 cfg;
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int rc;
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rc = xscom_read(gcid, xcfg, &cfg);
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if (rc)
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return rc;
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cfg = SETFIELD(NX_P9_EE_CFG_CH4, cfg, EE);
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rc = xscom_write(gcid, xcfg, cfg);
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if (rc)
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prerror("NX%d: ERROR: Engine Enable failure %d\n", gcid, rc);
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else
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prlog(PR_DEBUG, "NX%d: Engine Enable 0x%016lx\n",
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gcid, (unsigned long)cfg);
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return rc;
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}
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void p9_nx_enable_gzip(struct dt_node *node, u32 gcid, u32 pb_base)
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{
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u64 cfg_dma, cfg_ee;
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int rc;
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prlog(PR_INFO, "NX%d: gzip at 0x%x\n", gcid, pb_base);
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cfg_dma = pb_base + NX_P9_DMA_CFG;
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cfg_ee = pb_base + NX_P9_EE_CFG;
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rc = nx_cfg_gzip_dma(gcid, cfg_dma);
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if (rc)
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return;
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rc = nx_cfg_gzip_ee(gcid, cfg_ee);
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if (rc)
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return;
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rc = nx_cfg_gzip_umac(node, gcid, pb_base);
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if (rc)
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return;
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prlog(PR_INFO, "NX%d: gzip Coprocessor Enabled\n", gcid);
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}
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