217 lines
8.3 KiB
C
217 lines
8.3 KiB
C
/* Copyright 2017 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <phys-map.h>
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#include <chip.h>
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#include <skiboot.h>
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#include <opal-api.h>
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#include <stack.h>
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#include <inttypes.h>
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struct phys_map_entry {
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enum phys_map_type type;
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int index;
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uint64_t addr;
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uint64_t size;
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};
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struct phys_map_info {
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int chip_select_shift;
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const struct phys_map_entry *table;
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};
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static const struct phys_map_info *phys_map;
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static const struct phys_map_entry phys_map_table_nimbus[] = {
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/* System memory upto 4TB minus GPU memory */
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{ SYSTEM_MEM, 0, 0x0000000000000000ull, 0x0000034000000000ull },
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/* GPU memory from 4TB - 128GB*GPU */
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{ GPU_MEM_4T_DOWN, 5, 0x0000034000000000ull, 0x0000002000000000ull },
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{ GPU_MEM_4T_DOWN, 4, 0x0000036000000000ull, 0x0000002000000000ull },
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{ GPU_MEM_4T_DOWN, 3, 0x0000038000000000ull, 0x0000002000000000ull },
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{ GPU_MEM_4T_DOWN, 2, 0x000003a000000000ull, 0x0000002000000000ull },
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{ GPU_MEM_4T_DOWN, 1, 0x000003c000000000ull, 0x0000002000000000ull },
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{ GPU_MEM_4T_DOWN, 0, 0x000003e000000000ull, 0x0000002000000000ull },
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/* GPU memory from 4TB + 128GB*GPU. 4 GPUs only */
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{ GPU_MEM_4T_UP, 0, 0x0000040000000000ull, 0x0000002000000000ull },
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{ GPU_MEM_4T_UP, 1, 0x0000042000000000ull, 0x0000002000000000ull },
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{ GPU_MEM_4T_UP, 2, 0x0000044000000000ull, 0x0000002000000000ull },
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{ GPU_MEM_4T_UP, 3, 0x0000046000000000ull, 0x0000002000000000ull },
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/*
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* OpenCAPI LPC Memory - single 4TB range per chip, fills
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* whole second non-mirrored region.
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*
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* Longer term, we're going to use chip address extension to
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* enable >4TB to be allocated per chip. At that point, we
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* may have to find another way of assigning these ranges
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* outside of phys-map.
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*/
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{ OCAPI_MEM, 0, 0x0002000000000000ull, 0x0000040000000000ull },
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/* 0 TB offset @ MMIO 0x0006000000000000ull */
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{ PHB4_64BIT_MMIO, 0, 0x0006000000000000ull, 0x0000004000000000ull },
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{ PHB4_64BIT_MMIO, 1, 0x0006004000000000ull, 0x0000004000000000ull },
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{ PHB4_64BIT_MMIO, 2, 0x0006008000000000ull, 0x0000004000000000ull },
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{ PHB4_32BIT_MMIO, 0, 0x000600c000000000ull, 0x0000000080000000ull },
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{ PHB4_32BIT_MMIO, 1, 0x000600c080000000ull, 0x0000000080000000ull },
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{ PHB4_32BIT_MMIO, 2, 0x000600c100000000ull, 0x0000000080000000ull },
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{ PHB4_32BIT_MMIO, 3, 0x000600c180000000ull, 0x0000000080000000ull },
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{ PHB4_32BIT_MMIO, 4, 0x000600c200000000ull, 0x0000000080000000ull },
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{ PHB4_32BIT_MMIO, 5, 0x000600c280000000ull, 0x0000000080000000ull },
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{ PHB4_XIVE_ESB , 0, 0x000600c300000000ull, 0x0000000020000000ull },
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{ PHB4_XIVE_ESB , 1, 0x000600c320000000ull, 0x0000000020000000ull },
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{ PHB4_XIVE_ESB , 2, 0x000600c340000000ull, 0x0000000020000000ull },
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{ PHB4_XIVE_ESB , 3, 0x000600c360000000ull, 0x0000000020000000ull },
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{ PHB4_XIVE_ESB , 4, 0x000600c380000000ull, 0x0000000020000000ull },
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{ PHB4_XIVE_ESB , 5, 0x000600c3a0000000ull, 0x0000000020000000ull },
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{ PHB4_REG_SPC , 0, 0x000600c3c0000000ull, 0x0000000000100000ull },
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{ PHB4_REG_SPC , 1, 0x000600c3c0100000ull, 0x0000000000100000ull },
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{ PHB4_REG_SPC , 2, 0x000600c3c0200000ull, 0x0000000000100000ull },
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{ PHB4_REG_SPC , 3, 0x000600c3c0300000ull, 0x0000000000100000ull },
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{ PHB4_REG_SPC , 4, 0x000600c3c0400000ull, 0x0000000000100000ull },
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{ PHB4_REG_SPC , 5, 0x000600c3c0500000ull, 0x0000000000100000ull },
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{ RESV , 0, 0x000600c3c0600000ull, 0x0000000c3fa00000ull },
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{ NPU_OCAPI_MMIO , 0, 0x000600d000000000ull, 0x0000000800000000ull },
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{ NPU_OCAPI_MMIO , 1, 0x000600d800000000ull, 0x0000000800000000ull },
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{ NPU_OCAPI_MMIO , 2, 0x000600e000000000ull, 0x0000000800000000ull },
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{ NPU_OCAPI_MMIO , 3, 0x000600e800000000ull, 0x0000000800000000ull },
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{ NPU_OCAPI_MMIO , 4, 0x000600f000000000ull, 0x0000000800000000ull },
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{ NPU_OCAPI_MMIO , 5, 0x000600f800000000ull, 0x0000000800000000ull },
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/* 1 TB offset @ MMIO 0x0006000000000000ull */
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{ XIVE_VC , 0, 0x0006010000000000ull, 0x0000008000000000ull },
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{ XIVE_PC , 0, 0x0006018000000000ull, 0x0000001000000000ull },
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{ VAS_USER_WIN , 0, 0x0006019000000000ull, 0x0000000100000000ull },
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{ VAS_HYP_WIN , 0, 0x0006019100000000ull, 0x0000000002000000ull },
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{ RESV , 1, 0x0006019102000000ull, 0x000000001e000000ull },
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{ OCAB_XIVE_ESB , 0, 0x0006019120000000ull, 0x0000000020000000ull },
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{ RESV , 3, 0x0006019140000000ull, 0x0000006ec0000000ull },
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/* 2 TB offset @ MMIO 0x0006000000000000ull */
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{ PHB4_64BIT_MMIO, 3, 0x0006020000000000ull, 0x0000004000000000ull },
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{ PHB4_64BIT_MMIO, 4, 0x0006024000000000ull, 0x0000004000000000ull },
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{ PHB4_64BIT_MMIO, 5, 0x0006028000000000ull, 0x0000004000000000ull },
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{ RESV , 4, 0x000602c000000000ull, 0x0000004000000000ull },
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/* 3 TB offset @ MMIO 0x0006000000000000ull */
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{ LPC_BUS , 0, 0x0006030000000000ull, 0x0000000100000000ull },
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{ FSP_MMIO , 0, 0x0006030100000000ull, 0x0000000100000000ull },
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{ NPU_REGS , 0, 0x0006030200000000ull, 0x0000000001000000ull },
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{ NPU_USR , 0, 0x0006030201000000ull, 0x0000000000200000ull },
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{ NPU_PHY , 0, 0x0006030201200000ull, 0x0000000000200000ull },
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{ NPU_PHY , 1, 0x0006030201400000ull, 0x0000000000200000ull },
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{ NPU_NTL , 0, 0x0006030201600000ull, 0x0000000000020000ull },
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{ NPU_NTL , 1, 0x0006030201620000ull, 0x0000000000020000ull },
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{ NPU_NTL , 2, 0x0006030201640000ull, 0x0000000000020000ull },
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{ NPU_NTL , 3, 0x0006030201660000ull, 0x0000000000020000ull },
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{ NPU_NTL , 4, 0x0006030201680000ull, 0x0000000000020000ull },
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{ NPU_NTL , 5, 0x00060302016a0000ull, 0x0000000000020000ull },
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{ NPU_GENID , 0, 0x00060302016c0000ull, 0x0000000000020000ull },
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{ NPU_GENID , 1, 0x00060302016e0000ull, 0x0000000000020000ull },
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{ NPU_GENID , 2, 0x0006030201700000ull, 0x0000000000020000ull },
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{ RESV , 5, 0x0006030201720000ull, 0x00000000018e0000ull },
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{ PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull },
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{ XIVE_IC , 0, 0x0006030203100000ull, 0x0000000000080000ull },
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{ XIVE_TM , 0, 0x0006030203180000ull, 0x0000000000040000ull },
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{ PSIHB_ESB , 0, 0x00060302031c0000ull, 0x0000000000010000ull },
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{ NX_RNG , 0, 0x00060302031d0000ull, 0x0000000000010000ull },
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{ RESV , 6, 0x00060302031e0000ull, 0x000000001ce20000ull },
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{ CENTAUR_SCOM , 0, 0x0006030220000000ull, 0x0000000020000000ull },
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{ RESV , 7, 0x0006030240000000ull, 0x000000f9c0000000ull },
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{ XSCOM , 0, 0x000603fc00000000ull, 0x0000000400000000ull },
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/* NULL entry at end */
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{ NULL_MAP, 0, 0, 0 },
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};
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static const struct phys_map_info phys_map_nimbus = {
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.chip_select_shift = 42,
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.table = phys_map_table_nimbus,
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};
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static inline bool phys_map_entry_null(const struct phys_map_entry *e)
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{
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if (e->type == NULL_MAP)
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return true;
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return false;
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}
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/* This crashes skiboot on error as any bad calls here are almost
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* certainly a developer error
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*/
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void phys_map_get(uint64_t gcid, enum phys_map_type type,
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int index, uint64_t *addr, uint64_t *size) {
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const struct phys_map_entry *e;
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uint64_t a;
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if (!phys_map)
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goto error;
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/* Find entry in table */
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for (e = phys_map->table; ; e++) {
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/* End of table */
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if (phys_map_entry_null(e))
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goto error;
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/* Is this our entry? */
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if (e->type != type)
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continue;
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if (e->index != index)
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continue;
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/* Found entry! */
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break;
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}
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a = e->addr;
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a += gcid << phys_map->chip_select_shift;
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if (addr)
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*addr = a;
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if (size)
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*size = e->size;
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prlog(PR_TRACE, "Assigning BAR [%"PRIx64"] type:%02i index:%x "
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"0x%016"PRIx64" for 0x%016"PRIx64"\n",
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gcid, type, index, a, e->size);
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return;
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error:
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/* Something has gone really wrong */
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prlog(PR_EMERG, "ERROR: Failed to lookup BAR type:%i index:%i\n",
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type, index);
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assert(0);
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}
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void phys_map_init(void)
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{
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const char *name = "unused";
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phys_map = NULL;
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if (proc_gen == proc_gen_p9) {
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name = "nimbus";
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phys_map = &phys_map_nimbus;
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}
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prlog(PR_DEBUG, "Assigning physical memory map table for %s\n", name);
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}
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