310 lines
7.1 KiB
C
310 lines
7.1 KiB
C
/* Copyright 2013-2016 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <skiboot.h>
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#include <device.h>
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#include <console.h>
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#include <chip.h>
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#include <ipmi.h>
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#include <psi.h>
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#include <npu-regs.h>
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#include "astbmc.h"
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static const struct slot_table_entry garrison_phb0_0_slot[] = {
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{
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.etype = st_pluggable_slot,
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.location = ST_LOC_DEVFN(0,0),
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.name = "Slot3",
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},
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{ .etype = st_end },
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};
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static const struct slot_table_entry garrison_phb0_1_slot[] = {
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{
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.etype = st_pluggable_slot,
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.location = ST_LOC_DEVFN(0,0),
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.name = "Slot2",
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},
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{ .etype = st_end },
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};
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static const struct slot_table_entry garrison_phb0_2_slot[] = {
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{
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.etype = st_pluggable_slot,
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.location = ST_LOC_DEVFN(0,0),
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.name = "GPU1",
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},
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{ .etype = st_end },
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};
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static const struct slot_table_entry garrison_phb0_3_slot[] = {
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{
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.etype = st_pluggable_slot,
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.location = ST_LOC_DEVFN(0,0),
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.name = "GPU2",
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},
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{ .etype = st_end },
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};
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static const struct slot_table_entry garrison_npu0_slots[] = {
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{
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.etype = st_npu_slot,
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.location = ST_LOC_NPU_GROUP(0),
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.name = "GPU2",
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},
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{
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.etype = st_npu_slot,
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.location = ST_LOC_NPU_GROUP(1),
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.name = "GPU1",
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},
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{ .etype = st_end },
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};
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static const struct slot_table_entry garrison_phb1_0_slot[] = {
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{
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.etype = st_pluggable_slot,
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.location = ST_LOC_DEVFN(0,0),
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.name = "Slot1",
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},
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{ .etype = st_end },
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};
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static const struct slot_table_entry garrison_plx_slots[] = {
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{
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.etype = st_builtin_dev,
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.location = ST_LOC_DEVFN(1,0),
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.name = "Backplane USB",
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},
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{
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.etype = st_builtin_dev,
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.location = ST_LOC_DEVFN(2,0),
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.name = "Backplane SATA",
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},
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{
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.etype = st_builtin_dev,
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.location = ST_LOC_DEVFN(3,0),
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.name = "Backplane BMC",
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},
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{ .etype = st_end },
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};
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static const struct slot_table_entry garrison_plx_up[] = {
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{
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.etype = st_builtin_dev,
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.location = ST_LOC_DEVFN(0,0),
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.children = garrison_plx_slots,
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},
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{ .etype = st_end },
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};
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static const struct slot_table_entry garrison_phb1_1_slot[] = {
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{
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.etype = st_builtin_dev,
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.location = ST_LOC_DEVFN(0,0),
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.name = "Backplane PLX",
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.children = garrison_plx_up,
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},
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{ .etype = st_end },
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};
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static const struct slot_table_entry garrison_phb1_2_slot[] = {
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{
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.etype = st_pluggable_slot,
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.location = ST_LOC_DEVFN(0,0),
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.name = "GPU3",
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},
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{ .etype = st_end },
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};
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static const struct slot_table_entry garrison_phb1_3_slot[] = {
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{
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.etype = st_pluggable_slot,
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.location = ST_LOC_DEVFN(0,0),
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.name = "GPU4",
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},
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{ .etype = st_end },
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};
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static const struct slot_table_entry garrison_npu1_slots[] = {
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{
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.etype = st_npu_slot,
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.location = ST_LOC_NPU_GROUP(0),
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.name = "GPU4",
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},
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{
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.etype = st_npu_slot,
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.location = ST_LOC_NPU_GROUP(1),
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.name = "GPU3",
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},
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{ .etype = st_end },
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};
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static const struct slot_table_entry garrison_phb_table[] = {
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{
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.etype = st_phb,
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.location = ST_LOC_PHB(0,0),
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.children = garrison_phb0_0_slot,
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},
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{
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.etype = st_phb,
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.location = ST_LOC_PHB(0,1),
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.children = garrison_phb0_1_slot,
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},
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{
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.etype = st_phb,
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.location = ST_LOC_PHB(0,2),
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.children = garrison_phb0_2_slot,
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},
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{
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.etype = st_phb,
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.location = ST_LOC_PHB(0,3),
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.children = garrison_phb0_3_slot,
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},
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{
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.etype = st_phb,
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.location = ST_LOC_PHB(0,4),
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.children = garrison_npu0_slots,
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},
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{
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.etype = st_phb,
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.location = ST_LOC_PHB(1,0),
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.children = garrison_phb1_0_slot,
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},
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{
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.etype = st_phb,
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.location = ST_LOC_PHB(1,1),
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.children = garrison_phb1_1_slot,
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},
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{
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.etype = st_phb,
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.location = ST_LOC_PHB(1,2),
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.children = garrison_phb1_2_slot,
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},
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{
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.etype = st_phb,
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.location = ST_LOC_PHB(1,3),
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.children = garrison_phb1_3_slot,
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},
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{
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.etype = st_phb,
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.location = ST_LOC_PHB(1,4),
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.children = garrison_npu1_slots,
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},
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{ .etype = st_end },
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};
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#define NPU_BASE 0x8013c00
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#define NPU_SIZE 0x2c
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#define NPU_INDIRECT0 0x8000000008010c3fUL
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#define NPU_INDIRECT1 0x8000000008010c7fUL
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static void create_link(struct dt_node *npu, int group, int index)
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{
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struct dt_node *link;
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uint32_t lane_mask;
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uint64_t phy;
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char namebuf[32];
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snprintf(namebuf, sizeof(namebuf), "link@%x", index);
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link = dt_new(npu, namebuf);
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dt_add_property_string(link, "compatible", "ibm,npu-link");
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dt_add_property_cells(link, "ibm,npu-link-index", index);
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if (index < 4) {
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phy = NPU_INDIRECT0;
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lane_mask = 0xff << (index * 8);
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} else {
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phy = NPU_INDIRECT1;
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lane_mask = 0xff0000 >> (index - 3) * 8;
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}
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dt_add_property_u64s(link, "ibm,npu-phy", phy);
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dt_add_property_cells(link, "ibm,npu-lane-mask", lane_mask);
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dt_add_property_cells(link, "ibm,npu-group-id", group);
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}
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static void dt_create_npu(void)
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{
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struct dt_node *xscom, *npu;
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char namebuf[32];
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dt_for_each_compatible(dt_root, xscom, "ibm,xscom") {
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snprintf(namebuf, sizeof(namebuf), "npu@%x", NPU_BASE);
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npu = dt_new(xscom, namebuf);
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dt_add_property_cells(npu, "reg", NPU_BASE, NPU_SIZE);
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dt_add_property_strings(npu, "compatible", "ibm,power8-npu");
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/* Use the first available PHB index which is 4 given
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* there are three normal PHBs. */
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dt_add_property_cells(npu, "ibm,phb-index", 4);
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dt_add_property_cells(npu, "ibm,npu-index", 0);
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dt_add_property_cells(npu, "ibm,npu-links", 4);
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/* On Garrison we have 2 links per GPU device. These are
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* grouped together as per the slot tables above. */
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create_link(npu, 0, 0);
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create_link(npu, 0, 1);
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create_link(npu, 1, 4);
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create_link(npu, 1, 5);
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}
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}
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static bool garrison_probe(void)
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{
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if (!dt_node_is_compatible(dt_root, "ibm,garrison"))
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return false;
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/* Lot of common early inits here */
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astbmc_early_init();
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/*
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* Override external interrupt policy -> send to Linux
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*
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* On Naples, we get LPC interrupts via the built-in LPC
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* controller demuxer, not an external CPLD. The external
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* interrupt is for other uses, such as the TPM chip, we
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* currently route it to Linux, but we might change that
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* later if we decide we need it.
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*/
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psi_set_external_irq_policy(EXTERNAL_IRQ_POLICY_LINUX);
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/* Fixups until HB get the NPU bindings */
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dt_create_npu();
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slot_table_init(garrison_phb_table);
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return true;
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}
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DECLARE_PLATFORM(garrison) = {
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.name = "Garrison",
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.bmc = &bmc_plat_ast2400_ami,
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.probe = garrison_probe,
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.init = astbmc_init,
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.pci_get_slot_info = slot_table_get_slot_info,
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.pci_probe_complete = check_all_slot_table,
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.cec_power_down = astbmc_ipmi_power_down,
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.cec_reboot = astbmc_ipmi_reboot,
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.elog_commit = ipmi_elog_commit,
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.start_preload_resource = flash_start_preload_resource,
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.resource_loaded = flash_resource_loaded,
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.exit = ipmi_wdt_final_reset,
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.terminate = ipmi_terminate,
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.seeprom_update = astbmc_seeprom_update,
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.op_display = op_display_lpc,
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};
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