historical/m0-applesillicon.git/xnu-qemu-arm64-5.1.0/roms/u-boot/drivers/clk/exynos/clk-pll.h
2024-01-16 11:20:27 -06:00

8 lines
258 B
C

/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Exynos PLL helper functions for clock drivers.
* Copyright (C) 2016 Samsung Electronics
* Thomas Abraham <thomas.ab@samsung.com>
*/
unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);