595 lines
18 KiB
C
595 lines
18 KiB
C
/*
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* ARM implementation of KVM hooks, 32 bit specific code.
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*
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* Copyright Christoffer Dall 2009-2010
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include <sys/ioctl.h>
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#include <linux/kvm.h>
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#include "qemu-common.h"
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#include "cpu.h"
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#include "qemu/timer.h"
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#include "sysemu/runstate.h"
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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#include "internals.h"
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#include "qemu/log.h"
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static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
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{
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struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
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assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32);
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return ioctl(fd, KVM_GET_ONE_REG, &idreg);
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}
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bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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{
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/* Identify the feature bits corresponding to the host CPU, and
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* fill out the ARMHostCPUClass fields accordingly. To do this
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* we have to create a scratch VM, create a single CPU inside it,
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* and then query that CPU for the relevant ID registers.
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*/
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int err = 0, fdarray[3];
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uint32_t midr, id_pfr0;
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uint64_t features = 0;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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* we know these will only support creating one kind of guest CPU,
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* which is its preferred CPU type.
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*/
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static const uint32_t cpus_to_try[] = {
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QEMU_KVM_ARM_TARGET_CORTEX_A15,
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QEMU_KVM_ARM_TARGET_NONE
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};
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/*
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* target = -1 informs kvm_arm_create_scratch_host_vcpu()
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* to use the preferred target
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*/
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struct kvm_vcpu_init init = { .target = -1, };
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if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
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return false;
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}
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ahcf->target = init.target;
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/* This is not strictly blessed by the device tree binding docs yet,
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* but in practice the kernel does not care about this string so
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* there is no point maintaining an KVM_ARM_TARGET_* -> string table.
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*/
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ahcf->dtb_compatible = "arm,arm-v7";
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err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
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err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
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ARM_CP15_REG32(0, 0, 2, 0));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
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ARM_CP15_REG32(0, 0, 2, 1));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
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ARM_CP15_REG32(0, 0, 2, 2));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
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ARM_CP15_REG32(0, 0, 2, 3));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
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ARM_CP15_REG32(0, 0, 2, 4));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
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ARM_CP15_REG32(0, 0, 2, 5));
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if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
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ARM_CP15_REG32(0, 0, 2, 7))) {
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/*
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* Older kernels don't support reading ID_ISAR6. This register was
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* only introduced in ARMv8, so we can assume that it is zero on a
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* CPU that a kernel this old is running on.
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*/
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ahcf->isar.id_isar6 = 0;
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}
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
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ARM_CP15_REG32(0, 0, 1, 2));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
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KVM_REG_ARM | KVM_REG_SIZE_U32 |
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KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
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KVM_REG_ARM | KVM_REG_SIZE_U32 |
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KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
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/*
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* FIXME: There is not yet a way to read MVFR2.
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* Fortunately there is not yet anything in there that affects migration.
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*/
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
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ARM_CP15_REG32(0, 0, 1, 4));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
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ARM_CP15_REG32(0, 0, 1, 5));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
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ARM_CP15_REG32(0, 0, 1, 6));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
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ARM_CP15_REG32(0, 0, 1, 7));
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if (read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
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ARM_CP15_REG32(0, 0, 2, 6))) {
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/*
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* Older kernels don't support reading ID_MMFR4 (a new in v8
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* register); assume it's zero.
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*/
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ahcf->isar.id_mmfr4 = 0;
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}
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/*
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* There is no way to read DBGDIDR, because currently 32-bit KVM
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* doesn't implement debug at all. Leave it at zero.
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*/
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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if (err < 0) {
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return false;
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}
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/* Now we've retrieved all the register information we can
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* set the feature bits based on the ID register fields.
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* We can assume any KVM supporting CPU is at least a v7
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* with VFPv3, virtualization extensions, and the generic
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* timers; this in turn implies most of the other feature
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* bits, but a few must be tested.
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*/
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features |= 1ULL << ARM_FEATURE_V7VE;
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features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
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if (extract32(id_pfr0, 12, 4) == 1) {
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features |= 1ULL << ARM_FEATURE_THUMB2EE;
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}
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if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
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features |= 1ULL << ARM_FEATURE_NEON;
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}
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ahcf->features = features;
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return true;
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}
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bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
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{
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/* Return true if the regidx is a register we should synchronize
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* via the cpreg_tuples array (ie is not a core reg we sync by
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* hand in kvm_arch_get/put_registers())
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*/
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switch (regidx & KVM_REG_ARM_COPROC_MASK) {
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case KVM_REG_ARM_CORE:
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case KVM_REG_ARM_VFP:
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return false;
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default:
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return true;
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}
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}
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typedef struct CPRegStateLevel {
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uint64_t regidx;
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int level;
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} CPRegStateLevel;
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/* All coprocessor registers not listed in the following table are assumed to
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* be of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
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* often, you must add it to this table with a state of either
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* KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
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*/
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static const CPRegStateLevel non_runtime_cpregs[] = {
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{ KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE },
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};
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int kvm_arm_cpreg_level(uint64_t regidx)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) {
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const CPRegStateLevel *l = &non_runtime_cpregs[i];
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if (l->regidx == regidx) {
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return l->level;
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}
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}
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return KVM_PUT_RUNTIME_STATE;
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}
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#define ARM_CPU_ID_MPIDR 0, 0, 0, 5
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int kvm_arch_init_vcpu(CPUState *cs)
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{
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int ret;
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uint64_t v;
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uint32_t mpidr;
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struct kvm_one_reg r;
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ARMCPU *cpu = ARM_CPU(cs);
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if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
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fprintf(stderr, "KVM is not supported for this guest CPU type\n");
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return -EINVAL;
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}
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qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs);
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/* Determine init features for this CPU */
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memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
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if (cpu->start_powered_off) {
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cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
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}
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if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
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cpu->psci_version = 2;
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cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
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}
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/* Do KVM_ARM_VCPU_INIT ioctl */
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ret = kvm_arm_vcpu_init(cs);
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if (ret) {
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return ret;
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}
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/* Query the kernel to make sure it supports 32 VFP
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* registers: QEMU's "cortex-a15" CPU is always a
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* VFP-D32 core. The simplest way to do this is just
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* to attempt to read register d31.
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*/
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
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r.addr = (uintptr_t)(&v);
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
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if (ret == -ENOENT) {
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return -EINVAL;
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}
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/*
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* When KVM is in use, PSCI is emulated in-kernel and not by qemu.
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* Currently KVM has its own idea about MPIDR assignment, so we
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* override our defaults with what we get from KVM.
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*/
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ret = kvm_get_one_reg(cs, ARM_CP15_REG32(ARM_CPU_ID_MPIDR), &mpidr);
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if (ret) {
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return ret;
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}
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cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
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/* Check whether userspace can specify guest syndrome value */
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kvm_arm_init_serror_injection(cs);
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return kvm_arm_init_cpreg_list(cpu);
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}
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int kvm_arch_destroy_vcpu(CPUState *cs)
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{
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return 0;
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}
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typedef struct Reg {
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uint64_t id;
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int offset;
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} Reg;
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#define COREREG(KERNELNAME, QEMUFIELD) \
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{ \
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KVM_REG_ARM | KVM_REG_SIZE_U32 | \
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KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
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offsetof(CPUARMState, QEMUFIELD) \
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}
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#define VFPSYSREG(R) \
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{ \
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KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
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KVM_REG_ARM_VFP_##R, \
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offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R]) \
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}
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/* Like COREREG, but handle fields which are in a uint64_t in CPUARMState. */
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#define COREREG64(KERNELNAME, QEMUFIELD) \
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{ \
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KVM_REG_ARM | KVM_REG_SIZE_U32 | \
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KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
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offsetoflow32(CPUARMState, QEMUFIELD) \
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}
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static const Reg regs[] = {
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/* R0_usr .. R14_usr */
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COREREG(usr_regs.uregs[0], regs[0]),
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COREREG(usr_regs.uregs[1], regs[1]),
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COREREG(usr_regs.uregs[2], regs[2]),
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COREREG(usr_regs.uregs[3], regs[3]),
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COREREG(usr_regs.uregs[4], regs[4]),
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COREREG(usr_regs.uregs[5], regs[5]),
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COREREG(usr_regs.uregs[6], regs[6]),
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COREREG(usr_regs.uregs[7], regs[7]),
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COREREG(usr_regs.uregs[8], usr_regs[0]),
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COREREG(usr_regs.uregs[9], usr_regs[1]),
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COREREG(usr_regs.uregs[10], usr_regs[2]),
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COREREG(usr_regs.uregs[11], usr_regs[3]),
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COREREG(usr_regs.uregs[12], usr_regs[4]),
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COREREG(usr_regs.uregs[13], banked_r13[BANK_USRSYS]),
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COREREG(usr_regs.uregs[14], banked_r14[BANK_USRSYS]),
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/* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
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COREREG(svc_regs[0], banked_r13[BANK_SVC]),
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COREREG(svc_regs[1], banked_r14[BANK_SVC]),
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COREREG64(svc_regs[2], banked_spsr[BANK_SVC]),
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COREREG(abt_regs[0], banked_r13[BANK_ABT]),
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COREREG(abt_regs[1], banked_r14[BANK_ABT]),
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COREREG64(abt_regs[2], banked_spsr[BANK_ABT]),
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COREREG(und_regs[0], banked_r13[BANK_UND]),
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COREREG(und_regs[1], banked_r14[BANK_UND]),
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COREREG64(und_regs[2], banked_spsr[BANK_UND]),
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COREREG(irq_regs[0], banked_r13[BANK_IRQ]),
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COREREG(irq_regs[1], banked_r14[BANK_IRQ]),
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COREREG64(irq_regs[2], banked_spsr[BANK_IRQ]),
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/* R8_fiq .. R14_fiq and SPSR_fiq */
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COREREG(fiq_regs[0], fiq_regs[0]),
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COREREG(fiq_regs[1], fiq_regs[1]),
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COREREG(fiq_regs[2], fiq_regs[2]),
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COREREG(fiq_regs[3], fiq_regs[3]),
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COREREG(fiq_regs[4], fiq_regs[4]),
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COREREG(fiq_regs[5], banked_r13[BANK_FIQ]),
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COREREG(fiq_regs[6], banked_r14[BANK_FIQ]),
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COREREG64(fiq_regs[7], banked_spsr[BANK_FIQ]),
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/* R15 */
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COREREG(usr_regs.uregs[15], regs[15]),
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/* VFP system registers */
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VFPSYSREG(FPSID),
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VFPSYSREG(MVFR1),
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VFPSYSREG(MVFR0),
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VFPSYSREG(FPEXC),
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VFPSYSREG(FPINST),
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VFPSYSREG(FPINST2),
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};
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int kvm_arch_put_registers(CPUState *cs, int level)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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struct kvm_one_reg r;
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int mode, bn;
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int ret, i;
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uint32_t cpsr, fpscr;
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/* Make sure the banked regs are properly set */
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mode = env->uncached_cpsr & CPSR_M;
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bn = bank_number(mode);
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if (mode == ARM_CPU_MODE_FIQ) {
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memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
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} else {
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memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
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}
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env->banked_r13[bn] = env->regs[13];
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env->banked_spsr[bn] = env->spsr;
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env->banked_r14[r14_bank_number(mode)] = env->regs[14];
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/* Now we can safely copy stuff down to the kernel */
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for (i = 0; i < ARRAY_SIZE(regs); i++) {
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r.id = regs[i].id;
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r.addr = (uintptr_t)(env) + regs[i].offset;
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
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if (ret) {
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return ret;
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}
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}
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/* Special cases which aren't a single CPUARMState field */
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cpsr = cpsr_read(env);
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
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KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
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r.addr = (uintptr_t)(&cpsr);
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
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if (ret) {
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return ret;
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}
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/* VFP registers */
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
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for (i = 0; i < 32; i++) {
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r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
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if (ret) {
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return ret;
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}
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r.id++;
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}
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r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
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KVM_REG_ARM_VFP_FPSCR;
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fpscr = vfp_get_fpscr(env);
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r.addr = (uintptr_t)&fpscr;
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
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if (ret) {
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return ret;
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}
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write_cpustate_to_list(cpu, true);
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if (!write_list_to_kvmstate(cpu, level)) {
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return EINVAL;
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}
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/*
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* Setting VCPU events should be triggered after syncing the registers
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* to avoid overwriting potential changes made by KVM upon calling
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* KVM_SET_VCPU_EVENTS ioctl
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*/
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ret = kvm_put_vcpu_events(cpu);
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if (ret) {
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return ret;
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}
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kvm_arm_sync_mpstate_to_kvm(cpu);
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return ret;
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}
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int kvm_arch_get_registers(CPUState *cs)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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struct kvm_one_reg r;
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int mode, bn;
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int ret, i;
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uint32_t cpsr, fpscr;
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for (i = 0; i < ARRAY_SIZE(regs); i++) {
|
|
r.id = regs[i].id;
|
|
r.addr = (uintptr_t)(env) + regs[i].offset;
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
/* Special cases which aren't a single CPUARMState field */
|
|
r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
|
|
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
|
|
r.addr = (uintptr_t)(&cpsr);
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
cpsr_write(env, cpsr, 0xffffffff, CPSRWriteRaw);
|
|
|
|
/* Make sure the current mode regs are properly set */
|
|
mode = env->uncached_cpsr & CPSR_M;
|
|
bn = bank_number(mode);
|
|
if (mode == ARM_CPU_MODE_FIQ) {
|
|
memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
|
|
} else {
|
|
memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
|
|
}
|
|
env->regs[13] = env->banked_r13[bn];
|
|
env->spsr = env->banked_spsr[bn];
|
|
env->regs[14] = env->banked_r14[r14_bank_number(mode)];
|
|
|
|
/* VFP registers */
|
|
r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
|
|
for (i = 0; i < 32; i++) {
|
|
r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
r.id++;
|
|
}
|
|
|
|
r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
|
|
KVM_REG_ARM_VFP_FPSCR;
|
|
r.addr = (uintptr_t)&fpscr;
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
vfp_set_fpscr(env, fpscr);
|
|
|
|
ret = kvm_get_vcpu_events(cpu);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
if (!write_kvmstate_to_list(cpu)) {
|
|
return EINVAL;
|
|
}
|
|
/* Note that it's OK to have registers which aren't in CPUState,
|
|
* so we can ignore a failure return here.
|
|
*/
|
|
write_list_to_cpustate(cpu);
|
|
|
|
kvm_arm_sync_mpstate_to_qemu(cpu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
|
|
{
|
|
qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
|
|
{
|
|
qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
|
|
{
|
|
qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
|
|
return false;
|
|
}
|
|
|
|
int kvm_arch_insert_hw_breakpoint(target_ulong addr,
|
|
target_ulong len, int type)
|
|
{
|
|
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
int kvm_arch_remove_hw_breakpoint(target_ulong addr,
|
|
target_ulong len, int type)
|
|
{
|
|
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
void kvm_arch_remove_all_hw_breakpoints(void)
|
|
{
|
|
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
|
|
}
|
|
|
|
void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr)
|
|
{
|
|
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
|
|
}
|
|
|
|
bool kvm_arm_hw_debug_active(CPUState *cs)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
|
|
{
|
|
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
|
|
}
|
|
|
|
void kvm_arm_pmu_init(CPUState *cs)
|
|
{
|
|
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
|
|
}
|
|
|
|
#define ARM_REG_DFSR ARM_CP15_REG32(0, 5, 0, 0)
|
|
#define ARM_REG_TTBCR ARM_CP15_REG32(0, 2, 0, 2)
|
|
/*
|
|
*DFSR:
|
|
* TTBCR.EAE == 0
|
|
* FS[4] - DFSR[10]
|
|
* FS[3:0] - DFSR[3:0]
|
|
* TTBCR.EAE == 1
|
|
* FS, bits [5:0]
|
|
*/
|
|
#define DFSR_FSC(lpae, v) \
|
|
((lpae) ? ((v) & 0x3F) : (((v) >> 6) | ((v) & 0x1F)))
|
|
|
|
#define DFSC_EXTABT(lpae) ((lpae) ? 0x10 : 0x08)
|
|
|
|
bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
|
|
{
|
|
uint32_t dfsr_val;
|
|
|
|
if (!kvm_get_one_reg(cs, ARM_REG_DFSR, &dfsr_val)) {
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
CPUARMState *env = &cpu->env;
|
|
uint32_t ttbcr;
|
|
int lpae = 0;
|
|
|
|
if (!kvm_get_one_reg(cs, ARM_REG_TTBCR, &ttbcr)) {
|
|
lpae = arm_feature(env, ARM_FEATURE_LPAE) && (ttbcr & TTBCR_EAE);
|
|
}
|
|
/* The verification is based on FS filed of the DFSR reg only*/
|
|
return (DFSR_FSC(lpae, dfsr_val) == DFSC_EXTABT(lpae));
|
|
}
|
|
return false;
|
|
}
|