1454 lines
47 KiB
C
1454 lines
47 KiB
C
/*
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* ARM AdvSIMD / SVE Vector Operations
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*
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* Copyright (c) 2018 Linaro
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "tcg/tcg-gvec-desc.h"
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#include "fpu/softfloat.h"
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#include "vec_internal.h"
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/* Note that vector data is stored in host-endian 64-bit chunks,
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so addressing units smaller than that needs a host-endian fixup. */
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#ifdef HOST_WORDS_BIGENDIAN
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#define H1(x) ((x) ^ 7)
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#define H2(x) ((x) ^ 3)
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#define H4(x) ((x) ^ 1)
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#else
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#define H1(x) (x)
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#define H2(x) (x)
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#define H4(x) (x)
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#endif
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/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
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static int16_t inl_qrdmlah_s16(int16_t src1, int16_t src2,
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int16_t src3, uint32_t *sat)
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{
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/* Simplify:
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* = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16
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* = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15
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*/
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int32_t ret = (int32_t)src1 * src2;
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ret = ((int32_t)src3 << 15) + ret + (1 << 14);
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ret >>= 15;
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if (ret != (int16_t)ret) {
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*sat = 1;
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ret = (ret < 0 ? -0x8000 : 0x7fff);
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}
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return ret;
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}
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uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,
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uint32_t src2, uint32_t src3)
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{
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uint32_t *sat = &env->vfp.qc[0];
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uint16_t e1 = inl_qrdmlah_s16(src1, src2, src3, sat);
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uint16_t e2 = inl_qrdmlah_s16(src1 >> 16, src2 >> 16, src3 >> 16, sat);
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return deposit32(e1, 16, 16, e2);
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}
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void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm,
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void *vq, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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int16_t *d = vd;
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int16_t *n = vn;
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int16_t *m = vm;
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uintptr_t i;
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for (i = 0; i < opr_sz / 2; ++i) {
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d[i] = inl_qrdmlah_s16(n[i], m[i], d[i], vq);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */
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static int16_t inl_qrdmlsh_s16(int16_t src1, int16_t src2,
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int16_t src3, uint32_t *sat)
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{
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/* Similarly, using subtraction:
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* = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16
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* = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15
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*/
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int32_t ret = (int32_t)src1 * src2;
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ret = ((int32_t)src3 << 15) - ret + (1 << 14);
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ret >>= 15;
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if (ret != (int16_t)ret) {
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*sat = 1;
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ret = (ret < 0 ? -0x8000 : 0x7fff);
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}
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return ret;
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}
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uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,
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uint32_t src2, uint32_t src3)
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{
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uint32_t *sat = &env->vfp.qc[0];
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uint16_t e1 = inl_qrdmlsh_s16(src1, src2, src3, sat);
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uint16_t e2 = inl_qrdmlsh_s16(src1 >> 16, src2 >> 16, src3 >> 16, sat);
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return deposit32(e1, 16, 16, e2);
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}
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void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
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void *vq, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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int16_t *d = vd;
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int16_t *n = vn;
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int16_t *m = vm;
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uintptr_t i;
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for (i = 0; i < opr_sz / 2; ++i) {
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d[i] = inl_qrdmlsh_s16(n[i], m[i], d[i], vq);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
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static int32_t inl_qrdmlah_s32(int32_t src1, int32_t src2,
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int32_t src3, uint32_t *sat)
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{
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/* Simplify similarly to int_qrdmlah_s16 above. */
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int64_t ret = (int64_t)src1 * src2;
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ret = ((int64_t)src3 << 31) + ret + (1 << 30);
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ret >>= 31;
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if (ret != (int32_t)ret) {
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*sat = 1;
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ret = (ret < 0 ? INT32_MIN : INT32_MAX);
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}
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return ret;
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}
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uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
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int32_t src2, int32_t src3)
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{
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uint32_t *sat = &env->vfp.qc[0];
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return inl_qrdmlah_s32(src1, src2, src3, sat);
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}
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void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
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void *vq, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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int32_t *d = vd;
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int32_t *n = vn;
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int32_t *m = vm;
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uintptr_t i;
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for (i = 0; i < opr_sz / 4; ++i) {
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d[i] = inl_qrdmlah_s32(n[i], m[i], d[i], vq);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */
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static int32_t inl_qrdmlsh_s32(int32_t src1, int32_t src2,
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int32_t src3, uint32_t *sat)
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{
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/* Simplify similarly to int_qrdmlsh_s16 above. */
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int64_t ret = (int64_t)src1 * src2;
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ret = ((int64_t)src3 << 31) - ret + (1 << 30);
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ret >>= 31;
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if (ret != (int32_t)ret) {
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*sat = 1;
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ret = (ret < 0 ? INT32_MIN : INT32_MAX);
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}
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return ret;
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}
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uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
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int32_t src2, int32_t src3)
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{
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uint32_t *sat = &env->vfp.qc[0];
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return inl_qrdmlsh_s32(src1, src2, src3, sat);
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}
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void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
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void *vq, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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int32_t *d = vd;
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int32_t *n = vn;
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int32_t *m = vm;
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uintptr_t i;
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for (i = 0; i < opr_sz / 4; ++i) {
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d[i] = inl_qrdmlsh_s32(n[i], m[i], d[i], vq);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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/* Integer 8 and 16-bit dot-product.
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*
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* Note that for the loops herein, host endianness does not matter
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* with respect to the ordering of data within the 64-bit lanes.
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* All elements are treated equally, no matter where they are.
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*/
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void HELPER(gvec_sdot_b)(void *vd, void *vn, void *vm, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc);
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uint32_t *d = vd;
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int8_t *n = vn, *m = vm;
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for (i = 0; i < opr_sz / 4; ++i) {
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d[i] += n[i * 4 + 0] * m[i * 4 + 0]
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+ n[i * 4 + 1] * m[i * 4 + 1]
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+ n[i * 4 + 2] * m[i * 4 + 2]
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+ n[i * 4 + 3] * m[i * 4 + 3];
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_udot_b)(void *vd, void *vn, void *vm, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc);
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uint32_t *d = vd;
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uint8_t *n = vn, *m = vm;
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for (i = 0; i < opr_sz / 4; ++i) {
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d[i] += n[i * 4 + 0] * m[i * 4 + 0]
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+ n[i * 4 + 1] * m[i * 4 + 1]
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+ n[i * 4 + 2] * m[i * 4 + 2]
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+ n[i * 4 + 3] * m[i * 4 + 3];
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_sdot_h)(void *vd, void *vn, void *vm, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc);
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uint64_t *d = vd;
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int16_t *n = vn, *m = vm;
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for (i = 0; i < opr_sz / 8; ++i) {
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d[i] += (int64_t)n[i * 4 + 0] * m[i * 4 + 0]
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+ (int64_t)n[i * 4 + 1] * m[i * 4 + 1]
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+ (int64_t)n[i * 4 + 2] * m[i * 4 + 2]
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+ (int64_t)n[i * 4 + 3] * m[i * 4 + 3];
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_udot_h)(void *vd, void *vn, void *vm, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc);
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uint64_t *d = vd;
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uint16_t *n = vn, *m = vm;
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for (i = 0; i < opr_sz / 8; ++i) {
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d[i] += (uint64_t)n[i * 4 + 0] * m[i * 4 + 0]
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+ (uint64_t)n[i * 4 + 1] * m[i * 4 + 1]
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+ (uint64_t)n[i * 4 + 2] * m[i * 4 + 2]
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+ (uint64_t)n[i * 4 + 3] * m[i * 4 + 3];
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
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{
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intptr_t i, segend, opr_sz = simd_oprsz(desc), opr_sz_4 = opr_sz / 4;
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intptr_t index = simd_data(desc);
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uint32_t *d = vd;
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int8_t *n = vn;
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int8_t *m_indexed = (int8_t *)vm + index * 4;
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/* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
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* Otherwise opr_sz is a multiple of 16.
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*/
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segend = MIN(4, opr_sz_4);
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i = 0;
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do {
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int8_t m0 = m_indexed[i * 4 + 0];
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int8_t m1 = m_indexed[i * 4 + 1];
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int8_t m2 = m_indexed[i * 4 + 2];
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int8_t m3 = m_indexed[i * 4 + 3];
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do {
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d[i] += n[i * 4 + 0] * m0
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+ n[i * 4 + 1] * m1
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+ n[i * 4 + 2] * m2
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+ n[i * 4 + 3] * m3;
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} while (++i < segend);
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segend = i + 4;
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} while (i < opr_sz_4);
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
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{
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intptr_t i, segend, opr_sz = simd_oprsz(desc), opr_sz_4 = opr_sz / 4;
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intptr_t index = simd_data(desc);
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uint32_t *d = vd;
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uint8_t *n = vn;
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uint8_t *m_indexed = (uint8_t *)vm + index * 4;
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/* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
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* Otherwise opr_sz is a multiple of 16.
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*/
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segend = MIN(4, opr_sz_4);
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i = 0;
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do {
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uint8_t m0 = m_indexed[i * 4 + 0];
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uint8_t m1 = m_indexed[i * 4 + 1];
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uint8_t m2 = m_indexed[i * 4 + 2];
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uint8_t m3 = m_indexed[i * 4 + 3];
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do {
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d[i] += n[i * 4 + 0] * m0
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+ n[i * 4 + 1] * m1
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+ n[i * 4 + 2] * m2
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+ n[i * 4 + 3] * m3;
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} while (++i < segend);
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segend = i + 4;
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} while (i < opr_sz_4);
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_sdot_idx_h)(void *vd, void *vn, void *vm, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc), opr_sz_8 = opr_sz / 8;
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intptr_t index = simd_data(desc);
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uint64_t *d = vd;
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int16_t *n = vn;
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int16_t *m_indexed = (int16_t *)vm + index * 4;
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/* This is supported by SVE only, so opr_sz is always a multiple of 16.
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* Process the entire segment all at once, writing back the results
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* only after we've consumed all of the inputs.
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*/
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for (i = 0; i < opr_sz_8 ; i += 2) {
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uint64_t d0, d1;
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d0 = n[i * 4 + 0] * (int64_t)m_indexed[i * 4 + 0];
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d0 += n[i * 4 + 1] * (int64_t)m_indexed[i * 4 + 1];
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d0 += n[i * 4 + 2] * (int64_t)m_indexed[i * 4 + 2];
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d0 += n[i * 4 + 3] * (int64_t)m_indexed[i * 4 + 3];
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d1 = n[i * 4 + 4] * (int64_t)m_indexed[i * 4 + 0];
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d1 += n[i * 4 + 5] * (int64_t)m_indexed[i * 4 + 1];
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d1 += n[i * 4 + 6] * (int64_t)m_indexed[i * 4 + 2];
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d1 += n[i * 4 + 7] * (int64_t)m_indexed[i * 4 + 3];
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d[i + 0] += d0;
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d[i + 1] += d1;
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_udot_idx_h)(void *vd, void *vn, void *vm, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc), opr_sz_8 = opr_sz / 8;
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intptr_t index = simd_data(desc);
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uint64_t *d = vd;
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uint16_t *n = vn;
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uint16_t *m_indexed = (uint16_t *)vm + index * 4;
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/* This is supported by SVE only, so opr_sz is always a multiple of 16.
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* Process the entire segment all at once, writing back the results
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* only after we've consumed all of the inputs.
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*/
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for (i = 0; i < opr_sz_8 ; i += 2) {
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uint64_t d0, d1;
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d0 = n[i * 4 + 0] * (uint64_t)m_indexed[i * 4 + 0];
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d0 += n[i * 4 + 1] * (uint64_t)m_indexed[i * 4 + 1];
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d0 += n[i * 4 + 2] * (uint64_t)m_indexed[i * 4 + 2];
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d0 += n[i * 4 + 3] * (uint64_t)m_indexed[i * 4 + 3];
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d1 = n[i * 4 + 4] * (uint64_t)m_indexed[i * 4 + 0];
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d1 += n[i * 4 + 5] * (uint64_t)m_indexed[i * 4 + 1];
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d1 += n[i * 4 + 6] * (uint64_t)m_indexed[i * 4 + 2];
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d1 += n[i * 4 + 7] * (uint64_t)m_indexed[i * 4 + 3];
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d[i + 0] += d0;
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d[i + 1] += d1;
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
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void *vfpst, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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float16 *d = vd;
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float16 *n = vn;
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float16 *m = vm;
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float_status *fpst = vfpst;
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uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
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uint32_t neg_imag = neg_real ^ 1;
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uintptr_t i;
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/* Shift boolean to the sign bit so we can xor to negate. */
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neg_real <<= 15;
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neg_imag <<= 15;
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for (i = 0; i < opr_sz / 2; i += 2) {
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float16 e0 = n[H2(i)];
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float16 e1 = m[H2(i + 1)] ^ neg_imag;
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float16 e2 = n[H2(i + 1)];
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float16 e3 = m[H2(i)] ^ neg_real;
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d[H2(i)] = float16_add(e0, e1, fpst);
|
|
d[H2(i + 1)] = float16_add(e2, e3, fpst);
|
|
}
|
|
clear_tail(d, opr_sz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
|
|
void *vfpst, uint32_t desc)
|
|
{
|
|
uintptr_t opr_sz = simd_oprsz(desc);
|
|
float32 *d = vd;
|
|
float32 *n = vn;
|
|
float32 *m = vm;
|
|
float_status *fpst = vfpst;
|
|
uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
|
|
uint32_t neg_imag = neg_real ^ 1;
|
|
uintptr_t i;
|
|
|
|
/* Shift boolean to the sign bit so we can xor to negate. */
|
|
neg_real <<= 31;
|
|
neg_imag <<= 31;
|
|
|
|
for (i = 0; i < opr_sz / 4; i += 2) {
|
|
float32 e0 = n[H4(i)];
|
|
float32 e1 = m[H4(i + 1)] ^ neg_imag;
|
|
float32 e2 = n[H4(i + 1)];
|
|
float32 e3 = m[H4(i)] ^ neg_real;
|
|
|
|
d[H4(i)] = float32_add(e0, e1, fpst);
|
|
d[H4(i + 1)] = float32_add(e2, e3, fpst);
|
|
}
|
|
clear_tail(d, opr_sz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
|
|
void *vfpst, uint32_t desc)
|
|
{
|
|
uintptr_t opr_sz = simd_oprsz(desc);
|
|
float64 *d = vd;
|
|
float64 *n = vn;
|
|
float64 *m = vm;
|
|
float_status *fpst = vfpst;
|
|
uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1);
|
|
uint64_t neg_imag = neg_real ^ 1;
|
|
uintptr_t i;
|
|
|
|
/* Shift boolean to the sign bit so we can xor to negate. */
|
|
neg_real <<= 63;
|
|
neg_imag <<= 63;
|
|
|
|
for (i = 0; i < opr_sz / 8; i += 2) {
|
|
float64 e0 = n[i];
|
|
float64 e1 = m[i + 1] ^ neg_imag;
|
|
float64 e2 = n[i + 1];
|
|
float64 e3 = m[i] ^ neg_real;
|
|
|
|
d[i] = float64_add(e0, e1, fpst);
|
|
d[i + 1] = float64_add(e2, e3, fpst);
|
|
}
|
|
clear_tail(d, opr_sz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm,
|
|
void *vfpst, uint32_t desc)
|
|
{
|
|
uintptr_t opr_sz = simd_oprsz(desc);
|
|
float16 *d = vd;
|
|
float16 *n = vn;
|
|
float16 *m = vm;
|
|
float_status *fpst = vfpst;
|
|
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
|
|
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
|
|
uint32_t neg_real = flip ^ neg_imag;
|
|
uintptr_t i;
|
|
|
|
/* Shift boolean to the sign bit so we can xor to negate. */
|
|
neg_real <<= 15;
|
|
neg_imag <<= 15;
|
|
|
|
for (i = 0; i < opr_sz / 2; i += 2) {
|
|
float16 e2 = n[H2(i + flip)];
|
|
float16 e1 = m[H2(i + flip)] ^ neg_real;
|
|
float16 e4 = e2;
|
|
float16 e3 = m[H2(i + 1 - flip)] ^ neg_imag;
|
|
|
|
d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst);
|
|
d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst);
|
|
}
|
|
clear_tail(d, opr_sz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm,
|
|
void *vfpst, uint32_t desc)
|
|
{
|
|
uintptr_t opr_sz = simd_oprsz(desc);
|
|
float16 *d = vd;
|
|
float16 *n = vn;
|
|
float16 *m = vm;
|
|
float_status *fpst = vfpst;
|
|
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
|
|
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
|
|
intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
|
|
uint32_t neg_real = flip ^ neg_imag;
|
|
intptr_t elements = opr_sz / sizeof(float16);
|
|
intptr_t eltspersegment = 16 / sizeof(float16);
|
|
intptr_t i, j;
|
|
|
|
/* Shift boolean to the sign bit so we can xor to negate. */
|
|
neg_real <<= 15;
|
|
neg_imag <<= 15;
|
|
|
|
for (i = 0; i < elements; i += eltspersegment) {
|
|
float16 mr = m[H2(i + 2 * index + 0)];
|
|
float16 mi = m[H2(i + 2 * index + 1)];
|
|
float16 e1 = neg_real ^ (flip ? mi : mr);
|
|
float16 e3 = neg_imag ^ (flip ? mr : mi);
|
|
|
|
for (j = i; j < i + eltspersegment; j += 2) {
|
|
float16 e2 = n[H2(j + flip)];
|
|
float16 e4 = e2;
|
|
|
|
d[H2(j)] = float16_muladd(e2, e1, d[H2(j)], 0, fpst);
|
|
d[H2(j + 1)] = float16_muladd(e4, e3, d[H2(j + 1)], 0, fpst);
|
|
}
|
|
}
|
|
clear_tail(d, opr_sz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm,
|
|
void *vfpst, uint32_t desc)
|
|
{
|
|
uintptr_t opr_sz = simd_oprsz(desc);
|
|
float32 *d = vd;
|
|
float32 *n = vn;
|
|
float32 *m = vm;
|
|
float_status *fpst = vfpst;
|
|
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
|
|
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
|
|
uint32_t neg_real = flip ^ neg_imag;
|
|
uintptr_t i;
|
|
|
|
/* Shift boolean to the sign bit so we can xor to negate. */
|
|
neg_real <<= 31;
|
|
neg_imag <<= 31;
|
|
|
|
for (i = 0; i < opr_sz / 4; i += 2) {
|
|
float32 e2 = n[H4(i + flip)];
|
|
float32 e1 = m[H4(i + flip)] ^ neg_real;
|
|
float32 e4 = e2;
|
|
float32 e3 = m[H4(i + 1 - flip)] ^ neg_imag;
|
|
|
|
d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst);
|
|
d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst);
|
|
}
|
|
clear_tail(d, opr_sz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm,
|
|
void *vfpst, uint32_t desc)
|
|
{
|
|
uintptr_t opr_sz = simd_oprsz(desc);
|
|
float32 *d = vd;
|
|
float32 *n = vn;
|
|
float32 *m = vm;
|
|
float_status *fpst = vfpst;
|
|
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
|
|
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
|
|
intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
|
|
uint32_t neg_real = flip ^ neg_imag;
|
|
intptr_t elements = opr_sz / sizeof(float32);
|
|
intptr_t eltspersegment = 16 / sizeof(float32);
|
|
intptr_t i, j;
|
|
|
|
/* Shift boolean to the sign bit so we can xor to negate. */
|
|
neg_real <<= 31;
|
|
neg_imag <<= 31;
|
|
|
|
for (i = 0; i < elements; i += eltspersegment) {
|
|
float32 mr = m[H4(i + 2 * index + 0)];
|
|
float32 mi = m[H4(i + 2 * index + 1)];
|
|
float32 e1 = neg_real ^ (flip ? mi : mr);
|
|
float32 e3 = neg_imag ^ (flip ? mr : mi);
|
|
|
|
for (j = i; j < i + eltspersegment; j += 2) {
|
|
float32 e2 = n[H4(j + flip)];
|
|
float32 e4 = e2;
|
|
|
|
d[H4(j)] = float32_muladd(e2, e1, d[H4(j)], 0, fpst);
|
|
d[H4(j + 1)] = float32_muladd(e4, e3, d[H4(j + 1)], 0, fpst);
|
|
}
|
|
}
|
|
clear_tail(d, opr_sz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm,
|
|
void *vfpst, uint32_t desc)
|
|
{
|
|
uintptr_t opr_sz = simd_oprsz(desc);
|
|
float64 *d = vd;
|
|
float64 *n = vn;
|
|
float64 *m = vm;
|
|
float_status *fpst = vfpst;
|
|
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
|
|
uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
|
|
uint64_t neg_real = flip ^ neg_imag;
|
|
uintptr_t i;
|
|
|
|
/* Shift boolean to the sign bit so we can xor to negate. */
|
|
neg_real <<= 63;
|
|
neg_imag <<= 63;
|
|
|
|
for (i = 0; i < opr_sz / 8; i += 2) {
|
|
float64 e2 = n[i + flip];
|
|
float64 e1 = m[i + flip] ^ neg_real;
|
|
float64 e4 = e2;
|
|
float64 e3 = m[i + 1 - flip] ^ neg_imag;
|
|
|
|
d[i] = float64_muladd(e2, e1, d[i], 0, fpst);
|
|
d[i + 1] = float64_muladd(e4, e3, d[i + 1], 0, fpst);
|
|
}
|
|
clear_tail(d, opr_sz, simd_maxsz(desc));
|
|
}
|
|
|
|
#define DO_2OP(NAME, FUNC, TYPE) \
|
|
void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
|
|
{ \
|
|
intptr_t i, oprsz = simd_oprsz(desc); \
|
|
TYPE *d = vd, *n = vn; \
|
|
for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
|
|
d[i] = FUNC(n[i], stat); \
|
|
} \
|
|
clear_tail(d, oprsz, simd_maxsz(desc)); \
|
|
}
|
|
|
|
DO_2OP(gvec_frecpe_h, helper_recpe_f16, float16)
|
|
DO_2OP(gvec_frecpe_s, helper_recpe_f32, float32)
|
|
DO_2OP(gvec_frecpe_d, helper_recpe_f64, float64)
|
|
|
|
DO_2OP(gvec_frsqrte_h, helper_rsqrte_f16, float16)
|
|
DO_2OP(gvec_frsqrte_s, helper_rsqrte_f32, float32)
|
|
DO_2OP(gvec_frsqrte_d, helper_rsqrte_f64, float64)
|
|
|
|
#undef DO_2OP
|
|
|
|
/* Floating-point trigonometric starting value.
|
|
* See the ARM ARM pseudocode function FPTrigSMul.
|
|
*/
|
|
static float16 float16_ftsmul(float16 op1, uint16_t op2, float_status *stat)
|
|
{
|
|
float16 result = float16_mul(op1, op1, stat);
|
|
if (!float16_is_any_nan(result)) {
|
|
result = float16_set_sign(result, op2 & 1);
|
|
}
|
|
return result;
|
|
}
|
|
|
|
static float32 float32_ftsmul(float32 op1, uint32_t op2, float_status *stat)
|
|
{
|
|
float32 result = float32_mul(op1, op1, stat);
|
|
if (!float32_is_any_nan(result)) {
|
|
result = float32_set_sign(result, op2 & 1);
|
|
}
|
|
return result;
|
|
}
|
|
|
|
static float64 float64_ftsmul(float64 op1, uint64_t op2, float_status *stat)
|
|
{
|
|
float64 result = float64_mul(op1, op1, stat);
|
|
if (!float64_is_any_nan(result)) {
|
|
result = float64_set_sign(result, op2 & 1);
|
|
}
|
|
return result;
|
|
}
|
|
|
|
static float32 float32_abd(float32 op1, float32 op2, float_status *stat)
|
|
{
|
|
return float32_abs(float32_sub(op1, op2, stat));
|
|
}
|
|
|
|
#define DO_3OP(NAME, FUNC, TYPE) \
|
|
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
|
|
{ \
|
|
intptr_t i, oprsz = simd_oprsz(desc); \
|
|
TYPE *d = vd, *n = vn, *m = vm; \
|
|
for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
|
|
d[i] = FUNC(n[i], m[i], stat); \
|
|
} \
|
|
clear_tail(d, oprsz, simd_maxsz(desc)); \
|
|
}
|
|
|
|
DO_3OP(gvec_fadd_h, float16_add, float16)
|
|
DO_3OP(gvec_fadd_s, float32_add, float32)
|
|
DO_3OP(gvec_fadd_d, float64_add, float64)
|
|
|
|
DO_3OP(gvec_fsub_h, float16_sub, float16)
|
|
DO_3OP(gvec_fsub_s, float32_sub, float32)
|
|
DO_3OP(gvec_fsub_d, float64_sub, float64)
|
|
|
|
DO_3OP(gvec_fmul_h, float16_mul, float16)
|
|
DO_3OP(gvec_fmul_s, float32_mul, float32)
|
|
DO_3OP(gvec_fmul_d, float64_mul, float64)
|
|
|
|
DO_3OP(gvec_ftsmul_h, float16_ftsmul, float16)
|
|
DO_3OP(gvec_ftsmul_s, float32_ftsmul, float32)
|
|
DO_3OP(gvec_ftsmul_d, float64_ftsmul, float64)
|
|
|
|
DO_3OP(gvec_fabd_s, float32_abd, float32)
|
|
|
|
#ifdef TARGET_AARCH64
|
|
|
|
DO_3OP(gvec_recps_h, helper_recpsf_f16, float16)
|
|
DO_3OP(gvec_recps_s, helper_recpsf_f32, float32)
|
|
DO_3OP(gvec_recps_d, helper_recpsf_f64, float64)
|
|
|
|
DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16)
|
|
DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32)
|
|
DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64)
|
|
|
|
#endif
|
|
#undef DO_3OP
|
|
|
|
/* For the indexed ops, SVE applies the index per 128-bit vector segment.
|
|
* For AdvSIMD, there is of course only one such vector segment.
|
|
*/
|
|
|
|
#define DO_MUL_IDX(NAME, TYPE, H) \
|
|
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
|
|
{ \
|
|
intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
|
|
intptr_t idx = simd_data(desc); \
|
|
TYPE *d = vd, *n = vn, *m = vm; \
|
|
for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
|
|
TYPE mm = m[H(i + idx)]; \
|
|
for (j = 0; j < segment; j++) { \
|
|
d[i + j] = TYPE##_mul(n[i + j], mm, stat); \
|
|
} \
|
|
} \
|
|
clear_tail(d, oprsz, simd_maxsz(desc)); \
|
|
}
|
|
|
|
DO_MUL_IDX(gvec_fmul_idx_h, float16, H2)
|
|
DO_MUL_IDX(gvec_fmul_idx_s, float32, H4)
|
|
DO_MUL_IDX(gvec_fmul_idx_d, float64, )
|
|
|
|
#undef DO_MUL_IDX
|
|
|
|
#define DO_FMLA_IDX(NAME, TYPE, H) \
|
|
void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \
|
|
void *stat, uint32_t desc) \
|
|
{ \
|
|
intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
|
|
TYPE op1_neg = extract32(desc, SIMD_DATA_SHIFT, 1); \
|
|
intptr_t idx = desc >> (SIMD_DATA_SHIFT + 1); \
|
|
TYPE *d = vd, *n = vn, *m = vm, *a = va; \
|
|
op1_neg <<= (8 * sizeof(TYPE) - 1); \
|
|
for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
|
|
TYPE mm = m[H(i + idx)]; \
|
|
for (j = 0; j < segment; j++) { \
|
|
d[i + j] = TYPE##_muladd(n[i + j] ^ op1_neg, \
|
|
mm, a[i + j], 0, stat); \
|
|
} \
|
|
} \
|
|
clear_tail(d, oprsz, simd_maxsz(desc)); \
|
|
}
|
|
|
|
DO_FMLA_IDX(gvec_fmla_idx_h, float16, H2)
|
|
DO_FMLA_IDX(gvec_fmla_idx_s, float32, H4)
|
|
DO_FMLA_IDX(gvec_fmla_idx_d, float64, )
|
|
|
|
#undef DO_FMLA_IDX
|
|
|
|
#define DO_SAT(NAME, WTYPE, TYPEN, TYPEM, OP, MIN, MAX) \
|
|
void HELPER(NAME)(void *vd, void *vq, void *vn, void *vm, uint32_t desc) \
|
|
{ \
|
|
intptr_t i, oprsz = simd_oprsz(desc); \
|
|
TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
|
|
bool q = false; \
|
|
for (i = 0; i < oprsz / sizeof(TYPEN); i++) { \
|
|
WTYPE dd = (WTYPE)n[i] OP m[i]; \
|
|
if (dd < MIN) { \
|
|
dd = MIN; \
|
|
q = true; \
|
|
} else if (dd > MAX) { \
|
|
dd = MAX; \
|
|
q = true; \
|
|
} \
|
|
d[i] = dd; \
|
|
} \
|
|
if (q) { \
|
|
uint32_t *qc = vq; \
|
|
qc[0] = 1; \
|
|
} \
|
|
clear_tail(d, oprsz, simd_maxsz(desc)); \
|
|
}
|
|
|
|
DO_SAT(gvec_uqadd_b, int, uint8_t, uint8_t, +, 0, UINT8_MAX)
|
|
DO_SAT(gvec_uqadd_h, int, uint16_t, uint16_t, +, 0, UINT16_MAX)
|
|
DO_SAT(gvec_uqadd_s, int64_t, uint32_t, uint32_t, +, 0, UINT32_MAX)
|
|
|
|
DO_SAT(gvec_sqadd_b, int, int8_t, int8_t, +, INT8_MIN, INT8_MAX)
|
|
DO_SAT(gvec_sqadd_h, int, int16_t, int16_t, +, INT16_MIN, INT16_MAX)
|
|
DO_SAT(gvec_sqadd_s, int64_t, int32_t, int32_t, +, INT32_MIN, INT32_MAX)
|
|
|
|
DO_SAT(gvec_uqsub_b, int, uint8_t, uint8_t, -, 0, UINT8_MAX)
|
|
DO_SAT(gvec_uqsub_h, int, uint16_t, uint16_t, -, 0, UINT16_MAX)
|
|
DO_SAT(gvec_uqsub_s, int64_t, uint32_t, uint32_t, -, 0, UINT32_MAX)
|
|
|
|
DO_SAT(gvec_sqsub_b, int, int8_t, int8_t, -, INT8_MIN, INT8_MAX)
|
|
DO_SAT(gvec_sqsub_h, int, int16_t, int16_t, -, INT16_MIN, INT16_MAX)
|
|
DO_SAT(gvec_sqsub_s, int64_t, int32_t, int32_t, -, INT32_MIN, INT32_MAX)
|
|
|
|
#undef DO_SAT
|
|
|
|
void HELPER(gvec_uqadd_d)(void *vd, void *vq, void *vn,
|
|
void *vm, uint32_t desc)
|
|
{
|
|
intptr_t i, oprsz = simd_oprsz(desc);
|
|
uint64_t *d = vd, *n = vn, *m = vm;
|
|
bool q = false;
|
|
|
|
for (i = 0; i < oprsz / 8; i++) {
|
|
uint64_t nn = n[i], mm = m[i], dd = nn + mm;
|
|
if (dd < nn) {
|
|
dd = UINT64_MAX;
|
|
q = true;
|
|
}
|
|
d[i] = dd;
|
|
}
|
|
if (q) {
|
|
uint32_t *qc = vq;
|
|
qc[0] = 1;
|
|
}
|
|
clear_tail(d, oprsz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_uqsub_d)(void *vd, void *vq, void *vn,
|
|
void *vm, uint32_t desc)
|
|
{
|
|
intptr_t i, oprsz = simd_oprsz(desc);
|
|
uint64_t *d = vd, *n = vn, *m = vm;
|
|
bool q = false;
|
|
|
|
for (i = 0; i < oprsz / 8; i++) {
|
|
uint64_t nn = n[i], mm = m[i], dd = nn - mm;
|
|
if (nn < mm) {
|
|
dd = 0;
|
|
q = true;
|
|
}
|
|
d[i] = dd;
|
|
}
|
|
if (q) {
|
|
uint32_t *qc = vq;
|
|
qc[0] = 1;
|
|
}
|
|
clear_tail(d, oprsz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_sqadd_d)(void *vd, void *vq, void *vn,
|
|
void *vm, uint32_t desc)
|
|
{
|
|
intptr_t i, oprsz = simd_oprsz(desc);
|
|
int64_t *d = vd, *n = vn, *m = vm;
|
|
bool q = false;
|
|
|
|
for (i = 0; i < oprsz / 8; i++) {
|
|
int64_t nn = n[i], mm = m[i], dd = nn + mm;
|
|
if (((dd ^ nn) & ~(nn ^ mm)) & INT64_MIN) {
|
|
dd = (nn >> 63) ^ ~INT64_MIN;
|
|
q = true;
|
|
}
|
|
d[i] = dd;
|
|
}
|
|
if (q) {
|
|
uint32_t *qc = vq;
|
|
qc[0] = 1;
|
|
}
|
|
clear_tail(d, oprsz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn,
|
|
void *vm, uint32_t desc)
|
|
{
|
|
intptr_t i, oprsz = simd_oprsz(desc);
|
|
int64_t *d = vd, *n = vn, *m = vm;
|
|
bool q = false;
|
|
|
|
for (i = 0; i < oprsz / 8; i++) {
|
|
int64_t nn = n[i], mm = m[i], dd = nn - mm;
|
|
if (((dd ^ nn) & (nn ^ mm)) & INT64_MIN) {
|
|
dd = (nn >> 63) ^ ~INT64_MIN;
|
|
q = true;
|
|
}
|
|
d[i] = dd;
|
|
}
|
|
if (q) {
|
|
uint32_t *qc = vq;
|
|
qc[0] = 1;
|
|
}
|
|
clear_tail(d, oprsz, simd_maxsz(desc));
|
|
}
|
|
|
|
|
|
#define DO_SRA(NAME, TYPE) \
|
|
void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
|
|
{ \
|
|
intptr_t i, oprsz = simd_oprsz(desc); \
|
|
int shift = simd_data(desc); \
|
|
TYPE *d = vd, *n = vn; \
|
|
for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
|
|
d[i] += n[i] >> shift; \
|
|
} \
|
|
clear_tail(d, oprsz, simd_maxsz(desc)); \
|
|
}
|
|
|
|
DO_SRA(gvec_ssra_b, int8_t)
|
|
DO_SRA(gvec_ssra_h, int16_t)
|
|
DO_SRA(gvec_ssra_s, int32_t)
|
|
DO_SRA(gvec_ssra_d, int64_t)
|
|
|
|
DO_SRA(gvec_usra_b, uint8_t)
|
|
DO_SRA(gvec_usra_h, uint16_t)
|
|
DO_SRA(gvec_usra_s, uint32_t)
|
|
DO_SRA(gvec_usra_d, uint64_t)
|
|
|
|
#undef DO_SRA
|
|
|
|
#define DO_RSHR(NAME, TYPE) \
|
|
void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
|
|
{ \
|
|
intptr_t i, oprsz = simd_oprsz(desc); \
|
|
int shift = simd_data(desc); \
|
|
TYPE *d = vd, *n = vn; \
|
|
for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
|
|
TYPE tmp = n[i] >> (shift - 1); \
|
|
d[i] = (tmp >> 1) + (tmp & 1); \
|
|
} \
|
|
clear_tail(d, oprsz, simd_maxsz(desc)); \
|
|
}
|
|
|
|
DO_RSHR(gvec_srshr_b, int8_t)
|
|
DO_RSHR(gvec_srshr_h, int16_t)
|
|
DO_RSHR(gvec_srshr_s, int32_t)
|
|
DO_RSHR(gvec_srshr_d, int64_t)
|
|
|
|
DO_RSHR(gvec_urshr_b, uint8_t)
|
|
DO_RSHR(gvec_urshr_h, uint16_t)
|
|
DO_RSHR(gvec_urshr_s, uint32_t)
|
|
DO_RSHR(gvec_urshr_d, uint64_t)
|
|
|
|
#undef DO_RSHR
|
|
|
|
#define DO_RSRA(NAME, TYPE) \
|
|
void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
|
|
{ \
|
|
intptr_t i, oprsz = simd_oprsz(desc); \
|
|
int shift = simd_data(desc); \
|
|
TYPE *d = vd, *n = vn; \
|
|
for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
|
|
TYPE tmp = n[i] >> (shift - 1); \
|
|
d[i] += (tmp >> 1) + (tmp & 1); \
|
|
} \
|
|
clear_tail(d, oprsz, simd_maxsz(desc)); \
|
|
}
|
|
|
|
DO_RSRA(gvec_srsra_b, int8_t)
|
|
DO_RSRA(gvec_srsra_h, int16_t)
|
|
DO_RSRA(gvec_srsra_s, int32_t)
|
|
DO_RSRA(gvec_srsra_d, int64_t)
|
|
|
|
DO_RSRA(gvec_ursra_b, uint8_t)
|
|
DO_RSRA(gvec_ursra_h, uint16_t)
|
|
DO_RSRA(gvec_ursra_s, uint32_t)
|
|
DO_RSRA(gvec_ursra_d, uint64_t)
|
|
|
|
#undef DO_RSRA
|
|
|
|
#define DO_SRI(NAME, TYPE) \
|
|
void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
|
|
{ \
|
|
intptr_t i, oprsz = simd_oprsz(desc); \
|
|
int shift = simd_data(desc); \
|
|
TYPE *d = vd, *n = vn; \
|
|
for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
|
|
d[i] = deposit64(d[i], 0, sizeof(TYPE) * 8 - shift, n[i] >> shift); \
|
|
} \
|
|
clear_tail(d, oprsz, simd_maxsz(desc)); \
|
|
}
|
|
|
|
DO_SRI(gvec_sri_b, uint8_t)
|
|
DO_SRI(gvec_sri_h, uint16_t)
|
|
DO_SRI(gvec_sri_s, uint32_t)
|
|
DO_SRI(gvec_sri_d, uint64_t)
|
|
|
|
#undef DO_SRI
|
|
|
|
#define DO_SLI(NAME, TYPE) \
|
|
void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
|
|
{ \
|
|
intptr_t i, oprsz = simd_oprsz(desc); \
|
|
int shift = simd_data(desc); \
|
|
TYPE *d = vd, *n = vn; \
|
|
for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
|
|
d[i] = deposit64(d[i], shift, sizeof(TYPE) * 8 - shift, n[i]); \
|
|
} \
|
|
clear_tail(d, oprsz, simd_maxsz(desc)); \
|
|
}
|
|
|
|
DO_SLI(gvec_sli_b, uint8_t)
|
|
DO_SLI(gvec_sli_h, uint16_t)
|
|
DO_SLI(gvec_sli_s, uint32_t)
|
|
DO_SLI(gvec_sli_d, uint64_t)
|
|
|
|
#undef DO_SLI
|
|
|
|
/*
|
|
* Convert float16 to float32, raising no exceptions and
|
|
* preserving exceptional values, including SNaN.
|
|
* This is effectively an unpack+repack operation.
|
|
*/
|
|
static float32 float16_to_float32_by_bits(uint32_t f16, bool fz16)
|
|
{
|
|
const int f16_bias = 15;
|
|
const int f32_bias = 127;
|
|
uint32_t sign = extract32(f16, 15, 1);
|
|
uint32_t exp = extract32(f16, 10, 5);
|
|
uint32_t frac = extract32(f16, 0, 10);
|
|
|
|
if (exp == 0x1f) {
|
|
/* Inf or NaN */
|
|
exp = 0xff;
|
|
} else if (exp == 0) {
|
|
/* Zero or denormal. */
|
|
if (frac != 0) {
|
|
if (fz16) {
|
|
frac = 0;
|
|
} else {
|
|
/*
|
|
* Denormal; these are all normal float32.
|
|
* Shift the fraction so that the msb is at bit 11,
|
|
* then remove bit 11 as the implicit bit of the
|
|
* normalized float32. Note that we still go through
|
|
* the shift for normal numbers below, to put the
|
|
* float32 fraction at the right place.
|
|
*/
|
|
int shift = clz32(frac) - 21;
|
|
frac = (frac << shift) & 0x3ff;
|
|
exp = f32_bias - f16_bias - shift + 1;
|
|
}
|
|
}
|
|
} else {
|
|
/* Normal number; adjust the bias. */
|
|
exp += f32_bias - f16_bias;
|
|
}
|
|
sign <<= 31;
|
|
exp <<= 23;
|
|
frac <<= 23 - 10;
|
|
|
|
return sign | exp | frac;
|
|
}
|
|
|
|
static uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2)
|
|
{
|
|
/*
|
|
* Branchless load of u32[0], u64[0], u32[1], or u64[1].
|
|
* Load the 2nd qword iff is_q & is_2.
|
|
* Shift to the 2nd dword iff !is_q & is_2.
|
|
* For !is_q & !is_2, the upper bits of the result are garbage.
|
|
*/
|
|
return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5);
|
|
}
|
|
|
|
/*
|
|
* Note that FMLAL requires oprsz == 8 or oprsz == 16,
|
|
* as there is not yet SVE versions that might use blocking.
|
|
*/
|
|
|
|
static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst,
|
|
uint32_t desc, bool fz16)
|
|
{
|
|
intptr_t i, oprsz = simd_oprsz(desc);
|
|
int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
|
|
int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
|
|
int is_q = oprsz == 16;
|
|
uint64_t n_4, m_4;
|
|
|
|
/* Pre-load all of the f16 data, avoiding overlap issues. */
|
|
n_4 = load4_f16(vn, is_q, is_2);
|
|
m_4 = load4_f16(vm, is_q, is_2);
|
|
|
|
/* Negate all inputs for FMLSL at once. */
|
|
if (is_s) {
|
|
n_4 ^= 0x8000800080008000ull;
|
|
}
|
|
|
|
for (i = 0; i < oprsz / 4; i++) {
|
|
float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
|
|
float32 m_1 = float16_to_float32_by_bits(m_4 >> (i * 16), fz16);
|
|
d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
|
|
}
|
|
clear_tail(d, oprsz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
|
|
void *venv, uint32_t desc)
|
|
{
|
|
CPUARMState *env = venv;
|
|
do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc,
|
|
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
|
|
}
|
|
|
|
void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
|
|
void *venv, uint32_t desc)
|
|
{
|
|
CPUARMState *env = venv;
|
|
do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc,
|
|
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
|
|
}
|
|
|
|
static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst,
|
|
uint32_t desc, bool fz16)
|
|
{
|
|
intptr_t i, oprsz = simd_oprsz(desc);
|
|
int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
|
|
int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
|
|
int index = extract32(desc, SIMD_DATA_SHIFT + 2, 3);
|
|
int is_q = oprsz == 16;
|
|
uint64_t n_4;
|
|
float32 m_1;
|
|
|
|
/* Pre-load all of the f16 data, avoiding overlap issues. */
|
|
n_4 = load4_f16(vn, is_q, is_2);
|
|
|
|
/* Negate all inputs for FMLSL at once. */
|
|
if (is_s) {
|
|
n_4 ^= 0x8000800080008000ull;
|
|
}
|
|
|
|
m_1 = float16_to_float32_by_bits(((float16 *)vm)[H2(index)], fz16);
|
|
|
|
for (i = 0; i < oprsz / 4; i++) {
|
|
float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
|
|
d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
|
|
}
|
|
clear_tail(d, oprsz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
|
|
void *venv, uint32_t desc)
|
|
{
|
|
CPUARMState *env = venv;
|
|
do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc,
|
|
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
|
|
}
|
|
|
|
void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
|
|
void *venv, uint32_t desc)
|
|
{
|
|
CPUARMState *env = venv;
|
|
do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
|
|
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
|
|
}
|
|
|
|
void HELPER(gvec_sshl_b)(void *vd, void *vn, void *vm, uint32_t desc)
|
|
{
|
|
intptr_t i, opr_sz = simd_oprsz(desc);
|
|
int8_t *d = vd, *n = vn, *m = vm;
|
|
|
|
for (i = 0; i < opr_sz; ++i) {
|
|
int8_t mm = m[i];
|
|
int8_t nn = n[i];
|
|
int8_t res = 0;
|
|
if (mm >= 0) {
|
|
if (mm < 8) {
|
|
res = nn << mm;
|
|
}
|
|
} else {
|
|
res = nn >> (mm > -8 ? -mm : 7);
|
|
}
|
|
d[i] = res;
|
|
}
|
|
clear_tail(d, opr_sz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_sshl_h)(void *vd, void *vn, void *vm, uint32_t desc)
|
|
{
|
|
intptr_t i, opr_sz = simd_oprsz(desc);
|
|
int16_t *d = vd, *n = vn, *m = vm;
|
|
|
|
for (i = 0; i < opr_sz / 2; ++i) {
|
|
int8_t mm = m[i]; /* only 8 bits of shift are significant */
|
|
int16_t nn = n[i];
|
|
int16_t res = 0;
|
|
if (mm >= 0) {
|
|
if (mm < 16) {
|
|
res = nn << mm;
|
|
}
|
|
} else {
|
|
res = nn >> (mm > -16 ? -mm : 15);
|
|
}
|
|
d[i] = res;
|
|
}
|
|
clear_tail(d, opr_sz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_ushl_b)(void *vd, void *vn, void *vm, uint32_t desc)
|
|
{
|
|
intptr_t i, opr_sz = simd_oprsz(desc);
|
|
uint8_t *d = vd, *n = vn, *m = vm;
|
|
|
|
for (i = 0; i < opr_sz; ++i) {
|
|
int8_t mm = m[i];
|
|
uint8_t nn = n[i];
|
|
uint8_t res = 0;
|
|
if (mm >= 0) {
|
|
if (mm < 8) {
|
|
res = nn << mm;
|
|
}
|
|
} else {
|
|
if (mm > -8) {
|
|
res = nn >> -mm;
|
|
}
|
|
}
|
|
d[i] = res;
|
|
}
|
|
clear_tail(d, opr_sz, simd_maxsz(desc));
|
|
}
|
|
|
|
void HELPER(gvec_ushl_h)(void *vd, void *vn, void *vm, uint32_t desc)
|
|
{
|
|
intptr_t i, opr_sz = simd_oprsz(desc);
|
|
uint16_t *d = vd, *n = vn, *m = vm;
|
|
|
|
for (i = 0; i < opr_sz / 2; ++i) {
|
|
int8_t mm = m[i]; /* only 8 bits of shift are significant */
|
|
uint16_t nn = n[i];
|
|
uint16_t res = 0;
|
|
if (mm >= 0) {
|
|
if (mm < 16) {
|
|
res = nn << mm;
|
|
}
|
|
} else {
|
|
if (mm > -16) {
|
|
res = nn >> -mm;
|
|
}
|
|
}
|
|
d[i] = res;
|
|
}
|
|
clear_tail(d, opr_sz, simd_maxsz(desc));
|
|
}
|
|
|
|
/*
|
|
* 8x8->8 polynomial multiply.
|
|
*
|
|
* Polynomial multiplication is like integer multiplication except the
|
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* partial products are XORed, not added.
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*
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* TODO: expose this as a generic vector operation, as it is a common
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* crypto building block.
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*/
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void HELPER(gvec_pmul_b)(void *vd, void *vn, void *vm, uint32_t desc)
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{
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intptr_t i, j, opr_sz = simd_oprsz(desc);
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uint64_t *d = vd, *n = vn, *m = vm;
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for (i = 0; i < opr_sz / 8; ++i) {
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uint64_t nn = n[i];
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uint64_t mm = m[i];
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uint64_t rr = 0;
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for (j = 0; j < 8; ++j) {
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uint64_t mask = (nn & 0x0101010101010101ull) * 0xff;
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rr ^= mm & mask;
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mm = (mm << 1) & 0xfefefefefefefefeull;
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nn >>= 1;
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}
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d[i] = rr;
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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|
/*
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* 64x64->128 polynomial multiply.
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* Because of the lanes are not accessed in strict columns,
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* this probably cannot be turned into a generic helper.
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*/
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void HELPER(gvec_pmull_q)(void *vd, void *vn, void *vm, uint32_t desc)
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|
{
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intptr_t i, j, opr_sz = simd_oprsz(desc);
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intptr_t hi = simd_data(desc);
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uint64_t *d = vd, *n = vn, *m = vm;
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for (i = 0; i < opr_sz / 8; i += 2) {
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uint64_t nn = n[i + hi];
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uint64_t mm = m[i + hi];
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uint64_t rhi = 0;
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uint64_t rlo = 0;
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|
|
|
/* Bit 0 can only influence the low 64-bit result. */
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if (nn & 1) {
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rlo = mm;
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|
}
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|
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|
for (j = 1; j < 64; ++j) {
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uint64_t mask = -((nn >> j) & 1);
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rlo ^= (mm << j) & mask;
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rhi ^= (mm >> (64 - j)) & mask;
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}
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d[i] = rlo;
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d[i + 1] = rhi;
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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|
|
/*
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* 8x8->16 polynomial multiply.
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*
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* The byte inputs are expanded to (or extracted from) half-words.
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* Note that neon and sve2 get the inputs from different positions.
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* This allows 4 bytes to be processed in parallel with uint64_t.
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|
*/
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|
|
|
static uint64_t expand_byte_to_half(uint64_t x)
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|
{
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|
return (x & 0x000000ff)
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| ((x & 0x0000ff00) << 8)
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| ((x & 0x00ff0000) << 16)
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| ((x & 0xff000000) << 24);
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}
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|
|
|
static uint64_t pmull_h(uint64_t op1, uint64_t op2)
|
|
{
|
|
uint64_t result = 0;
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|
int i;
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|
|
|
for (i = 0; i < 8; ++i) {
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|
uint64_t mask = (op1 & 0x0001000100010001ull) * 0xffff;
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|
result ^= op2 & mask;
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|
op1 >>= 1;
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|
op2 <<= 1;
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|
}
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|
return result;
|
|
}
|
|
|
|
void HELPER(neon_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc)
|
|
{
|
|
int hi = simd_data(desc);
|
|
uint64_t *d = vd, *n = vn, *m = vm;
|
|
uint64_t nn = n[hi], mm = m[hi];
|
|
|
|
d[0] = pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm));
|
|
nn >>= 32;
|
|
mm >>= 32;
|
|
d[1] = pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm));
|
|
|
|
clear_tail(d, 16, simd_maxsz(desc));
|
|
}
|
|
|
|
#ifdef TARGET_AARCH64
|
|
void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc)
|
|
{
|
|
int shift = simd_data(desc) * 8;
|
|
intptr_t i, opr_sz = simd_oprsz(desc);
|
|
uint64_t *d = vd, *n = vn, *m = vm;
|
|
|
|
for (i = 0; i < opr_sz / 8; ++i) {
|
|
uint64_t nn = (n[i] >> shift) & 0x00ff00ff00ff00ffull;
|
|
uint64_t mm = (m[i] >> shift) & 0x00ff00ff00ff00ffull;
|
|
|
|
d[i] = pmull_h(nn, mm);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#define DO_CMP0(NAME, TYPE, OP) \
|
|
void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
|
|
{ \
|
|
intptr_t i, opr_sz = simd_oprsz(desc); \
|
|
for (i = 0; i < opr_sz; i += sizeof(TYPE)) { \
|
|
TYPE nn = *(TYPE *)(vn + i); \
|
|
*(TYPE *)(vd + i) = -(nn OP 0); \
|
|
} \
|
|
clear_tail(vd, opr_sz, simd_maxsz(desc)); \
|
|
}
|
|
|
|
DO_CMP0(gvec_ceq0_b, int8_t, ==)
|
|
DO_CMP0(gvec_clt0_b, int8_t, <)
|
|
DO_CMP0(gvec_cle0_b, int8_t, <=)
|
|
DO_CMP0(gvec_cgt0_b, int8_t, >)
|
|
DO_CMP0(gvec_cge0_b, int8_t, >=)
|
|
|
|
DO_CMP0(gvec_ceq0_h, int16_t, ==)
|
|
DO_CMP0(gvec_clt0_h, int16_t, <)
|
|
DO_CMP0(gvec_cle0_h, int16_t, <=)
|
|
DO_CMP0(gvec_cgt0_h, int16_t, >)
|
|
DO_CMP0(gvec_cge0_h, int16_t, >=)
|
|
|
|
#undef DO_CMP0
|
|
|
|
#define DO_ABD(NAME, TYPE) \
|
|
void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
|
|
{ \
|
|
intptr_t i, opr_sz = simd_oprsz(desc); \
|
|
TYPE *d = vd, *n = vn, *m = vm; \
|
|
\
|
|
for (i = 0; i < opr_sz / sizeof(TYPE); ++i) { \
|
|
d[i] = n[i] < m[i] ? m[i] - n[i] : n[i] - m[i]; \
|
|
} \
|
|
clear_tail(d, opr_sz, simd_maxsz(desc)); \
|
|
}
|
|
|
|
DO_ABD(gvec_sabd_b, int8_t)
|
|
DO_ABD(gvec_sabd_h, int16_t)
|
|
DO_ABD(gvec_sabd_s, int32_t)
|
|
DO_ABD(gvec_sabd_d, int64_t)
|
|
|
|
DO_ABD(gvec_uabd_b, uint8_t)
|
|
DO_ABD(gvec_uabd_h, uint16_t)
|
|
DO_ABD(gvec_uabd_s, uint32_t)
|
|
DO_ABD(gvec_uabd_d, uint64_t)
|
|
|
|
#undef DO_ABD
|
|
|
|
#define DO_ABA(NAME, TYPE) \
|
|
void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
|
|
{ \
|
|
intptr_t i, opr_sz = simd_oprsz(desc); \
|
|
TYPE *d = vd, *n = vn, *m = vm; \
|
|
\
|
|
for (i = 0; i < opr_sz / sizeof(TYPE); ++i) { \
|
|
d[i] += n[i] < m[i] ? m[i] - n[i] : n[i] - m[i]; \
|
|
} \
|
|
clear_tail(d, opr_sz, simd_maxsz(desc)); \
|
|
}
|
|
|
|
DO_ABA(gvec_saba_b, int8_t)
|
|
DO_ABA(gvec_saba_h, int16_t)
|
|
DO_ABA(gvec_saba_s, int32_t)
|
|
DO_ABA(gvec_saba_d, int64_t)
|
|
|
|
DO_ABA(gvec_uaba_b, uint8_t)
|
|
DO_ABA(gvec_uaba_h, uint16_t)
|
|
DO_ABA(gvec_uaba_s, uint32_t)
|
|
DO_ABA(gvec_uaba_d, uint64_t)
|
|
|
|
#undef DO_ABA
|