623 lines
21 KiB
C
623 lines
21 KiB
C
/*
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* PowerPC memory access emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "qemu/host-utils.h"
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#include "qemu/main-loop.h"
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#include "exec/helper-proto.h"
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#include "helper_regs.h"
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#include "exec/cpu_ldst.h"
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#include "tcg/tcg.h"
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#include "internal.h"
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#include "qemu/atomic128.h"
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/* #define DEBUG_OP */
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static inline bool needs_byteswap(const CPUPPCState *env)
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{
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#if defined(TARGET_WORDS_BIGENDIAN)
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return msr_le;
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#else
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return !msr_le;
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#endif
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}
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/*****************************************************************************/
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/* Memory load and stores */
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static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr,
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target_long arg)
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{
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#if defined(TARGET_PPC64)
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if (!msr_is_64bit(env, env->msr)) {
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return (uint32_t)(addr + arg);
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} else
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#endif
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{
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return addr + arg;
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}
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}
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static void *probe_contiguous(CPUPPCState *env, target_ulong addr, uint32_t nb,
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MMUAccessType access_type, int mmu_idx,
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uintptr_t raddr)
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{
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void *host1, *host2;
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uint32_t nb_pg1, nb_pg2;
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nb_pg1 = -(addr | TARGET_PAGE_MASK);
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if (likely(nb <= nb_pg1)) {
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/* The entire operation is on a single page. */
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return probe_access(env, addr, nb, access_type, mmu_idx, raddr);
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}
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/* The operation spans two pages. */
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nb_pg2 = nb - nb_pg1;
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host1 = probe_access(env, addr, nb_pg1, access_type, mmu_idx, raddr);
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addr = addr_add(env, addr, nb_pg1);
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host2 = probe_access(env, addr, nb_pg2, access_type, mmu_idx, raddr);
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/* If the two host pages are contiguous, optimize. */
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if (host2 == host1 + nb_pg1) {
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return host1;
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}
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return NULL;
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}
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void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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{
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uintptr_t raddr = GETPC();
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int mmu_idx = cpu_mmu_index(env, false);
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void *host = probe_contiguous(env, addr, (32 - reg) * 4,
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MMU_DATA_LOAD, mmu_idx, raddr);
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if (likely(host)) {
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/* Fast path -- the entire operation is in RAM at host. */
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for (; reg < 32; reg++) {
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env->gpr[reg] = (uint32_t)ldl_be_p(host);
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host += 4;
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}
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} else {
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/* Slow path -- at least some of the operation requires i/o. */
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for (; reg < 32; reg++) {
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env->gpr[reg] = cpu_ldl_mmuidx_ra(env, addr, mmu_idx, raddr);
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addr = addr_add(env, addr, 4);
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}
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}
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}
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void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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{
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uintptr_t raddr = GETPC();
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int mmu_idx = cpu_mmu_index(env, false);
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void *host = probe_contiguous(env, addr, (32 - reg) * 4,
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MMU_DATA_STORE, mmu_idx, raddr);
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if (likely(host)) {
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/* Fast path -- the entire operation is in RAM at host. */
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for (; reg < 32; reg++) {
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stl_be_p(host, env->gpr[reg]);
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host += 4;
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}
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} else {
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/* Slow path -- at least some of the operation requires i/o. */
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for (; reg < 32; reg++) {
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cpu_stl_mmuidx_ra(env, addr, env->gpr[reg], mmu_idx, raddr);
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addr = addr_add(env, addr, 4);
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}
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}
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}
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static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
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uint32_t reg, uintptr_t raddr)
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{
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int mmu_idx;
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void *host;
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uint32_t val;
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if (unlikely(nb == 0)) {
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return;
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}
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mmu_idx = cpu_mmu_index(env, false);
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host = probe_contiguous(env, addr, nb, MMU_DATA_LOAD, mmu_idx, raddr);
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if (likely(host)) {
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/* Fast path -- the entire operation is in RAM at host. */
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for (; nb > 3; nb -= 4) {
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env->gpr[reg] = (uint32_t)ldl_be_p(host);
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reg = (reg + 1) % 32;
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host += 4;
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}
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switch (nb) {
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default:
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return;
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case 1:
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val = ldub_p(host) << 24;
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break;
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case 2:
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val = lduw_be_p(host) << 16;
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break;
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case 3:
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val = (lduw_be_p(host) << 16) | (ldub_p(host + 2) << 8);
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break;
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}
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} else {
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/* Slow path -- at least some of the operation requires i/o. */
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for (; nb > 3; nb -= 4) {
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env->gpr[reg] = cpu_ldl_mmuidx_ra(env, addr, mmu_idx, raddr);
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reg = (reg + 1) % 32;
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addr = addr_add(env, addr, 4);
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}
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switch (nb) {
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default:
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return;
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case 1:
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val = cpu_ldub_mmuidx_ra(env, addr, mmu_idx, raddr) << 24;
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break;
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case 2:
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val = cpu_lduw_mmuidx_ra(env, addr, mmu_idx, raddr) << 16;
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break;
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case 3:
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val = cpu_lduw_mmuidx_ra(env, addr, mmu_idx, raddr) << 16;
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addr = addr_add(env, addr, 2);
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val |= cpu_ldub_mmuidx_ra(env, addr, mmu_idx, raddr) << 8;
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break;
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}
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}
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env->gpr[reg] = val;
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}
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void helper_lsw(CPUPPCState *env, target_ulong addr,
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uint32_t nb, uint32_t reg)
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{
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do_lsw(env, addr, nb, reg, GETPC());
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}
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/*
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* PPC32 specification says we must generate an exception if rA is in
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* the range of registers to be loaded. In an other hand, IBM says
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* this is valid, but rA won't be loaded. For now, I'll follow the
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* spec...
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*/
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void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
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uint32_t ra, uint32_t rb)
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{
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if (likely(xer_bc != 0)) {
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int num_used_regs = DIV_ROUND_UP(xer_bc, 4);
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if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) ||
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lsw_reg_in_range(reg, num_used_regs, rb))) {
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL |
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POWERPC_EXCP_INVAL_LSWX, GETPC());
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} else {
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do_lsw(env, addr, xer_bc, reg, GETPC());
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}
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}
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}
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void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
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uint32_t reg)
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{
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uintptr_t raddr = GETPC();
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int mmu_idx;
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void *host;
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uint32_t val;
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if (unlikely(nb == 0)) {
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return;
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}
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mmu_idx = cpu_mmu_index(env, false);
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host = probe_contiguous(env, addr, nb, MMU_DATA_STORE, mmu_idx, raddr);
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if (likely(host)) {
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/* Fast path -- the entire operation is in RAM at host. */
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for (; nb > 3; nb -= 4) {
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stl_be_p(host, env->gpr[reg]);
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reg = (reg + 1) % 32;
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host += 4;
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}
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val = env->gpr[reg];
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switch (nb) {
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case 1:
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stb_p(host, val >> 24);
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break;
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case 2:
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stw_be_p(host, val >> 16);
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break;
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case 3:
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stw_be_p(host, val >> 16);
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stb_p(host + 2, val >> 8);
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break;
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}
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} else {
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for (; nb > 3; nb -= 4) {
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cpu_stl_mmuidx_ra(env, addr, env->gpr[reg], mmu_idx, raddr);
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reg = (reg + 1) % 32;
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addr = addr_add(env, addr, 4);
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}
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val = env->gpr[reg];
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switch (nb) {
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case 1:
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cpu_stb_mmuidx_ra(env, addr, val >> 24, mmu_idx, raddr);
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break;
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case 2:
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cpu_stw_mmuidx_ra(env, addr, val >> 16, mmu_idx, raddr);
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break;
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case 3:
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cpu_stw_mmuidx_ra(env, addr, val >> 16, mmu_idx, raddr);
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addr = addr_add(env, addr, 2);
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cpu_stb_mmuidx_ra(env, addr, val >> 8, mmu_idx, raddr);
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break;
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}
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}
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}
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static void dcbz_common(CPUPPCState *env, target_ulong addr,
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uint32_t opcode, bool epid, uintptr_t retaddr)
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{
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target_ulong mask, dcbz_size = env->dcache_line_size;
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uint32_t i;
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void *haddr;
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int mmu_idx = epid ? PPC_TLB_EPID_STORE : env->dmmu_idx;
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#if defined(TARGET_PPC64)
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/* Check for dcbz vs dcbzl on 970 */
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if (env->excp_model == POWERPC_EXCP_970 &&
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!(opcode & 0x00200000) && ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
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dcbz_size = 32;
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}
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#endif
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/* Align address */
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mask = ~(dcbz_size - 1);
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addr &= mask;
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/* Check reservation */
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if ((env->reserve_addr & mask) == addr) {
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env->reserve_addr = (target_ulong)-1ULL;
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}
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/* Try fast path translate */
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haddr = probe_write(env, addr, dcbz_size, mmu_idx, retaddr);
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if (haddr) {
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memset(haddr, 0, dcbz_size);
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} else {
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/* Slow path */
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for (i = 0; i < dcbz_size; i += 8) {
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cpu_stq_mmuidx_ra(env, addr + i, 0, mmu_idx, retaddr);
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}
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}
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}
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void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t opcode)
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{
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dcbz_common(env, addr, opcode, false, GETPC());
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}
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void helper_dcbzep(CPUPPCState *env, target_ulong addr, uint32_t opcode)
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{
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dcbz_common(env, addr, opcode, true, GETPC());
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}
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void helper_icbi(CPUPPCState *env, target_ulong addr)
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{
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addr &= ~(env->dcache_line_size - 1);
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/*
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* Invalidate one cache line :
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* PowerPC specification says this is to be treated like a load
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* (not a fetch) by the MMU. To be sure it will be so,
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* do the load "by hand".
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*/
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cpu_ldl_data_ra(env, addr, GETPC());
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}
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void helper_icbiep(CPUPPCState *env, target_ulong addr)
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{
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#if !defined(CONFIG_USER_ONLY)
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/* See comments above */
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addr &= ~(env->dcache_line_size - 1);
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cpu_ldl_mmuidx_ra(env, addr, PPC_TLB_EPID_LOAD, GETPC());
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#endif
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}
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/* XXX: to be tested */
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target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
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uint32_t ra, uint32_t rb)
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{
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int i, c, d;
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d = 24;
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for (i = 0; i < xer_bc; i++) {
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c = cpu_ldub_data_ra(env, addr, GETPC());
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addr = addr_add(env, addr, 1);
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/* ra (if not 0) and rb are never modified */
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if (likely(reg != rb && (ra == 0 || reg != ra))) {
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env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
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}
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if (unlikely(c == xer_cmp)) {
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break;
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}
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if (likely(d != 0)) {
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d -= 8;
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} else {
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d = 24;
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reg++;
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reg = reg & 0x1F;
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}
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}
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return i;
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}
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#ifdef TARGET_PPC64
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uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr,
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uint32_t opidx)
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{
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Int128 ret;
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/* We will have raised EXCP_ATOMIC from the translator. */
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assert(HAVE_ATOMIC128);
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ret = helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC());
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env->retxh = int128_gethi(ret);
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return int128_getlo(ret);
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}
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uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr,
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uint32_t opidx)
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{
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Int128 ret;
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/* We will have raised EXCP_ATOMIC from the translator. */
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assert(HAVE_ATOMIC128);
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ret = helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC());
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env->retxh = int128_gethi(ret);
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return int128_getlo(ret);
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}
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void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr,
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uint64_t lo, uint64_t hi, uint32_t opidx)
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{
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Int128 val;
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/* We will have raised EXCP_ATOMIC from the translator. */
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assert(HAVE_ATOMIC128);
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val = int128_make128(lo, hi);
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helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC());
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}
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void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr,
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uint64_t lo, uint64_t hi, uint32_t opidx)
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{
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Int128 val;
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/* We will have raised EXCP_ATOMIC from the translator. */
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assert(HAVE_ATOMIC128);
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val = int128_make128(lo, hi);
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helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC());
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}
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uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr,
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uint64_t new_lo, uint64_t new_hi,
|
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uint32_t opidx)
|
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{
|
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bool success = false;
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/* We will have raised EXCP_ATOMIC from the translator. */
|
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assert(HAVE_CMPXCHG128);
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|
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if (likely(addr == env->reserve_addr)) {
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Int128 oldv, cmpv, newv;
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cmpv = int128_make128(env->reserve_val2, env->reserve_val);
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newv = int128_make128(new_lo, new_hi);
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oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv,
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opidx, GETPC());
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success = int128_eq(oldv, cmpv);
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}
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env->reserve_addr = -1;
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return env->so + success * CRF_EQ_BIT;
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}
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|
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uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr,
|
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uint64_t new_lo, uint64_t new_hi,
|
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uint32_t opidx)
|
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{
|
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bool success = false;
|
|
|
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/* We will have raised EXCP_ATOMIC from the translator. */
|
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assert(HAVE_CMPXCHG128);
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|
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if (likely(addr == env->reserve_addr)) {
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Int128 oldv, cmpv, newv;
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cmpv = int128_make128(env->reserve_val2, env->reserve_val);
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newv = int128_make128(new_lo, new_hi);
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oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv,
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opidx, GETPC());
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success = int128_eq(oldv, cmpv);
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}
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env->reserve_addr = -1;
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return env->so + success * CRF_EQ_BIT;
|
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}
|
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#endif
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|
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/*****************************************************************************/
|
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/* Altivec extension helpers */
|
|
#if defined(HOST_WORDS_BIGENDIAN)
|
|
#define HI_IDX 0
|
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#define LO_IDX 1
|
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#else
|
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#define HI_IDX 1
|
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#define LO_IDX 0
|
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#endif
|
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|
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/*
|
|
* We use msr_le to determine index ordering in a vector. However,
|
|
* byteswapping is not simply controlled by msr_le. We also need to
|
|
* take into account endianness of the target. This is done for the
|
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* little-endian PPC64 user-mode target.
|
|
*/
|
|
|
|
#define LVE(name, access, swap, element) \
|
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void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
|
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target_ulong addr) \
|
|
{ \
|
|
size_t n_elems = ARRAY_SIZE(r->element); \
|
|
int adjust = HI_IDX * (n_elems - 1); \
|
|
int sh = sizeof(r->element[0]) >> 1; \
|
|
int index = (addr & 0xf) >> sh; \
|
|
if (msr_le) { \
|
|
index = n_elems - index - 1; \
|
|
} \
|
|
\
|
|
if (needs_byteswap(env)) { \
|
|
r->element[LO_IDX ? index : (adjust - index)] = \
|
|
swap(access(env, addr, GETPC())); \
|
|
} else { \
|
|
r->element[LO_IDX ? index : (adjust - index)] = \
|
|
access(env, addr, GETPC()); \
|
|
} \
|
|
}
|
|
#define I(x) (x)
|
|
LVE(lvebx, cpu_ldub_data_ra, I, u8)
|
|
LVE(lvehx, cpu_lduw_data_ra, bswap16, u16)
|
|
LVE(lvewx, cpu_ldl_data_ra, bswap32, u32)
|
|
#undef I
|
|
#undef LVE
|
|
|
|
#define STVE(name, access, swap, element) \
|
|
void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
|
|
target_ulong addr) \
|
|
{ \
|
|
size_t n_elems = ARRAY_SIZE(r->element); \
|
|
int adjust = HI_IDX * (n_elems - 1); \
|
|
int sh = sizeof(r->element[0]) >> 1; \
|
|
int index = (addr & 0xf) >> sh; \
|
|
if (msr_le) { \
|
|
index = n_elems - index - 1; \
|
|
} \
|
|
\
|
|
if (needs_byteswap(env)) { \
|
|
access(env, addr, swap(r->element[LO_IDX ? index : \
|
|
(adjust - index)]), \
|
|
GETPC()); \
|
|
} else { \
|
|
access(env, addr, r->element[LO_IDX ? index : \
|
|
(adjust - index)], GETPC()); \
|
|
} \
|
|
}
|
|
#define I(x) (x)
|
|
STVE(stvebx, cpu_stb_data_ra, I, u8)
|
|
STVE(stvehx, cpu_stw_data_ra, bswap16, u16)
|
|
STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
|
|
#undef I
|
|
#undef LVE
|
|
|
|
#ifdef TARGET_PPC64
|
|
#define GET_NB(rb) ((rb >> 56) & 0xFF)
|
|
|
|
#define VSX_LXVL(name, lj) \
|
|
void helper_##name(CPUPPCState *env, target_ulong addr, \
|
|
ppc_vsr_t *xt, target_ulong rb) \
|
|
{ \
|
|
ppc_vsr_t t; \
|
|
uint64_t nb = GET_NB(rb); \
|
|
int i; \
|
|
\
|
|
t.s128 = int128_zero(); \
|
|
if (nb) { \
|
|
nb = (nb >= 16) ? 16 : nb; \
|
|
if (msr_le && !lj) { \
|
|
for (i = 16; i > 16 - nb; i--) { \
|
|
t.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC()); \
|
|
addr = addr_add(env, addr, 1); \
|
|
} \
|
|
} else { \
|
|
for (i = 0; i < nb; i++) { \
|
|
t.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC()); \
|
|
addr = addr_add(env, addr, 1); \
|
|
} \
|
|
} \
|
|
} \
|
|
*xt = t; \
|
|
}
|
|
|
|
VSX_LXVL(lxvl, 0)
|
|
VSX_LXVL(lxvll, 1)
|
|
#undef VSX_LXVL
|
|
|
|
#define VSX_STXVL(name, lj) \
|
|
void helper_##name(CPUPPCState *env, target_ulong addr, \
|
|
ppc_vsr_t *xt, target_ulong rb) \
|
|
{ \
|
|
target_ulong nb = GET_NB(rb); \
|
|
int i; \
|
|
\
|
|
if (!nb) { \
|
|
return; \
|
|
} \
|
|
\
|
|
nb = (nb >= 16) ? 16 : nb; \
|
|
if (msr_le && !lj) { \
|
|
for (i = 16; i > 16 - nb; i--) { \
|
|
cpu_stb_data_ra(env, addr, xt->VsrB(i - 1), GETPC()); \
|
|
addr = addr_add(env, addr, 1); \
|
|
} \
|
|
} else { \
|
|
for (i = 0; i < nb; i++) { \
|
|
cpu_stb_data_ra(env, addr, xt->VsrB(i), GETPC()); \
|
|
addr = addr_add(env, addr, 1); \
|
|
} \
|
|
} \
|
|
}
|
|
|
|
VSX_STXVL(stxvl, 0)
|
|
VSX_STXVL(stxvll, 1)
|
|
#undef VSX_STXVL
|
|
#undef GET_NB
|
|
#endif /* TARGET_PPC64 */
|
|
|
|
#undef HI_IDX
|
|
#undef LO_IDX
|
|
|
|
void helper_tbegin(CPUPPCState *env)
|
|
{
|
|
/*
|
|
* As a degenerate implementation, always fail tbegin. The reason
|
|
* given is "Nesting overflow". The "persistent" bit is set,
|
|
* providing a hint to the error handler to not retry. The TFIAR
|
|
* captures the address of the failure, which is this tbegin
|
|
* instruction. Instruction execution will continue with the next
|
|
* instruction in memory, which is precisely what we want.
|
|
*/
|
|
|
|
env->spr[SPR_TEXASR] =
|
|
(1ULL << TEXASR_FAILURE_PERSISTENT) |
|
|
(1ULL << TEXASR_NESTING_OVERFLOW) |
|
|
(msr_hv << TEXASR_PRIVILEGE_HV) |
|
|
(msr_pr << TEXASR_PRIVILEGE_PR) |
|
|
(1ULL << TEXASR_FAILURE_SUMMARY) |
|
|
(1ULL << TEXASR_TFIAR_EXACT);
|
|
env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr;
|
|
env->spr[SPR_TFHAR] = env->nip + 4;
|
|
env->crf[0] = 0xB; /* 0b1010 = transaction failure */
|
|
}
|