599 lines
20 KiB
C
599 lines
20 KiB
C
/*
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* PowerPC Radix MMU mulation helpers for QEMU.
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*
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* Copyright (c) 2016 Suraj Jitindar Singh, IBM Corporation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "qemu/error-report.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "exec/log.h"
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#include "mmu-radix64.h"
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#include "mmu-book3s-v3.h"
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static bool ppc_radix64_get_fully_qualified_addr(const CPUPPCState *env,
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vaddr eaddr,
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uint64_t *lpid, uint64_t *pid)
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{
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if (msr_hv) { /* MSR[HV] -> Hypervisor/bare metal */
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switch (eaddr & R_EADDR_QUADRANT) {
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case R_EADDR_QUADRANT0:
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*lpid = 0;
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*pid = env->spr[SPR_BOOKS_PID];
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break;
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case R_EADDR_QUADRANT1:
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*lpid = env->spr[SPR_LPIDR];
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*pid = env->spr[SPR_BOOKS_PID];
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break;
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case R_EADDR_QUADRANT2:
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*lpid = env->spr[SPR_LPIDR];
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*pid = 0;
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break;
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case R_EADDR_QUADRANT3:
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*lpid = 0;
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*pid = 0;
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break;
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default:
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g_assert_not_reached();
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}
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} else { /* !MSR[HV] -> Guest */
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switch (eaddr & R_EADDR_QUADRANT) {
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case R_EADDR_QUADRANT0: /* Guest application */
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*lpid = env->spr[SPR_LPIDR];
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*pid = env->spr[SPR_BOOKS_PID];
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break;
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case R_EADDR_QUADRANT1: /* Illegal */
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case R_EADDR_QUADRANT2:
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return false;
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case R_EADDR_QUADRANT3: /* Guest OS */
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*lpid = env->spr[SPR_LPIDR];
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*pid = 0; /* pid set to 0 -> addresses guest operating system */
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break;
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default:
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g_assert_not_reached();
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}
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}
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return true;
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}
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static void ppc_radix64_raise_segi(PowerPCCPU *cpu, int rwx, vaddr eaddr)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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if (rwx == 2) { /* Instruction Segment Interrupt */
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cs->exception_index = POWERPC_EXCP_ISEG;
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} else { /* Data Segment Interrupt */
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cs->exception_index = POWERPC_EXCP_DSEG;
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env->spr[SPR_DAR] = eaddr;
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}
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env->error_code = 0;
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}
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static void ppc_radix64_raise_si(PowerPCCPU *cpu, int rwx, vaddr eaddr,
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uint32_t cause)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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if (rwx == 2) { /* Instruction Storage Interrupt */
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cs->exception_index = POWERPC_EXCP_ISI;
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env->error_code = cause;
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} else { /* Data Storage Interrupt */
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cs->exception_index = POWERPC_EXCP_DSI;
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if (rwx == 1) { /* Write -> Store */
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cause |= DSISR_ISSTORE;
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}
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env->spr[SPR_DSISR] = cause;
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env->spr[SPR_DAR] = eaddr;
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env->error_code = 0;
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}
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}
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static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, int rwx, vaddr eaddr,
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hwaddr g_raddr, uint32_t cause)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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if (rwx == 2) { /* H Instruction Storage Interrupt */
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cs->exception_index = POWERPC_EXCP_HISI;
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env->spr[SPR_ASDR] = g_raddr;
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env->error_code = cause;
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} else { /* H Data Storage Interrupt */
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cs->exception_index = POWERPC_EXCP_HDSI;
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if (rwx == 1) { /* Write -> Store */
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cause |= DSISR_ISSTORE;
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}
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env->spr[SPR_HDSISR] = cause;
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env->spr[SPR_HDAR] = eaddr;
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env->spr[SPR_ASDR] = g_raddr;
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env->error_code = 0;
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}
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}
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static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte,
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int *fault_cause, int *prot,
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bool partition_scoped)
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{
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CPUPPCState *env = &cpu->env;
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const int need_prot[] = { PAGE_READ, PAGE_WRITE, PAGE_EXEC };
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/* Check Page Attributes (pte58:59) */
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if (((pte & R_PTE_ATT) == R_PTE_ATT_NI_IO) && (rwx == 2)) {
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/*
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* Radix PTE entries with the non-idempotent I/O attribute are treated
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* as guarded storage
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*/
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*fault_cause |= SRR1_NOEXEC_GUARD;
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return true;
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}
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/* Determine permissions allowed by Encoded Access Authority */
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if (!partition_scoped && (pte & R_PTE_EAA_PRIV) && msr_pr) {
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*prot = 0;
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} else if (msr_pr || (pte & R_PTE_EAA_PRIV) || partition_scoped) {
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*prot = ppc_radix64_get_prot_eaa(pte);
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} else { /* !msr_pr && !(pte & R_PTE_EAA_PRIV) && !partition_scoped */
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*prot = ppc_radix64_get_prot_eaa(pte);
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*prot &= ppc_radix64_get_prot_amr(cpu); /* Least combined permissions */
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}
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/* Check if requested access type is allowed */
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if (need_prot[rwx] & ~(*prot)) { /* Page Protected for that Access */
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*fault_cause |= DSISR_PROTFAULT;
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return true;
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}
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return false;
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}
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static void ppc_radix64_set_rc(PowerPCCPU *cpu, int rwx, uint64_t pte,
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hwaddr pte_addr, int *prot)
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{
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CPUState *cs = CPU(cpu);
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uint64_t npte;
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npte = pte | R_PTE_R; /* Always set reference bit */
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if (rwx == 1) { /* Store/Write */
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npte |= R_PTE_C; /* Set change bit */
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} else {
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/*
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* Treat the page as read-only for now, so that a later write
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* will pass through this function again to set the C bit.
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*/
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*prot &= ~PAGE_WRITE;
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}
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if (pte ^ npte) { /* If pte has changed then write it back */
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stq_phys(cs->as, pte_addr, npte);
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}
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}
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static int ppc_radix64_next_level(AddressSpace *as, vaddr eaddr,
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uint64_t *pte_addr, uint64_t *nls,
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int *psize, uint64_t *pte, int *fault_cause)
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{
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uint64_t index, pde;
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if (*nls < 5) { /* Directory maps less than 2**5 entries */
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*fault_cause |= DSISR_R_BADCONFIG;
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return 1;
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}
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/* Read page <directory/table> entry from guest address space */
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pde = ldq_phys(as, *pte_addr);
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if (!(pde & R_PTE_VALID)) { /* Invalid Entry */
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*fault_cause |= DSISR_NOPTE;
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return 1;
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}
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*pte = pde;
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*psize -= *nls;
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if (!(pde & R_PTE_LEAF)) { /* Prepare for next iteration */
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*nls = pde & R_PDE_NLS;
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index = eaddr >> (*psize - *nls); /* Shift */
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index &= ((1UL << *nls) - 1); /* Mask */
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*pte_addr = (pde & R_PDE_NLB) + (index * sizeof(pde));
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}
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return 0;
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}
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static int ppc_radix64_walk_tree(AddressSpace *as, vaddr eaddr,
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uint64_t base_addr, uint64_t nls,
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hwaddr *raddr, int *psize, uint64_t *pte,
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int *fault_cause, hwaddr *pte_addr)
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{
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uint64_t index, pde, rpn , mask;
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if (nls < 5) { /* Directory maps less than 2**5 entries */
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*fault_cause |= DSISR_R_BADCONFIG;
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return 1;
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}
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index = eaddr >> (*psize - nls); /* Shift */
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index &= ((1UL << nls) - 1); /* Mask */
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*pte_addr = base_addr + (index * sizeof(pde));
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do {
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int ret;
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ret = ppc_radix64_next_level(as, eaddr, pte_addr, &nls, psize, &pde,
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fault_cause);
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if (ret) {
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return ret;
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}
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} while (!(pde & R_PTE_LEAF));
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*pte = pde;
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rpn = pde & R_PTE_RPN;
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mask = (1UL << *psize) - 1;
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/* Or high bits of rpn and low bits to ea to form whole real addr */
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*raddr = (rpn & ~mask) | (eaddr & mask);
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return 0;
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}
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static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate)
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{
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CPUPPCState *env = &cpu->env;
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if (!(pate->dw0 & PATE0_HR)) {
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return false;
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}
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if (lpid == 0 && !msr_hv) {
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return false;
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}
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if ((pate->dw0 & PATE1_R_PRTS) < 5) {
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return false;
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}
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/* More checks ... */
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return true;
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}
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static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, int rwx,
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vaddr eaddr, hwaddr g_raddr,
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ppc_v3_pate_t pate,
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hwaddr *h_raddr, int *h_prot,
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int *h_page_size, bool pde_addr,
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bool guest_visible)
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{
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int fault_cause = 0;
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hwaddr pte_addr;
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uint64_t pte;
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*h_page_size = PRTBE_R_GET_RTS(pate.dw0);
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/* No valid pte or access denied due to protection */
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if (ppc_radix64_walk_tree(CPU(cpu)->as, g_raddr, pate.dw0 & PRTBE_R_RPDB,
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pate.dw0 & PRTBE_R_RPDS, h_raddr, h_page_size,
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&pte, &fault_cause, &pte_addr) ||
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ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, h_prot, true)) {
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if (pde_addr) { /* address being translated was that of a guest pde */
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fault_cause |= DSISR_PRTABLE_FAULT;
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}
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if (guest_visible) {
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ppc_radix64_raise_hsi(cpu, rwx, eaddr, g_raddr, fault_cause);
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}
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return 1;
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}
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if (guest_visible) {
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ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, h_prot);
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}
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return 0;
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}
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static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
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vaddr eaddr, uint64_t pid,
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ppc_v3_pate_t pate, hwaddr *g_raddr,
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int *g_prot, int *g_page_size,
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bool guest_visible)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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uint64_t offset, size, prtbe_addr, prtbe0, base_addr, nls, index, pte;
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int fault_cause = 0, h_page_size, h_prot;
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hwaddr h_raddr, pte_addr;
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int ret;
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/* Index Process Table by PID to Find Corresponding Process Table Entry */
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offset = pid * sizeof(struct prtb_entry);
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size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
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if (offset >= size) {
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/* offset exceeds size of the process table */
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if (guest_visible) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
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}
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return 1;
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}
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prtbe_addr = (pate.dw1 & PATE1_R_PRTB) + offset;
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if (cpu->vhyp) {
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prtbe0 = ldq_phys(cs->as, prtbe_addr);
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} else {
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/*
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* Process table addresses are subject to partition-scoped
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* translation
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*
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* On a Radix host, the partition-scoped page table for LPID=0
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* is only used to translate the effective addresses of the
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* process table entries.
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*/
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ret = ppc_radix64_partition_scoped_xlate(cpu, 0, eaddr, prtbe_addr,
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pate, &h_raddr, &h_prot,
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&h_page_size, true,
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guest_visible);
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if (ret) {
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return ret;
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}
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prtbe0 = ldq_phys(cs->as, h_raddr);
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}
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/* Walk Radix Tree from Process Table Entry to Convert EA to RA */
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*g_page_size = PRTBE_R_GET_RTS(prtbe0);
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base_addr = prtbe0 & PRTBE_R_RPDB;
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nls = prtbe0 & PRTBE_R_RPDS;
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if (msr_hv || cpu->vhyp) {
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/*
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* Can treat process table addresses as real addresses
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*/
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ret = ppc_radix64_walk_tree(cs->as, eaddr & R_EADDR_MASK, base_addr,
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nls, g_raddr, g_page_size, &pte,
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&fault_cause, &pte_addr);
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if (ret) {
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/* No valid PTE */
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if (guest_visible) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
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}
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return ret;
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}
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} else {
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uint64_t rpn, mask;
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index = (eaddr & R_EADDR_MASK) >> (*g_page_size - nls); /* Shift */
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index &= ((1UL << nls) - 1); /* Mask */
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pte_addr = base_addr + (index * sizeof(pte));
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/*
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* Each process table address is subject to a partition-scoped
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* translation
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*/
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do {
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ret = ppc_radix64_partition_scoped_xlate(cpu, 0, eaddr, pte_addr,
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pate, &h_raddr, &h_prot,
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&h_page_size, true,
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guest_visible);
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if (ret) {
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return ret;
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}
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ret = ppc_radix64_next_level(cs->as, eaddr & R_EADDR_MASK, &h_raddr,
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&nls, g_page_size, &pte, &fault_cause);
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if (ret) {
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/* No valid pte */
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if (guest_visible) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
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}
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return ret;
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}
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pte_addr = h_raddr;
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} while (!(pte & R_PTE_LEAF));
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rpn = pte & R_PTE_RPN;
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mask = (1UL << *g_page_size) - 1;
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/* Or high bits of rpn and low bits to ea to form whole real addr */
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*g_raddr = (rpn & ~mask) | (eaddr & mask);
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}
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if (ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, g_prot, false)) {
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/* Access denied due to protection */
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if (guest_visible) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
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}
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return 1;
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}
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if (guest_visible) {
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ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, g_prot);
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}
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return 0;
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}
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/*
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* Radix tree translation is a 2 steps translation process:
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*
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* 1. Process-scoped translation: Guest Eff Addr -> Guest Real Addr
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* 2. Partition-scoped translation: Guest Real Addr -> Host Real Addr
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*
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* MSR[HV]
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* +-------------+----------------+---------------+
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* | | HV = 0 | HV = 1 |
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* +-------------+----------------+---------------+
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* | Relocation | Partition | No |
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* | = Off | Scoped | Translation |
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* Relocation +-------------+----------------+---------------+
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* | Relocation | Partition & | Process |
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* | = On | Process Scoped | Scoped |
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* +-------------+----------------+---------------+
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*/
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static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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bool relocation,
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hwaddr *raddr, int *psizep, int *protp,
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bool guest_visible)
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{
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CPUPPCState *env = &cpu->env;
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uint64_t lpid, pid;
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ppc_v3_pate_t pate;
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int psize, prot;
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hwaddr g_raddr;
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/* Virtual Mode Access - get the fully qualified address */
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if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pid)) {
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if (guest_visible) {
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ppc_radix64_raise_segi(cpu, rwx, eaddr);
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}
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return 1;
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}
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/* Get Process Table */
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if (cpu->vhyp) {
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PPCVirtualHypervisorClass *vhc;
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vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
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vhc->get_pate(cpu->vhyp, &pate);
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} else {
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if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
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if (guest_visible) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
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}
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return 1;
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}
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if (!validate_pate(cpu, lpid, &pate)) {
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if (guest_visible) {
|
|
ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_R_BADCONFIG);
|
|
}
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
*psizep = INT_MAX;
|
|
*protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
|
|
|
/*
|
|
* Perform process-scoped translation if relocation enabled.
|
|
*
|
|
* - Translates an effective address to a host real address in
|
|
* quadrants 0 and 3 when HV=1.
|
|
*
|
|
* - Translates an effective address to a guest real address.
|
|
*/
|
|
if (relocation) {
|
|
int ret = ppc_radix64_process_scoped_xlate(cpu, rwx, eaddr, pid,
|
|
pate, &g_raddr, &prot,
|
|
&psize, guest_visible);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
*psizep = MIN(*psizep, psize);
|
|
*protp &= prot;
|
|
} else {
|
|
g_raddr = eaddr & R_EADDR_MASK;
|
|
}
|
|
|
|
if (cpu->vhyp) {
|
|
*raddr = g_raddr;
|
|
} else {
|
|
/*
|
|
* Perform partition-scoped translation if !HV or HV access to
|
|
* quadrants 1 or 2. Translates a guest real address to a host
|
|
* real address.
|
|
*/
|
|
if (lpid || !msr_hv) {
|
|
int ret;
|
|
|
|
ret = ppc_radix64_partition_scoped_xlate(cpu, rwx, eaddr, g_raddr,
|
|
pate, raddr, &prot, &psize,
|
|
false, guest_visible);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
*psizep = MIN(*psizep, psize);
|
|
*protp &= prot;
|
|
} else {
|
|
*raddr = g_raddr;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
|
|
int mmu_idx)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
CPUPPCState *env = &cpu->env;
|
|
int page_size, prot;
|
|
bool relocation;
|
|
hwaddr raddr;
|
|
|
|
assert(!(msr_hv && cpu->vhyp));
|
|
assert((rwx == 0) || (rwx == 1) || (rwx == 2));
|
|
|
|
relocation = ((rwx == 2) && (msr_ir == 1)) || ((rwx != 2) && (msr_dr == 1));
|
|
/* HV or virtual hypervisor Real Mode Access */
|
|
if (!relocation && (msr_hv || cpu->vhyp)) {
|
|
/* In real mode top 4 effective addr bits (mostly) ignored */
|
|
raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
|
|
|
|
/* In HV mode, add HRMOR if top EA bit is clear */
|
|
if (msr_hv || !env->has_hv_mode) {
|
|
if (!(eaddr >> 63)) {
|
|
raddr |= env->spr[SPR_HRMOR];
|
|
}
|
|
}
|
|
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
|
|
PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
|
|
TARGET_PAGE_SIZE);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Check UPRT (we avoid the check in real mode to deal with
|
|
* transitional states during kexec.
|
|
*/
|
|
if (!ppc64_use_proc_tbl(cpu)) {
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"LPCR:UPRT not set in radix mode ! LPCR="
|
|
TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
|
|
}
|
|
|
|
/* Translate eaddr to raddr (where raddr is addr qemu needs for access) */
|
|
if (ppc_radix64_xlate(cpu, eaddr, rwx, relocation, &raddr,
|
|
&page_size, &prot, true)) {
|
|
return 1;
|
|
}
|
|
|
|
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
|
|
prot, mmu_idx, 1UL << page_size);
|
|
return 0;
|
|
}
|
|
|
|
hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
|
|
{
|
|
CPUPPCState *env = &cpu->env;
|
|
int psize, prot;
|
|
hwaddr raddr;
|
|
|
|
/* Handle Real Mode */
|
|
if ((msr_dr == 0) && (msr_hv || cpu->vhyp)) {
|
|
/* In real mode top 4 effective addr bits (mostly) ignored */
|
|
return eaddr & 0x0FFFFFFFFFFFFFFFULL;
|
|
}
|
|
|
|
if (ppc_radix64_xlate(cpu, eaddr, 0, msr_dr, &raddr, &psize,
|
|
&prot, false)) {
|
|
return -1;
|
|
}
|
|
|
|
return raddr & TARGET_PAGE_MASK;
|
|
}
|