163 lines
5.3 KiB
C
163 lines
5.3 KiB
C
/*
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* TILE-Gx virtual CPU header
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*
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* Copyright (c) 2015 Chen Gang
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TILEGX_CPU_H
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#define TILEGX_CPU_H
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#include "exec/cpu-defs.h"
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/* TILE-Gx common register alias */
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#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
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#define TILEGX_R_ERR 1 /* 1 register, for syscall errno flag */
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#define TILEGX_R_NR 10 /* 10 register, for syscall number */
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#define TILEGX_R_BP 52 /* 52 register, optional frame pointer */
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#define TILEGX_R_TP 53 /* TP register, thread local storage data */
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#define TILEGX_R_SP 54 /* SP register, stack pointer */
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#define TILEGX_R_LR 55 /* LR register, may save pc, but it is not pc */
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#define TILEGX_R_COUNT 56 /* Only 56 registers are really useful */
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#define TILEGX_R_SN 56 /* SN register, obsoleted, it likes zero register */
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#define TILEGX_R_IDN0 57 /* IDN0 register, cause IDN_ACCESS exception */
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#define TILEGX_R_IDN1 58 /* IDN1 register, cause IDN_ACCESS exception */
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#define TILEGX_R_UDN0 59 /* UDN0 register, cause UDN_ACCESS exception */
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#define TILEGX_R_UDN1 60 /* UDN1 register, cause UDN_ACCESS exception */
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#define TILEGX_R_UDN2 61 /* UDN2 register, cause UDN_ACCESS exception */
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#define TILEGX_R_UDN3 62 /* UDN3 register, cause UDN_ACCESS exception */
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#define TILEGX_R_ZERO 63 /* Zero register, always zero */
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#define TILEGX_R_NOREG 255 /* Invalid register value */
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/* TILE-Gx special registers used by outside */
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enum {
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TILEGX_SPR_CMPEXCH = 0,
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TILEGX_SPR_CRITICAL_SEC = 1,
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TILEGX_SPR_SIM_CONTROL = 2,
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TILEGX_SPR_EX_CONTEXT_0_0 = 3,
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TILEGX_SPR_EX_CONTEXT_0_1 = 4,
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TILEGX_SPR_COUNT
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};
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/* Exception numbers */
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typedef enum {
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TILEGX_EXCP_NONE = 0,
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TILEGX_EXCP_SYSCALL = 1,
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TILEGX_EXCP_SIGNAL = 2,
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TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
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TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
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TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
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TILEGX_EXCP_OPCODE_CMPEXCH4 = 0x104,
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TILEGX_EXCP_OPCODE_EXCH = 0x105,
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TILEGX_EXCP_OPCODE_EXCH4 = 0x106,
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TILEGX_EXCP_OPCODE_FETCHADD = 0x107,
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TILEGX_EXCP_OPCODE_FETCHADD4 = 0x108,
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TILEGX_EXCP_OPCODE_FETCHADDGEZ = 0x109,
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TILEGX_EXCP_OPCODE_FETCHADDGEZ4 = 0x10a,
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TILEGX_EXCP_OPCODE_FETCHAND = 0x10b,
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TILEGX_EXCP_OPCODE_FETCHAND4 = 0x10c,
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TILEGX_EXCP_OPCODE_FETCHOR = 0x10d,
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TILEGX_EXCP_OPCODE_FETCHOR4 = 0x10e,
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TILEGX_EXCP_REG_IDN_ACCESS = 0x181,
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TILEGX_EXCP_REG_UDN_ACCESS = 0x182,
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TILEGX_EXCP_UNALIGNMENT = 0x201,
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TILEGX_EXCP_DBUG_BREAK = 0x301
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} TileExcp;
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typedef struct CPUTLGState {
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uint64_t regs[TILEGX_R_COUNT]; /* Common used registers by outside */
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uint64_t spregs[TILEGX_SPR_COUNT]; /* Special used registers by outside */
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uint64_t pc; /* Current pc */
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#if defined(CONFIG_USER_ONLY)
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uint64_t excaddr; /* exception address */
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uint64_t atomic_srca; /* Arguments to atomic "exceptions" */
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uint64_t atomic_srcb;
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uint32_t atomic_dstr;
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uint32_t signo; /* Signal number */
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uint32_t sigcode; /* Signal code */
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#endif
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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} CPUTLGState;
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#include "hw/core/cpu.h"
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#define TYPE_TILEGX_CPU "tilegx-cpu"
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#define TILEGX_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(TileGXCPUClass, (klass), TYPE_TILEGX_CPU)
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#define TILEGX_CPU(obj) \
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OBJECT_CHECK(TileGXCPU, (obj), TYPE_TILEGX_CPU)
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#define TILEGX_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(TileGXCPUClass, (obj), TYPE_TILEGX_CPU)
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/**
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* TileGXCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* A Tile-Gx CPU model.
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*/
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typedef struct TileGXCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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DeviceReset parent_reset;
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} TileGXCPUClass;
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/**
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* TileGXCPU:
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* @env: #CPUTLGState
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*
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* A Tile-GX CPU.
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*/
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typedef struct TileGXCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPUTLGState env;
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} TileGXCPU;
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/* TILE-Gx memory attributes */
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#define MMU_USER_IDX 0 /* Current memory operation is in user mode */
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typedef CPUTLGState CPUArchState;
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typedef TileGXCPU ArchCPU;
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#include "exec/cpu-all.h"
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void tilegx_tcg_init(void);
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int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
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#define CPU_RESOLVING_TYPE TYPE_TILEGX_CPU
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#define cpu_signal_handler cpu_tilegx_signal_handler
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static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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*pc = env->pc;
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*cs_base = 0;
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*flags = 0;
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}
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#endif
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