1066 lines
30 KiB
C
1066 lines
30 KiB
C
/*
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* IDE test cases
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*
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* Copyright (c) 2013 Kevin Wolf <kwolf@redhat.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#include "libqos/libqos.h"
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#include "libqos/pci-pc.h"
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#include "libqos/malloc-pc.h"
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#include "qapi/qmp/qdict.h"
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#include "qemu-common.h"
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#include "qemu/bswap.h"
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#include "hw/pci/pci_ids.h"
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#include "hw/pci/pci_regs.h"
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/* TODO actually test the results and get rid of this */
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#define qmp_discard_response(q, ...) qobject_unref(qtest_qmp(q, __VA_ARGS__))
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#define TEST_IMAGE_SIZE 64 * 1024 * 1024
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#define IDE_PCI_DEV 1
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#define IDE_PCI_FUNC 1
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#define IDE_BASE 0x1f0
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#define IDE_PRIMARY_IRQ 14
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#define ATAPI_BLOCK_SIZE 2048
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/* How many bytes to receive via ATAPI PIO at one time.
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* Must be less than 0xFFFF. */
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#define BYTE_COUNT_LIMIT 5120
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enum {
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reg_data = 0x0,
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reg_feature = 0x1,
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reg_error = 0x1,
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reg_nsectors = 0x2,
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reg_lba_low = 0x3,
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reg_lba_middle = 0x4,
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reg_lba_high = 0x5,
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reg_device = 0x6,
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reg_status = 0x7,
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reg_command = 0x7,
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};
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enum {
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BSY = 0x80,
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DRDY = 0x40,
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DF = 0x20,
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DRQ = 0x08,
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ERR = 0x01,
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};
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/* Error field */
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enum {
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ABRT = 0x04,
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};
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enum {
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DEV = 0x10,
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LBA = 0x40,
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};
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enum {
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bmreg_cmd = 0x0,
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bmreg_status = 0x2,
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bmreg_prdt = 0x4,
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};
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enum {
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CMD_DSM = 0x06,
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CMD_READ_DMA = 0xc8,
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CMD_WRITE_DMA = 0xca,
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CMD_FLUSH_CACHE = 0xe7,
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CMD_IDENTIFY = 0xec,
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CMD_PACKET = 0xa0,
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CMDF_ABORT = 0x100,
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CMDF_NO_BM = 0x200,
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};
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enum {
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BM_CMD_START = 0x1,
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BM_CMD_WRITE = 0x8, /* write = from device to memory */
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};
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enum {
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BM_STS_ACTIVE = 0x1,
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BM_STS_ERROR = 0x2,
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BM_STS_INTR = 0x4,
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};
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enum {
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PRDT_EOT = 0x80000000,
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};
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#define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
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#define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
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static QPCIBus *pcibus = NULL;
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static QGuestAllocator guest_malloc;
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static char tmp_path[] = "/tmp/qtest.XXXXXX";
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static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX";
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static QTestState *ide_test_start(const char *cmdline_fmt, ...)
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{
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QTestState *qts;
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va_list ap;
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va_start(ap, cmdline_fmt);
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qts = qtest_vinitf(cmdline_fmt, ap);
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va_end(ap);
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pc_alloc_init(&guest_malloc, qts, 0);
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return qts;
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}
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static void ide_test_quit(QTestState *qts)
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{
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if (pcibus) {
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qpci_free_pc(pcibus);
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pcibus = NULL;
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}
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alloc_destroy(&guest_malloc);
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qtest_quit(qts);
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}
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static QPCIDevice *get_pci_device(QTestState *qts, QPCIBar *bmdma_bar,
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QPCIBar *ide_bar)
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{
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QPCIDevice *dev;
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uint16_t vendor_id, device_id;
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if (!pcibus) {
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pcibus = qpci_new_pc(qts, NULL);
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}
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/* Find PCI device and verify it's the right one */
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dev = qpci_device_find(pcibus, QPCI_DEVFN(IDE_PCI_DEV, IDE_PCI_FUNC));
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g_assert(dev != NULL);
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vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID);
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device_id = qpci_config_readw(dev, PCI_DEVICE_ID);
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g_assert(vendor_id == PCI_VENDOR_ID_INTEL);
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g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1);
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/* Map bmdma BAR */
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*bmdma_bar = qpci_iomap(dev, 4, NULL);
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*ide_bar = qpci_legacy_iomap(dev, IDE_BASE);
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qpci_device_enable(dev);
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return dev;
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}
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static void free_pci_device(QPCIDevice *dev)
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{
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/* libqos doesn't have a function for this, so free it manually */
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g_free(dev);
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}
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typedef struct PrdtEntry {
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uint32_t addr;
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uint32_t size;
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} QEMU_PACKED PrdtEntry;
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#define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
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#define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
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static uint64_t trim_range_le(uint64_t sector, uint16_t count)
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{
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/* 2-byte range, 6-byte LBA */
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return cpu_to_le64(((uint64_t)count << 48) + sector);
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}
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static int send_dma_request(QTestState *qts, int cmd, uint64_t sector,
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int nb_sectors, PrdtEntry *prdt, int prdt_entries,
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void(*post_exec)(QPCIDevice *dev, QPCIBar ide_bar,
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uint64_t sector, int nb_sectors))
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{
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QPCIDevice *dev;
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QPCIBar bmdma_bar, ide_bar;
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uintptr_t guest_prdt;
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size_t len;
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bool from_dev;
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uint8_t status;
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int flags;
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dev = get_pci_device(qts, &bmdma_bar, &ide_bar);
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flags = cmd & ~0xff;
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cmd &= 0xff;
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switch (cmd) {
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case CMD_READ_DMA:
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case CMD_PACKET:
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/* Assuming we only test data reads w/ ATAPI, otherwise we need to know
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* the SCSI command being sent in the packet, too. */
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from_dev = true;
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break;
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case CMD_DSM:
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case CMD_WRITE_DMA:
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from_dev = false;
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break;
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default:
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g_assert_not_reached();
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}
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if (flags & CMDF_NO_BM) {
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qpci_config_writew(dev, PCI_COMMAND,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
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}
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/* Select device 0 */
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qpci_io_writeb(dev, ide_bar, reg_device, 0 | LBA);
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/* Stop any running transfer, clear any pending interrupt */
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qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0);
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qpci_io_writeb(dev, bmdma_bar, bmreg_status, BM_STS_INTR);
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/* Setup PRDT */
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len = sizeof(*prdt) * prdt_entries;
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guest_prdt = guest_alloc(&guest_malloc, len);
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qtest_memwrite(qts, guest_prdt, prdt, len);
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qpci_io_writel(dev, bmdma_bar, bmreg_prdt, guest_prdt);
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/* ATA DMA command */
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if (cmd == CMD_PACKET) {
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/* Enables ATAPI DMA; otherwise PIO is attempted */
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qpci_io_writeb(dev, ide_bar, reg_feature, 0x01);
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} else {
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if (cmd == CMD_DSM) {
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/* trim bit */
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qpci_io_writeb(dev, ide_bar, reg_feature, 0x01);
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}
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qpci_io_writeb(dev, ide_bar, reg_nsectors, nb_sectors);
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qpci_io_writeb(dev, ide_bar, reg_lba_low, sector & 0xff);
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qpci_io_writeb(dev, ide_bar, reg_lba_middle, (sector >> 8) & 0xff);
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qpci_io_writeb(dev, ide_bar, reg_lba_high, (sector >> 16) & 0xff);
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}
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qpci_io_writeb(dev, ide_bar, reg_command, cmd);
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if (post_exec) {
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post_exec(dev, ide_bar, sector, nb_sectors);
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}
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/* Start DMA transfer */
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qpci_io_writeb(dev, bmdma_bar, bmreg_cmd,
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BM_CMD_START | (from_dev ? BM_CMD_WRITE : 0));
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if (flags & CMDF_ABORT) {
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qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0);
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}
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/* Wait for the DMA transfer to complete */
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do {
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status = qpci_io_readb(dev, bmdma_bar, bmreg_status);
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} while ((status & (BM_STS_ACTIVE | BM_STS_INTR)) == BM_STS_ACTIVE);
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g_assert_cmpint(qtest_get_irq(qts, IDE_PRIMARY_IRQ), ==,
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!!(status & BM_STS_INTR));
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/* Check IDE status code */
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assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), DRDY);
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assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), BSY | DRQ);
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/* Reading the status register clears the IRQ */
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g_assert(!qtest_get_irq(qts, IDE_PRIMARY_IRQ));
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/* Stop DMA transfer if still active */
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if (status & BM_STS_ACTIVE) {
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qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0);
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}
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free_pci_device(dev);
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return status;
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}
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static QTestState *test_bmdma_setup(void)
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{
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QTestState *qts;
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qts = ide_test_start(
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"-drive file=%s,if=ide,cache=writeback,format=raw "
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"-global ide-hd.serial=%s -global ide-hd.ver=%s",
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tmp_path, "testdisk", "version");
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qtest_irq_intercept_in(qts, "ioapic");
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return qts;
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}
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static void test_bmdma_teardown(QTestState *qts)
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{
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ide_test_quit(qts);
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}
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static void test_bmdma_simple_rw(void)
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{
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QTestState *qts;
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QPCIDevice *dev;
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QPCIBar bmdma_bar, ide_bar;
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uint8_t status;
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uint8_t *buf;
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uint8_t *cmpbuf;
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size_t len = 512;
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uintptr_t guest_buf;
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PrdtEntry prdt[1];
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qts = test_bmdma_setup();
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guest_buf = guest_alloc(&guest_malloc, len);
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prdt[0].addr = cpu_to_le32(guest_buf);
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prdt[0].size = cpu_to_le32(len | PRDT_EOT);
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dev = get_pci_device(qts, &bmdma_bar, &ide_bar);
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buf = g_malloc(len);
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cmpbuf = g_malloc(len);
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/* Write 0x55 pattern to sector 0 */
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memset(buf, 0x55, len);
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qtest_memwrite(qts, guest_buf, buf, len);
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status = send_dma_request(qts, CMD_WRITE_DMA, 0, 1, prdt,
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ARRAY_SIZE(prdt), NULL);
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g_assert_cmphex(status, ==, BM_STS_INTR);
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assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
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/* Write 0xaa pattern to sector 1 */
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memset(buf, 0xaa, len);
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qtest_memwrite(qts, guest_buf, buf, len);
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status = send_dma_request(qts, CMD_WRITE_DMA, 1, 1, prdt,
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ARRAY_SIZE(prdt), NULL);
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g_assert_cmphex(status, ==, BM_STS_INTR);
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assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
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/* Read and verify 0x55 pattern in sector 0 */
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memset(cmpbuf, 0x55, len);
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status = send_dma_request(qts, CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt),
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NULL);
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g_assert_cmphex(status, ==, BM_STS_INTR);
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assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
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qtest_memread(qts, guest_buf, buf, len);
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g_assert(memcmp(buf, cmpbuf, len) == 0);
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/* Read and verify 0xaa pattern in sector 1 */
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memset(cmpbuf, 0xaa, len);
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status = send_dma_request(qts, CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt),
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NULL);
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g_assert_cmphex(status, ==, BM_STS_INTR);
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assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
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qtest_memread(qts, guest_buf, buf, len);
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g_assert(memcmp(buf, cmpbuf, len) == 0);
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free_pci_device(dev);
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g_free(buf);
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g_free(cmpbuf);
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test_bmdma_teardown(qts);
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}
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static void test_bmdma_trim(void)
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{
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QTestState *qts;
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QPCIDevice *dev;
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QPCIBar bmdma_bar, ide_bar;
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uint8_t status;
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const uint64_t trim_range[] = { trim_range_le(0, 2),
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trim_range_le(6, 8),
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trim_range_le(10, 1),
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};
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const uint64_t bad_range = trim_range_le(TEST_IMAGE_SIZE / 512 - 1, 2);
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size_t len = 512;
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uint8_t *buf;
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uintptr_t guest_buf;
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PrdtEntry prdt[1];
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qts = test_bmdma_setup();
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guest_buf = guest_alloc(&guest_malloc, len);
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prdt[0].addr = cpu_to_le32(guest_buf),
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prdt[0].size = cpu_to_le32(len | PRDT_EOT),
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dev = get_pci_device(qts, &bmdma_bar, &ide_bar);
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buf = g_malloc(len);
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/* Normal request */
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*((uint64_t *)buf) = trim_range[0];
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*((uint64_t *)buf + 1) = trim_range[1];
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qtest_memwrite(qts, guest_buf, buf, 2 * sizeof(uint64_t));
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status = send_dma_request(qts, CMD_DSM, 0, 1, prdt,
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ARRAY_SIZE(prdt), NULL);
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g_assert_cmphex(status, ==, BM_STS_INTR);
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assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
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/* Request contains invalid range */
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*((uint64_t *)buf) = trim_range[2];
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*((uint64_t *)buf + 1) = bad_range;
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qtest_memwrite(qts, guest_buf, buf, 2 * sizeof(uint64_t));
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status = send_dma_request(qts, CMD_DSM, 0, 1, prdt,
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ARRAY_SIZE(prdt), NULL);
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g_assert_cmphex(status, ==, BM_STS_INTR);
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assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), ERR);
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assert_bit_set(qpci_io_readb(dev, ide_bar, reg_error), ABRT);
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free_pci_device(dev);
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g_free(buf);
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test_bmdma_teardown(qts);
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}
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/*
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* This test is developed according to the Programming Interface for
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* Bus Master IDE Controller (Revision 1.0 5/16/94)
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*/
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static void test_bmdma_various_prdts(void)
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{
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int sectors = 0;
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uint32_t size = 0;
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for (sectors = 1; sectors <= 256; sectors *= 2) {
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QTestState *qts = NULL;
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QPCIDevice *dev = NULL;
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QPCIBar bmdma_bar, ide_bar;
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qts = test_bmdma_setup();
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dev = get_pci_device(qts, &bmdma_bar, &ide_bar);
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for (size = 0; size < 65536; size += 256) {
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uint32_t req_size = sectors * 512;
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uint32_t prd_size = size & 0xfffe; /* bit 0 is always set to 0 */
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uint8_t ret = 0;
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uint8_t req_status = 0;
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uint8_t abort_req_status = 0;
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PrdtEntry prdt[] = {
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{
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.addr = 0,
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.size = cpu_to_le32(size | PRDT_EOT),
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},
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};
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/* A value of zero in PRD size indicates 64K */
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if (prd_size == 0) {
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prd_size = 65536;
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}
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/*
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* 1. If PRDs specified a smaller size than the IDE transfer
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* size, then the Interrupt and Active bits in the Controller
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* status register are not set (Error Condition).
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*
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* 2. If the size of the physical memory regions was equal to
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* the IDE device transfer size, the Interrupt bit in the
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* Controller status register is set to 1, Active bit is set to 0.
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*
|
|
* 3. If PRDs specified a larger size than the IDE transfer size,
|
|
* the Interrupt and Active bits in the Controller status register
|
|
* are both set to 1.
|
|
*/
|
|
if (prd_size < req_size) {
|
|
req_status = 0;
|
|
abort_req_status = 0;
|
|
} else if (prd_size == req_size) {
|
|
req_status = BM_STS_INTR;
|
|
abort_req_status = BM_STS_INTR;
|
|
} else {
|
|
req_status = BM_STS_ACTIVE | BM_STS_INTR;
|
|
abort_req_status = BM_STS_INTR;
|
|
}
|
|
|
|
/* Test the request */
|
|
ret = send_dma_request(qts, CMD_READ_DMA, 0, sectors,
|
|
prdt, ARRAY_SIZE(prdt), NULL);
|
|
g_assert_cmphex(ret, ==, req_status);
|
|
assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
|
|
|
|
/* Now test aborting the same request */
|
|
ret = send_dma_request(qts, CMD_READ_DMA | CMDF_ABORT, 0,
|
|
sectors, prdt, ARRAY_SIZE(prdt), NULL);
|
|
g_assert_cmphex(ret, ==, abort_req_status);
|
|
assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
|
|
}
|
|
|
|
free_pci_device(dev);
|
|
test_bmdma_teardown(qts);
|
|
}
|
|
}
|
|
|
|
static void test_bmdma_no_busmaster(void)
|
|
{
|
|
QTestState *qts;
|
|
QPCIDevice *dev;
|
|
QPCIBar bmdma_bar, ide_bar;
|
|
uint8_t status;
|
|
|
|
qts = test_bmdma_setup();
|
|
|
|
dev = get_pci_device(qts, &bmdma_bar, &ide_bar);
|
|
|
|
/* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be
|
|
* able to access it anyway because the Bus Master bit in the PCI command
|
|
* register isn't set. This is complete nonsense, but it used to be pretty
|
|
* good at confusing and occasionally crashing qemu. */
|
|
PrdtEntry prdt[4096] = { };
|
|
|
|
status = send_dma_request(qts, CMD_READ_DMA | CMDF_NO_BM, 0, 512,
|
|
prdt, ARRAY_SIZE(prdt), NULL);
|
|
|
|
/* Not entirely clear what the expected result is, but this is what we get
|
|
* in practice. At least we want to be aware of any changes. */
|
|
g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR);
|
|
assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
|
|
free_pci_device(dev);
|
|
test_bmdma_teardown(qts);
|
|
}
|
|
|
|
static void string_cpu_to_be16(uint16_t *s, size_t bytes)
|
|
{
|
|
g_assert((bytes & 1) == 0);
|
|
bytes /= 2;
|
|
|
|
while (bytes--) {
|
|
*s = cpu_to_be16(*s);
|
|
s++;
|
|
}
|
|
}
|
|
|
|
static void test_identify(void)
|
|
{
|
|
QTestState *qts;
|
|
QPCIDevice *dev;
|
|
QPCIBar bmdma_bar, ide_bar;
|
|
uint8_t data;
|
|
uint16_t buf[256];
|
|
int i;
|
|
int ret;
|
|
|
|
qts = ide_test_start(
|
|
"-drive file=%s,if=ide,cache=writeback,format=raw "
|
|
"-global ide-hd.serial=%s -global ide-hd.ver=%s",
|
|
tmp_path, "testdisk", "version");
|
|
|
|
dev = get_pci_device(qts, &bmdma_bar, &ide_bar);
|
|
|
|
/* IDENTIFY command on device 0*/
|
|
qpci_io_writeb(dev, ide_bar, reg_device, 0);
|
|
qpci_io_writeb(dev, ide_bar, reg_command, CMD_IDENTIFY);
|
|
|
|
/* Read in the IDENTIFY buffer and check registers */
|
|
data = qpci_io_readb(dev, ide_bar, reg_device);
|
|
g_assert_cmpint(data & DEV, ==, 0);
|
|
|
|
for (i = 0; i < 256; i++) {
|
|
data = qpci_io_readb(dev, ide_bar, reg_status);
|
|
assert_bit_set(data, DRDY | DRQ);
|
|
assert_bit_clear(data, BSY | DF | ERR);
|
|
|
|
buf[i] = qpci_io_readw(dev, ide_bar, reg_data);
|
|
}
|
|
|
|
data = qpci_io_readb(dev, ide_bar, reg_status);
|
|
assert_bit_set(data, DRDY);
|
|
assert_bit_clear(data, BSY | DF | ERR | DRQ);
|
|
|
|
/* Check serial number/version in the buffer */
|
|
string_cpu_to_be16(&buf[10], 20);
|
|
ret = memcmp(&buf[10], "testdisk ", 20);
|
|
g_assert(ret == 0);
|
|
|
|
string_cpu_to_be16(&buf[23], 8);
|
|
ret = memcmp(&buf[23], "version ", 8);
|
|
g_assert(ret == 0);
|
|
|
|
/* Write cache enabled bit */
|
|
assert_bit_set(buf[85], 0x20);
|
|
|
|
ide_test_quit(qts);
|
|
free_pci_device(dev);
|
|
}
|
|
|
|
/*
|
|
* Write sector 1 with random data to make IDE storage dirty
|
|
* Needed for flush tests so that flushes actually go though the block layer
|
|
*/
|
|
static void make_dirty(QTestState *qts, uint8_t device)
|
|
{
|
|
QPCIDevice *dev;
|
|
QPCIBar bmdma_bar, ide_bar;
|
|
uint8_t status;
|
|
size_t len = 512;
|
|
uintptr_t guest_buf;
|
|
void* buf;
|
|
|
|
dev = get_pci_device(qts, &bmdma_bar, &ide_bar);
|
|
|
|
guest_buf = guest_alloc(&guest_malloc, len);
|
|
buf = g_malloc(len);
|
|
memset(buf, rand() % 255 + 1, len);
|
|
g_assert(guest_buf);
|
|
g_assert(buf);
|
|
|
|
qtest_memwrite(qts, guest_buf, buf, len);
|
|
|
|
PrdtEntry prdt[] = {
|
|
{
|
|
.addr = cpu_to_le32(guest_buf),
|
|
.size = cpu_to_le32(len | PRDT_EOT),
|
|
},
|
|
};
|
|
|
|
status = send_dma_request(qts, CMD_WRITE_DMA, 1, 1, prdt,
|
|
ARRAY_SIZE(prdt), NULL);
|
|
g_assert_cmphex(status, ==, BM_STS_INTR);
|
|
assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR);
|
|
|
|
g_free(buf);
|
|
free_pci_device(dev);
|
|
}
|
|
|
|
static void test_flush(void)
|
|
{
|
|
QTestState *qts;
|
|
QPCIDevice *dev;
|
|
QPCIBar bmdma_bar, ide_bar;
|
|
uint8_t data;
|
|
|
|
qts = ide_test_start(
|
|
"-drive file=blkdebug::%s,if=ide,cache=writeback,format=raw",
|
|
tmp_path);
|
|
|
|
dev = get_pci_device(qts, &bmdma_bar, &ide_bar);
|
|
|
|
qtest_irq_intercept_in(qts, "ioapic");
|
|
|
|
/* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */
|
|
make_dirty(qts, 0);
|
|
|
|
/* Delay the completion of the flush request until we explicitly do it */
|
|
g_free(qtest_hmp(qts, "qemu-io ide0-hd0 \"break flush_to_os A\""));
|
|
|
|
/* FLUSH CACHE command on device 0*/
|
|
qpci_io_writeb(dev, ide_bar, reg_device, 0);
|
|
qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE);
|
|
|
|
/* Check status while request is in flight*/
|
|
data = qpci_io_readb(dev, ide_bar, reg_status);
|
|
assert_bit_set(data, BSY | DRDY);
|
|
assert_bit_clear(data, DF | ERR | DRQ);
|
|
|
|
/* Complete the command */
|
|
g_free(qtest_hmp(qts, "qemu-io ide0-hd0 \"resume A\""));
|
|
|
|
/* Check registers */
|
|
data = qpci_io_readb(dev, ide_bar, reg_device);
|
|
g_assert_cmpint(data & DEV, ==, 0);
|
|
|
|
do {
|
|
data = qpci_io_readb(dev, ide_bar, reg_status);
|
|
} while (data & BSY);
|
|
|
|
assert_bit_set(data, DRDY);
|
|
assert_bit_clear(data, BSY | DF | ERR | DRQ);
|
|
|
|
ide_test_quit(qts);
|
|
free_pci_device(dev);
|
|
}
|
|
|
|
static void test_retry_flush(const char *machine)
|
|
{
|
|
QTestState *qts;
|
|
QPCIDevice *dev;
|
|
QPCIBar bmdma_bar, ide_bar;
|
|
uint8_t data;
|
|
|
|
prepare_blkdebug_script(debug_path, "flush_to_disk");
|
|
|
|
qts = ide_test_start(
|
|
"-drive file=blkdebug:%s:%s,if=ide,cache=writeback,format=raw,"
|
|
"rerror=stop,werror=stop",
|
|
debug_path, tmp_path);
|
|
|
|
dev = get_pci_device(qts, &bmdma_bar, &ide_bar);
|
|
|
|
qtest_irq_intercept_in(qts, "ioapic");
|
|
|
|
/* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */
|
|
make_dirty(qts, 0);
|
|
|
|
/* FLUSH CACHE command on device 0*/
|
|
qpci_io_writeb(dev, ide_bar, reg_device, 0);
|
|
qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE);
|
|
|
|
/* Check status while request is in flight*/
|
|
data = qpci_io_readb(dev, ide_bar, reg_status);
|
|
assert_bit_set(data, BSY | DRDY);
|
|
assert_bit_clear(data, DF | ERR | DRQ);
|
|
|
|
qtest_qmp_eventwait(qts, "STOP");
|
|
|
|
/* Complete the command */
|
|
qmp_discard_response(qts, "{'execute':'cont' }");
|
|
|
|
/* Check registers */
|
|
data = qpci_io_readb(dev, ide_bar, reg_device);
|
|
g_assert_cmpint(data & DEV, ==, 0);
|
|
|
|
do {
|
|
data = qpci_io_readb(dev, ide_bar, reg_status);
|
|
} while (data & BSY);
|
|
|
|
assert_bit_set(data, DRDY);
|
|
assert_bit_clear(data, BSY | DF | ERR | DRQ);
|
|
|
|
ide_test_quit(qts);
|
|
free_pci_device(dev);
|
|
}
|
|
|
|
static void test_flush_nodev(void)
|
|
{
|
|
QTestState *qts;
|
|
QPCIDevice *dev;
|
|
QPCIBar bmdma_bar, ide_bar;
|
|
|
|
qts = ide_test_start("");
|
|
|
|
dev = get_pci_device(qts, &bmdma_bar, &ide_bar);
|
|
|
|
/* FLUSH CACHE command on device 0*/
|
|
qpci_io_writeb(dev, ide_bar, reg_device, 0);
|
|
qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE);
|
|
|
|
/* Just testing that qemu doesn't crash... */
|
|
|
|
free_pci_device(dev);
|
|
ide_test_quit(qts);
|
|
}
|
|
|
|
static void test_flush_empty_drive(void)
|
|
{
|
|
QTestState *qts;
|
|
QPCIDevice *dev;
|
|
QPCIBar bmdma_bar, ide_bar;
|
|
|
|
qts = ide_test_start("-device ide-cd,bus=ide.0");
|
|
dev = get_pci_device(qts, &bmdma_bar, &ide_bar);
|
|
|
|
/* FLUSH CACHE command on device 0 */
|
|
qpci_io_writeb(dev, ide_bar, reg_device, 0);
|
|
qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE);
|
|
|
|
/* Just testing that qemu doesn't crash... */
|
|
|
|
free_pci_device(dev);
|
|
ide_test_quit(qts);
|
|
}
|
|
|
|
static void test_pci_retry_flush(void)
|
|
{
|
|
test_retry_flush("pc");
|
|
}
|
|
|
|
static void test_isa_retry_flush(void)
|
|
{
|
|
test_retry_flush("isapc");
|
|
}
|
|
|
|
typedef struct Read10CDB {
|
|
uint8_t opcode;
|
|
uint8_t flags;
|
|
uint32_t lba;
|
|
uint8_t reserved;
|
|
uint16_t nblocks;
|
|
uint8_t control;
|
|
uint16_t padding;
|
|
} __attribute__((__packed__)) Read10CDB;
|
|
|
|
static void send_scsi_cdb_read10(QPCIDevice *dev, QPCIBar ide_bar,
|
|
uint64_t lba, int nblocks)
|
|
{
|
|
Read10CDB pkt = { .padding = 0 };
|
|
int i;
|
|
|
|
g_assert_cmpint(lba, <=, UINT32_MAX);
|
|
g_assert_cmpint(nblocks, <=, UINT16_MAX);
|
|
g_assert_cmpint(nblocks, >=, 0);
|
|
|
|
/* Construct SCSI CDB packet */
|
|
pkt.opcode = 0x28;
|
|
pkt.lba = cpu_to_be32(lba);
|
|
pkt.nblocks = cpu_to_be16(nblocks);
|
|
|
|
/* Send Packet */
|
|
for (i = 0; i < sizeof(Read10CDB)/2; i++) {
|
|
qpci_io_writew(dev, ide_bar, reg_data,
|
|
le16_to_cpu(((uint16_t *)&pkt)[i]));
|
|
}
|
|
}
|
|
|
|
static void nsleep(QTestState *qts, int64_t nsecs)
|
|
{
|
|
const struct timespec val = { .tv_nsec = nsecs };
|
|
nanosleep(&val, NULL);
|
|
qtest_clock_set(qts, nsecs);
|
|
}
|
|
|
|
static uint8_t ide_wait_clear(QTestState *qts, uint8_t flag)
|
|
{
|
|
QPCIDevice *dev;
|
|
QPCIBar bmdma_bar, ide_bar;
|
|
uint8_t data;
|
|
time_t st;
|
|
|
|
dev = get_pci_device(qts, &bmdma_bar, &ide_bar);
|
|
|
|
/* Wait with a 5 second timeout */
|
|
time(&st);
|
|
while (true) {
|
|
data = qpci_io_readb(dev, ide_bar, reg_status);
|
|
if (!(data & flag)) {
|
|
free_pci_device(dev);
|
|
return data;
|
|
}
|
|
if (difftime(time(NULL), st) > 5.0) {
|
|
break;
|
|
}
|
|
nsleep(qts, 400);
|
|
}
|
|
g_assert_not_reached();
|
|
}
|
|
|
|
static void ide_wait_intr(QTestState *qts, int irq)
|
|
{
|
|
time_t st;
|
|
bool intr;
|
|
|
|
time(&st);
|
|
while (true) {
|
|
intr = qtest_get_irq(qts, irq);
|
|
if (intr) {
|
|
return;
|
|
}
|
|
if (difftime(time(NULL), st) > 5.0) {
|
|
break;
|
|
}
|
|
nsleep(qts, 400);
|
|
}
|
|
|
|
g_assert_not_reached();
|
|
}
|
|
|
|
static void cdrom_pio_impl(int nblocks)
|
|
{
|
|
QTestState *qts;
|
|
QPCIDevice *dev;
|
|
QPCIBar bmdma_bar, ide_bar;
|
|
FILE *fh;
|
|
int patt_blocks = MAX(16, nblocks);
|
|
size_t patt_len = ATAPI_BLOCK_SIZE * patt_blocks;
|
|
char *pattern = g_malloc(patt_len);
|
|
size_t rxsize = ATAPI_BLOCK_SIZE * nblocks;
|
|
uint16_t *rx = g_malloc0(rxsize);
|
|
int i, j;
|
|
uint8_t data;
|
|
uint16_t limit;
|
|
size_t ret;
|
|
|
|
/* Prepopulate the CDROM with an interesting pattern */
|
|
generate_pattern(pattern, patt_len, ATAPI_BLOCK_SIZE);
|
|
fh = fopen(tmp_path, "w+");
|
|
ret = fwrite(pattern, ATAPI_BLOCK_SIZE, patt_blocks, fh);
|
|
g_assert_cmpint(ret, ==, patt_blocks);
|
|
fclose(fh);
|
|
|
|
qts = ide_test_start(
|
|
"-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 "
|
|
"-device ide-cd,drive=sr0,bus=ide.0", tmp_path);
|
|
dev = get_pci_device(qts, &bmdma_bar, &ide_bar);
|
|
qtest_irq_intercept_in(qts, "ioapic");
|
|
|
|
/* PACKET command on device 0 */
|
|
qpci_io_writeb(dev, ide_bar, reg_device, 0);
|
|
qpci_io_writeb(dev, ide_bar, reg_lba_middle, BYTE_COUNT_LIMIT & 0xFF);
|
|
qpci_io_writeb(dev, ide_bar, reg_lba_high, (BYTE_COUNT_LIMIT >> 8 & 0xFF));
|
|
qpci_io_writeb(dev, ide_bar, reg_command, CMD_PACKET);
|
|
/* HP0: Check_Status_A State */
|
|
nsleep(qts, 400);
|
|
data = ide_wait_clear(qts, BSY);
|
|
/* HP1: Send_Packet State */
|
|
assert_bit_set(data, DRQ | DRDY);
|
|
assert_bit_clear(data, ERR | DF | BSY);
|
|
|
|
/* SCSI CDB (READ10) -- read n*2048 bytes from block 0 */
|
|
send_scsi_cdb_read10(dev, ide_bar, 0, nblocks);
|
|
|
|
/* Read data back: occurs in bursts of 'BYTE_COUNT_LIMIT' bytes.
|
|
* If BYTE_COUNT_LIMIT is odd, we transfer BYTE_COUNT_LIMIT - 1 bytes.
|
|
* We allow an odd limit only when the remaining transfer size is
|
|
* less than BYTE_COUNT_LIMIT. However, SCSI's read10 command can only
|
|
* request n blocks, so our request size is always even.
|
|
* For this reason, we assume there is never a hanging byte to fetch. */
|
|
g_assert(!(rxsize & 1));
|
|
limit = BYTE_COUNT_LIMIT & ~1;
|
|
for (i = 0; i < DIV_ROUND_UP(rxsize, limit); i++) {
|
|
size_t offset = i * (limit / 2);
|
|
size_t rem = (rxsize / 2) - offset;
|
|
|
|
/* HP3: INTRQ_Wait */
|
|
ide_wait_intr(qts, IDE_PRIMARY_IRQ);
|
|
|
|
/* HP2: Check_Status_B (and clear IRQ) */
|
|
data = ide_wait_clear(qts, BSY);
|
|
assert_bit_set(data, DRQ | DRDY);
|
|
assert_bit_clear(data, ERR | DF | BSY);
|
|
|
|
/* HP4: Transfer_Data */
|
|
for (j = 0; j < MIN((limit / 2), rem); j++) {
|
|
rx[offset + j] = cpu_to_le16(qpci_io_readw(dev, ide_bar,
|
|
reg_data));
|
|
}
|
|
}
|
|
|
|
/* Check for final completion IRQ */
|
|
ide_wait_intr(qts, IDE_PRIMARY_IRQ);
|
|
|
|
/* Sanity check final state */
|
|
data = ide_wait_clear(qts, DRQ);
|
|
assert_bit_set(data, DRDY);
|
|
assert_bit_clear(data, DRQ | ERR | DF | BSY);
|
|
|
|
g_assert_cmpint(memcmp(pattern, rx, rxsize), ==, 0);
|
|
g_free(pattern);
|
|
g_free(rx);
|
|
test_bmdma_teardown(qts);
|
|
free_pci_device(dev);
|
|
}
|
|
|
|
static void test_cdrom_pio(void)
|
|
{
|
|
cdrom_pio_impl(1);
|
|
}
|
|
|
|
static void test_cdrom_pio_large(void)
|
|
{
|
|
/* Test a few loops of the PIO DRQ mechanism. */
|
|
cdrom_pio_impl(BYTE_COUNT_LIMIT * 4 / ATAPI_BLOCK_SIZE);
|
|
}
|
|
|
|
|
|
static void test_cdrom_dma(void)
|
|
{
|
|
QTestState *qts;
|
|
static const size_t len = ATAPI_BLOCK_SIZE;
|
|
size_t ret;
|
|
char *pattern = g_malloc(ATAPI_BLOCK_SIZE * 16);
|
|
char *rx = g_malloc0(len);
|
|
uintptr_t guest_buf;
|
|
PrdtEntry prdt[1];
|
|
FILE *fh;
|
|
|
|
qts = ide_test_start(
|
|
"-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 "
|
|
"-device ide-cd,drive=sr0,bus=ide.0", tmp_path);
|
|
qtest_irq_intercept_in(qts, "ioapic");
|
|
|
|
guest_buf = guest_alloc(&guest_malloc, len);
|
|
prdt[0].addr = cpu_to_le32(guest_buf);
|
|
prdt[0].size = cpu_to_le32(len | PRDT_EOT);
|
|
|
|
generate_pattern(pattern, ATAPI_BLOCK_SIZE * 16, ATAPI_BLOCK_SIZE);
|
|
fh = fopen(tmp_path, "w+");
|
|
ret = fwrite(pattern, ATAPI_BLOCK_SIZE, 16, fh);
|
|
g_assert_cmpint(ret, ==, 16);
|
|
fclose(fh);
|
|
|
|
send_dma_request(qts, CMD_PACKET, 0, 1, prdt, 1, send_scsi_cdb_read10);
|
|
|
|
/* Read back data from guest memory into local qtest memory */
|
|
qtest_memread(qts, guest_buf, rx, len);
|
|
g_assert_cmpint(memcmp(pattern, rx, len), ==, 0);
|
|
|
|
g_free(pattern);
|
|
g_free(rx);
|
|
test_bmdma_teardown(qts);
|
|
}
|
|
|
|
int main(int argc, char **argv)
|
|
{
|
|
int fd;
|
|
int ret;
|
|
|
|
/* Create temporary blkdebug instructions */
|
|
fd = mkstemp(debug_path);
|
|
g_assert(fd >= 0);
|
|
close(fd);
|
|
|
|
/* Create a temporary raw image */
|
|
fd = mkstemp(tmp_path);
|
|
g_assert(fd >= 0);
|
|
ret = ftruncate(fd, TEST_IMAGE_SIZE);
|
|
g_assert(ret == 0);
|
|
close(fd);
|
|
|
|
/* Run the tests */
|
|
g_test_init(&argc, &argv, NULL);
|
|
|
|
qtest_add_func("/ide/identify", test_identify);
|
|
|
|
qtest_add_func("/ide/bmdma/simple_rw", test_bmdma_simple_rw);
|
|
qtest_add_func("/ide/bmdma/trim", test_bmdma_trim);
|
|
qtest_add_func("/ide/bmdma/various_prdts", test_bmdma_various_prdts);
|
|
qtest_add_func("/ide/bmdma/no_busmaster", test_bmdma_no_busmaster);
|
|
|
|
qtest_add_func("/ide/flush", test_flush);
|
|
qtest_add_func("/ide/flush/nodev", test_flush_nodev);
|
|
qtest_add_func("/ide/flush/empty_drive", test_flush_empty_drive);
|
|
qtest_add_func("/ide/flush/retry_pci", test_pci_retry_flush);
|
|
qtest_add_func("/ide/flush/retry_isa", test_isa_retry_flush);
|
|
|
|
qtest_add_func("/ide/cdrom/pio", test_cdrom_pio);
|
|
qtest_add_func("/ide/cdrom/pio_large", test_cdrom_pio_large);
|
|
qtest_add_func("/ide/cdrom/dma", test_cdrom_dma);
|
|
|
|
ret = g_test_run();
|
|
|
|
/* Cleanup */
|
|
unlink(tmp_path);
|
|
unlink(debug_path);
|
|
|
|
return ret;
|
|
}
|