822 lines
24 KiB
C
822 lines
24 KiB
C
/*
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* Flash NAND memory emulation. Based on "16M x 8 Bit NAND Flash
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* Memory" datasheet for the KM29U128AT / K9F2808U0A chips from
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* Samsung Electronic.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* Support for additional features based on "MT29F2G16ABCWP 2Gx16"
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* datasheet from Micron Technology and "NAND02G-B2C" datasheet
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* from ST Microelectronics.
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*
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* This code is licensed under the GNU GPL v2.
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#ifndef NAND_IO
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/qdev-properties.h"
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#include "hw/block/flash.h"
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#include "sysemu/block-backend.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/module.h"
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# define NAND_CMD_READ0 0x00
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# define NAND_CMD_READ1 0x01
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# define NAND_CMD_READ2 0x50
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# define NAND_CMD_LPREAD2 0x30
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# define NAND_CMD_NOSERIALREAD2 0x35
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# define NAND_CMD_RANDOMREAD1 0x05
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# define NAND_CMD_RANDOMREAD2 0xe0
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# define NAND_CMD_READID 0x90
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# define NAND_CMD_RESET 0xff
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# define NAND_CMD_PAGEPROGRAM1 0x80
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# define NAND_CMD_PAGEPROGRAM2 0x10
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# define NAND_CMD_CACHEPROGRAM2 0x15
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# define NAND_CMD_BLOCKERASE1 0x60
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# define NAND_CMD_BLOCKERASE2 0xd0
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# define NAND_CMD_READSTATUS 0x70
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# define NAND_CMD_COPYBACKPRG1 0x85
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# define NAND_IOSTATUS_ERROR (1 << 0)
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# define NAND_IOSTATUS_PLANE0 (1 << 1)
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# define NAND_IOSTATUS_PLANE1 (1 << 2)
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# define NAND_IOSTATUS_PLANE2 (1 << 3)
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# define NAND_IOSTATUS_PLANE3 (1 << 4)
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# define NAND_IOSTATUS_READY (1 << 6)
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# define NAND_IOSTATUS_UNPROTCT (1 << 7)
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# define MAX_PAGE 0x800
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# define MAX_OOB 0x40
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typedef struct NANDFlashState NANDFlashState;
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struct NANDFlashState {
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DeviceState parent_obj;
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uint8_t manf_id, chip_id;
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uint8_t buswidth; /* in BYTES */
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int size, pages;
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int page_shift, oob_shift, erase_shift, addr_shift;
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uint8_t *storage;
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BlockBackend *blk;
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int mem_oob;
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uint8_t cle, ale, ce, wp, gnd;
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uint8_t io[MAX_PAGE + MAX_OOB + 0x400];
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uint8_t *ioaddr;
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int iolen;
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uint32_t cmd;
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uint64_t addr;
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int addrlen;
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int status;
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int offset;
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void (*blk_write)(NANDFlashState *s);
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void (*blk_erase)(NANDFlashState *s);
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void (*blk_load)(NANDFlashState *s, uint64_t addr, int offset);
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uint32_t ioaddr_vmstate;
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};
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#define TYPE_NAND "nand"
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#define NAND(obj) \
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OBJECT_CHECK(NANDFlashState, (obj), TYPE_NAND)
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static void mem_and(uint8_t *dest, const uint8_t *src, size_t n)
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{
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/* Like memcpy() but we logical-AND the data into the destination */
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int i;
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for (i = 0; i < n; i++) {
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dest[i] &= src[i];
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}
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}
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# define NAND_NO_AUTOINCR 0x00000001
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# define NAND_BUSWIDTH_16 0x00000002
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# define NAND_NO_PADDING 0x00000004
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# define NAND_CACHEPRG 0x00000008
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# define NAND_COPYBACK 0x00000010
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# define NAND_IS_AND 0x00000020
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# define NAND_4PAGE_ARRAY 0x00000040
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# define NAND_NO_READRDY 0x00000100
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# define NAND_SAMSUNG_LP (NAND_NO_PADDING | NAND_COPYBACK)
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# define NAND_IO
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# define PAGE(addr) ((addr) >> ADDR_SHIFT)
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# define PAGE_START(page) (PAGE(page) * (PAGE_SIZE + OOB_SIZE))
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# define PAGE_MASK ((1 << ADDR_SHIFT) - 1)
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# define OOB_SHIFT (PAGE_SHIFT - 5)
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# define OOB_SIZE (1 << OOB_SHIFT)
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# define SECTOR(addr) ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT))
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# define SECTOR_OFFSET(addr) ((addr) & ((511 >> PAGE_SHIFT) << 8))
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# define PAGE_SIZE 256
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# define PAGE_SHIFT 8
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# define PAGE_SECTORS 1
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# define ADDR_SHIFT 8
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# include "nand.c"
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# define PAGE_SIZE 512
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# define PAGE_SHIFT 9
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# define PAGE_SECTORS 1
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# define ADDR_SHIFT 8
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# include "nand.c"
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# define PAGE_SIZE 2048
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# define PAGE_SHIFT 11
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# define PAGE_SECTORS 4
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# define ADDR_SHIFT 16
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# include "nand.c"
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/* Information based on Linux drivers/mtd/nand/nand_ids.c */
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static const struct {
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int size;
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int width;
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int page_shift;
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int erase_shift;
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uint32_t options;
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} nand_flash_ids[0x100] = {
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[0 ... 0xff] = { 0 },
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[0x6e] = { 1, 8, 8, 4, 0 },
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[0x64] = { 2, 8, 8, 4, 0 },
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[0x6b] = { 4, 8, 9, 4, 0 },
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[0xe8] = { 1, 8, 8, 4, 0 },
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[0xec] = { 1, 8, 8, 4, 0 },
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[0xea] = { 2, 8, 8, 4, 0 },
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[0xd5] = { 4, 8, 9, 4, 0 },
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[0xe3] = { 4, 8, 9, 4, 0 },
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[0xe5] = { 4, 8, 9, 4, 0 },
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[0xd6] = { 8, 8, 9, 4, 0 },
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[0x39] = { 8, 8, 9, 4, 0 },
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[0xe6] = { 8, 8, 9, 4, 0 },
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[0x49] = { 8, 16, 9, 4, NAND_BUSWIDTH_16 },
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[0x59] = { 8, 16, 9, 4, NAND_BUSWIDTH_16 },
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[0x33] = { 16, 8, 9, 5, 0 },
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[0x73] = { 16, 8, 9, 5, 0 },
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[0x43] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x53] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x35] = { 32, 8, 9, 5, 0 },
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[0x75] = { 32, 8, 9, 5, 0 },
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[0x45] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x55] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x36] = { 64, 8, 9, 5, 0 },
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[0x76] = { 64, 8, 9, 5, 0 },
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[0x46] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x56] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x78] = { 128, 8, 9, 5, 0 },
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[0x39] = { 128, 8, 9, 5, 0 },
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[0x79] = { 128, 8, 9, 5, 0 },
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[0x72] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x49] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x74] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x59] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x71] = { 256, 8, 9, 5, 0 },
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/*
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* These are the new chips with large page size. The pagesize and the
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* erasesize is determined from the extended id bytes
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*/
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# define LP_OPTIONS (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR)
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# define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
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/* 512 Megabit */
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[0xa2] = { 64, 8, 0, 0, LP_OPTIONS },
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[0xf2] = { 64, 8, 0, 0, LP_OPTIONS },
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[0xb2] = { 64, 16, 0, 0, LP_OPTIONS16 },
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[0xc2] = { 64, 16, 0, 0, LP_OPTIONS16 },
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/* 1 Gigabit */
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[0xa1] = { 128, 8, 0, 0, LP_OPTIONS },
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[0xf1] = { 128, 8, 0, 0, LP_OPTIONS },
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[0xb1] = { 128, 16, 0, 0, LP_OPTIONS16 },
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[0xc1] = { 128, 16, 0, 0, LP_OPTIONS16 },
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/* 2 Gigabit */
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[0xaa] = { 256, 8, 0, 0, LP_OPTIONS },
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[0xda] = { 256, 8, 0, 0, LP_OPTIONS },
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[0xba] = { 256, 16, 0, 0, LP_OPTIONS16 },
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[0xca] = { 256, 16, 0, 0, LP_OPTIONS16 },
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/* 4 Gigabit */
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[0xac] = { 512, 8, 0, 0, LP_OPTIONS },
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[0xdc] = { 512, 8, 0, 0, LP_OPTIONS },
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[0xbc] = { 512, 16, 0, 0, LP_OPTIONS16 },
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[0xcc] = { 512, 16, 0, 0, LP_OPTIONS16 },
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/* 8 Gigabit */
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[0xa3] = { 1024, 8, 0, 0, LP_OPTIONS },
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[0xd3] = { 1024, 8, 0, 0, LP_OPTIONS },
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[0xb3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
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[0xc3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
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/* 16 Gigabit */
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[0xa5] = { 2048, 8, 0, 0, LP_OPTIONS },
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[0xd5] = { 2048, 8, 0, 0, LP_OPTIONS },
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[0xb5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
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[0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
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};
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static void nand_reset(DeviceState *dev)
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{
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NANDFlashState *s = NAND(dev);
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s->cmd = NAND_CMD_READ0;
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s->addr = 0;
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s->addrlen = 0;
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s->iolen = 0;
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s->offset = 0;
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s->status &= NAND_IOSTATUS_UNPROTCT;
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s->status |= NAND_IOSTATUS_READY;
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}
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static inline void nand_pushio_byte(NANDFlashState *s, uint8_t value)
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{
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s->ioaddr[s->iolen++] = value;
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for (value = s->buswidth; --value;) {
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s->ioaddr[s->iolen++] = 0;
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}
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}
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static void nand_command(NANDFlashState *s)
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{
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unsigned int offset;
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switch (s->cmd) {
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case NAND_CMD_READ0:
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s->iolen = 0;
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break;
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case NAND_CMD_READID:
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s->ioaddr = s->io;
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s->iolen = 0;
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nand_pushio_byte(s, s->manf_id);
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nand_pushio_byte(s, s->chip_id);
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nand_pushio_byte(s, 'Q'); /* Don't-care byte (often 0xa5) */
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if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
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/* Page Size, Block Size, Spare Size; bit 6 indicates
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* 8 vs 16 bit width NAND.
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*/
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nand_pushio_byte(s, (s->buswidth == 2) ? 0x55 : 0x15);
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} else {
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nand_pushio_byte(s, 0xc0); /* Multi-plane */
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}
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break;
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case NAND_CMD_RANDOMREAD2:
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case NAND_CMD_NOSERIALREAD2:
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if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP))
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break;
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offset = s->addr & ((1 << s->addr_shift) - 1);
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s->blk_load(s, s->addr, offset);
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if (s->gnd)
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s->iolen = (1 << s->page_shift) - offset;
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else
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s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
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break;
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case NAND_CMD_RESET:
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nand_reset(DEVICE(s));
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break;
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case NAND_CMD_PAGEPROGRAM1:
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s->ioaddr = s->io;
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s->iolen = 0;
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break;
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case NAND_CMD_PAGEPROGRAM2:
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if (s->wp) {
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s->blk_write(s);
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}
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break;
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case NAND_CMD_BLOCKERASE1:
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break;
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case NAND_CMD_BLOCKERASE2:
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s->addr &= (1ull << s->addrlen * 8) - 1;
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s->addr <<= nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP ?
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16 : 8;
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if (s->wp) {
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s->blk_erase(s);
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}
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break;
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case NAND_CMD_READSTATUS:
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s->ioaddr = s->io;
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s->iolen = 0;
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nand_pushio_byte(s, s->status);
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break;
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default:
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printf("%s: Unknown NAND command 0x%02x\n", __func__, s->cmd);
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}
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}
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static int nand_pre_save(void *opaque)
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{
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NANDFlashState *s = NAND(opaque);
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s->ioaddr_vmstate = s->ioaddr - s->io;
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return 0;
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}
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static int nand_post_load(void *opaque, int version_id)
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{
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NANDFlashState *s = NAND(opaque);
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if (s->ioaddr_vmstate > sizeof(s->io)) {
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return -EINVAL;
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}
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s->ioaddr = s->io + s->ioaddr_vmstate;
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return 0;
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}
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static const VMStateDescription vmstate_nand = {
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.name = "nand",
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_save = nand_pre_save,
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.post_load = nand_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(cle, NANDFlashState),
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VMSTATE_UINT8(ale, NANDFlashState),
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VMSTATE_UINT8(ce, NANDFlashState),
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VMSTATE_UINT8(wp, NANDFlashState),
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VMSTATE_UINT8(gnd, NANDFlashState),
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VMSTATE_BUFFER(io, NANDFlashState),
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VMSTATE_UINT32(ioaddr_vmstate, NANDFlashState),
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VMSTATE_INT32(iolen, NANDFlashState),
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VMSTATE_UINT32(cmd, NANDFlashState),
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VMSTATE_UINT64(addr, NANDFlashState),
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VMSTATE_INT32(addrlen, NANDFlashState),
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VMSTATE_INT32(status, NANDFlashState),
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VMSTATE_INT32(offset, NANDFlashState),
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/* XXX: do we want to save s->storage too? */
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VMSTATE_END_OF_LIST()
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}
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};
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static void nand_realize(DeviceState *dev, Error **errp)
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{
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int pagesize;
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NANDFlashState *s = NAND(dev);
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int ret;
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s->buswidth = nand_flash_ids[s->chip_id].width >> 3;
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s->size = nand_flash_ids[s->chip_id].size << 20;
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if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
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s->page_shift = 11;
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s->erase_shift = 6;
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} else {
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s->page_shift = nand_flash_ids[s->chip_id].page_shift;
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s->erase_shift = nand_flash_ids[s->chip_id].erase_shift;
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}
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switch (1 << s->page_shift) {
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case 256:
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nand_init_256(s);
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break;
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case 512:
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nand_init_512(s);
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break;
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case 2048:
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nand_init_2048(s);
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break;
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default:
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error_setg(errp, "Unsupported NAND block size %#x",
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1 << s->page_shift);
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return;
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}
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pagesize = 1 << s->oob_shift;
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s->mem_oob = 1;
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if (s->blk) {
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if (blk_is_read_only(s->blk)) {
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error_setg(errp, "Can't use a read-only drive");
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return;
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}
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ret = blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
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BLK_PERM_ALL, errp);
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if (ret < 0) {
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return;
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}
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if (blk_getlength(s->blk) >=
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(s->pages << s->page_shift) + (s->pages << s->oob_shift)) {
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pagesize = 0;
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s->mem_oob = 0;
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}
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} else {
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pagesize += 1 << s->page_shift;
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}
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if (pagesize) {
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s->storage = (uint8_t *) memset(g_malloc(s->pages * pagesize),
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0xff, s->pages * pagesize);
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}
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/* Give s->ioaddr a sane value in case we save state before it is used. */
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s->ioaddr = s->io;
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}
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static Property nand_properties[] = {
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DEFINE_PROP_UINT8("manufacturer_id", NANDFlashState, manf_id, 0),
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DEFINE_PROP_UINT8("chip_id", NANDFlashState, chip_id, 0),
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DEFINE_PROP_DRIVE("drive", NANDFlashState, blk),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void nand_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = nand_realize;
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dc->reset = nand_reset;
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dc->vmsd = &vmstate_nand;
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device_class_set_props(dc, nand_properties);
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}
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static const TypeInfo nand_info = {
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.name = TYPE_NAND,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(NANDFlashState),
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.class_init = nand_class_init,
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};
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static void nand_register_types(void)
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{
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type_register_static(&nand_info);
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}
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/*
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* Chip inputs are CLE, ALE, CE, WP, GND and eight I/O pins. Chip
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* outputs are R/B and eight I/O pins.
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*
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* CE, WP and R/B are active low.
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*/
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void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
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uint8_t ce, uint8_t wp, uint8_t gnd)
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{
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NANDFlashState *s = NAND(dev);
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s->cle = cle;
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s->ale = ale;
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s->ce = ce;
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s->wp = wp;
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s->gnd = gnd;
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if (wp) {
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s->status |= NAND_IOSTATUS_UNPROTCT;
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} else {
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s->status &= ~NAND_IOSTATUS_UNPROTCT;
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}
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}
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void nand_getpins(DeviceState *dev, int *rb)
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{
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*rb = 1;
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}
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void nand_setio(DeviceState *dev, uint32_t value)
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{
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int i;
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NANDFlashState *s = NAND(dev);
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if (!s->ce && s->cle) {
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if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
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if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2)
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return;
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if (value == NAND_CMD_RANDOMREAD1) {
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s->addr &= ~((1 << s->addr_shift) - 1);
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s->addrlen = 0;
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return;
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}
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}
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if (value == NAND_CMD_READ0) {
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s->offset = 0;
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} else if (value == NAND_CMD_READ1) {
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s->offset = 0x100;
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value = NAND_CMD_READ0;
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} else if (value == NAND_CMD_READ2) {
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s->offset = 1 << s->page_shift;
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value = NAND_CMD_READ0;
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}
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s->cmd = value;
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if (s->cmd == NAND_CMD_READSTATUS ||
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s->cmd == NAND_CMD_PAGEPROGRAM2 ||
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s->cmd == NAND_CMD_BLOCKERASE1 ||
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s->cmd == NAND_CMD_BLOCKERASE2 ||
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s->cmd == NAND_CMD_NOSERIALREAD2 ||
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s->cmd == NAND_CMD_RANDOMREAD2 ||
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s->cmd == NAND_CMD_RESET) {
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nand_command(s);
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}
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if (s->cmd != NAND_CMD_RANDOMREAD2) {
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s->addrlen = 0;
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}
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}
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if (s->ale) {
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unsigned int shift = s->addrlen * 8;
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uint64_t mask = ~(0xffull << shift);
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uint64_t v = (uint64_t)value << shift;
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s->addr = (s->addr & mask) | v;
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s->addrlen ++;
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switch (s->addrlen) {
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case 1:
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if (s->cmd == NAND_CMD_READID) {
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nand_command(s);
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}
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break;
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case 2: /* fix cache address as a byte address */
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s->addr <<= (s->buswidth - 1);
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break;
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case 3:
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if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
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(s->cmd == NAND_CMD_READ0 ||
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s->cmd == NAND_CMD_PAGEPROGRAM1)) {
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nand_command(s);
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}
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break;
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case 4:
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if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
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nand_flash_ids[s->chip_id].size < 256 && /* 1Gb or less */
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(s->cmd == NAND_CMD_READ0 ||
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s->cmd == NAND_CMD_PAGEPROGRAM1)) {
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nand_command(s);
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}
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break;
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case 5:
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if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
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nand_flash_ids[s->chip_id].size >= 256 && /* 2Gb or more */
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(s->cmd == NAND_CMD_READ0 ||
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s->cmd == NAND_CMD_PAGEPROGRAM1)) {
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nand_command(s);
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}
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break;
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default:
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break;
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}
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}
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if (!s->cle && !s->ale && s->cmd == NAND_CMD_PAGEPROGRAM1) {
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if (s->iolen < (1 << s->page_shift) + (1 << s->oob_shift)) {
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for (i = s->buswidth; i--; value >>= 8) {
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s->io[s->iolen ++] = (uint8_t) (value & 0xff);
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}
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}
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} else if (!s->cle && !s->ale && s->cmd == NAND_CMD_COPYBACKPRG1) {
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if ((s->addr & ((1 << s->addr_shift) - 1)) <
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(1 << s->page_shift) + (1 << s->oob_shift)) {
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for (i = s->buswidth; i--; s->addr++, value >>= 8) {
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s->io[s->iolen + (s->addr & ((1 << s->addr_shift) - 1))] =
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(uint8_t) (value & 0xff);
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}
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}
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}
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}
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uint32_t nand_getio(DeviceState *dev)
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{
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int offset;
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uint32_t x = 0;
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NANDFlashState *s = NAND(dev);
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/* Allow sequential reading */
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if (!s->iolen && s->cmd == NAND_CMD_READ0) {
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offset = (int) (s->addr & ((1 << s->addr_shift) - 1)) + s->offset;
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s->offset = 0;
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s->blk_load(s, s->addr, offset);
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if (s->gnd)
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s->iolen = (1 << s->page_shift) - offset;
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else
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s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
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}
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if (s->ce || s->iolen <= 0) {
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return 0;
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}
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for (offset = s->buswidth; offset--;) {
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x |= s->ioaddr[offset] << (offset << 3);
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}
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/* after receiving READ STATUS command all subsequent reads will
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* return the status register value until another command is issued
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*/
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if (s->cmd != NAND_CMD_READSTATUS) {
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s->addr += s->buswidth;
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s->ioaddr += s->buswidth;
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s->iolen -= s->buswidth;
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}
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return x;
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}
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uint32_t nand_getbuswidth(DeviceState *dev)
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{
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NANDFlashState *s = (NANDFlashState *) dev;
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return s->buswidth << 3;
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}
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DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id)
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{
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DeviceState *dev;
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if (nand_flash_ids[chip_id].size == 0) {
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hw_error("%s: Unsupported NAND chip ID.\n", __func__);
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}
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dev = qdev_new(TYPE_NAND);
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qdev_prop_set_uint8(dev, "manufacturer_id", manf_id);
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qdev_prop_set_uint8(dev, "chip_id", chip_id);
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if (blk) {
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qdev_prop_set_drive_err(dev, "drive", blk, &error_fatal);
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}
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qdev_realize(dev, NULL, &error_fatal);
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return dev;
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}
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type_init(nand_register_types)
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#else
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/* Program a single page */
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static void glue(nand_blk_write_, PAGE_SIZE)(NANDFlashState *s)
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{
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uint64_t off, page, sector, soff;
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uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200];
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if (PAGE(s->addr) >= s->pages)
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return;
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if (!s->blk) {
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mem_and(s->storage + PAGE_START(s->addr) + (s->addr & PAGE_MASK) +
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s->offset, s->io, s->iolen);
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} else if (s->mem_oob) {
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sector = SECTOR(s->addr);
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off = (s->addr & PAGE_MASK) + s->offset;
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soff = SECTOR_OFFSET(s->addr);
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if (blk_pread(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
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PAGE_SECTORS << BDRV_SECTOR_BITS) < 0) {
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printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
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return;
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}
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mem_and(iobuf + (soff | off), s->io, MIN(s->iolen, PAGE_SIZE - off));
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if (off + s->iolen > PAGE_SIZE) {
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page = PAGE(s->addr);
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mem_and(s->storage + (page << OOB_SHIFT), s->io + PAGE_SIZE - off,
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MIN(OOB_SIZE, off + s->iolen - PAGE_SIZE));
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}
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if (blk_pwrite(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
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PAGE_SECTORS << BDRV_SECTOR_BITS, 0) < 0) {
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printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
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}
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} else {
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off = PAGE_START(s->addr) + (s->addr & PAGE_MASK) + s->offset;
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sector = off >> 9;
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soff = off & 0x1ff;
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if (blk_pread(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
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(PAGE_SECTORS + 2) << BDRV_SECTOR_BITS) < 0) {
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printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
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return;
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}
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mem_and(iobuf + soff, s->io, s->iolen);
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if (blk_pwrite(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
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(PAGE_SECTORS + 2) << BDRV_SECTOR_BITS, 0) < 0) {
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printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
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}
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}
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s->offset = 0;
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}
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/* Erase a single block */
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static void glue(nand_blk_erase_, PAGE_SIZE)(NANDFlashState *s)
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{
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uint64_t i, page, addr;
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uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, };
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addr = s->addr & ~((1 << (ADDR_SHIFT + s->erase_shift)) - 1);
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if (PAGE(addr) >= s->pages) {
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return;
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}
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if (!s->blk) {
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memset(s->storage + PAGE_START(addr),
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0xff, (PAGE_SIZE + OOB_SIZE) << s->erase_shift);
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} else if (s->mem_oob) {
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memset(s->storage + (PAGE(addr) << OOB_SHIFT),
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0xff, OOB_SIZE << s->erase_shift);
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i = SECTOR(addr);
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page = SECTOR(addr + (1 << (ADDR_SHIFT + s->erase_shift)));
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for (; i < page; i ++)
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if (blk_pwrite(s->blk, i << BDRV_SECTOR_BITS, iobuf,
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BDRV_SECTOR_SIZE, 0) < 0) {
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printf("%s: write error in sector %" PRIu64 "\n", __func__, i);
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}
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} else {
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addr = PAGE_START(addr);
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page = addr >> 9;
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if (blk_pread(s->blk, page << BDRV_SECTOR_BITS, iobuf,
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BDRV_SECTOR_SIZE) < 0) {
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printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
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}
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memset(iobuf + (addr & 0x1ff), 0xff, (~addr & 0x1ff) + 1);
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if (blk_pwrite(s->blk, page << BDRV_SECTOR_BITS, iobuf,
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BDRV_SECTOR_SIZE, 0) < 0) {
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printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
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}
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memset(iobuf, 0xff, 0x200);
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i = (addr & ~0x1ff) + 0x200;
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for (addr += ((PAGE_SIZE + OOB_SIZE) << s->erase_shift) - 0x200;
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i < addr; i += 0x200) {
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if (blk_pwrite(s->blk, i, iobuf, BDRV_SECTOR_SIZE, 0) < 0) {
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printf("%s: write error in sector %" PRIu64 "\n",
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__func__, i >> 9);
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}
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}
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page = i >> 9;
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if (blk_pread(s->blk, page << BDRV_SECTOR_BITS, iobuf,
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BDRV_SECTOR_SIZE) < 0) {
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printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
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}
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memset(iobuf, 0xff, ((addr - 1) & 0x1ff) + 1);
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if (blk_pwrite(s->blk, page << BDRV_SECTOR_BITS, iobuf,
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BDRV_SECTOR_SIZE, 0) < 0) {
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printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
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}
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}
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}
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static void glue(nand_blk_load_, PAGE_SIZE)(NANDFlashState *s,
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uint64_t addr, int offset)
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{
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if (PAGE(addr) >= s->pages) {
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return;
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}
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if (s->blk) {
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if (s->mem_oob) {
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if (blk_pread(s->blk, SECTOR(addr) << BDRV_SECTOR_BITS, s->io,
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PAGE_SECTORS << BDRV_SECTOR_BITS) < 0) {
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printf("%s: read error in sector %" PRIu64 "\n",
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__func__, SECTOR(addr));
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}
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memcpy(s->io + SECTOR_OFFSET(s->addr) + PAGE_SIZE,
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s->storage + (PAGE(s->addr) << OOB_SHIFT),
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OOB_SIZE);
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s->ioaddr = s->io + SECTOR_OFFSET(s->addr) + offset;
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} else {
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if (blk_pread(s->blk, PAGE_START(addr), s->io,
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(PAGE_SECTORS + 2) << BDRV_SECTOR_BITS) < 0) {
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printf("%s: read error in sector %" PRIu64 "\n",
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__func__, PAGE_START(addr) >> 9);
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}
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s->ioaddr = s->io + (PAGE_START(addr) & 0x1ff) + offset;
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}
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} else {
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memcpy(s->io, s->storage + PAGE_START(s->addr) +
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offset, PAGE_SIZE + OOB_SIZE - offset);
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s->ioaddr = s->io;
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}
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}
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static void glue(nand_init_, PAGE_SIZE)(NANDFlashState *s)
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{
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s->oob_shift = PAGE_SHIFT - 5;
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s->pages = s->size >> PAGE_SHIFT;
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s->addr_shift = ADDR_SHIFT;
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s->blk_erase = glue(nand_blk_erase_, PAGE_SIZE);
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s->blk_write = glue(nand_blk_write_, PAGE_SIZE);
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s->blk_load = glue(nand_blk_load_, PAGE_SIZE);
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}
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# undef PAGE_SIZE
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# undef PAGE_SHIFT
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# undef PAGE_SECTORS
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# undef ADDR_SHIFT
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#endif /* NAND_IO */
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