301 lines
7.6 KiB
C
301 lines
7.6 KiB
C
/*
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* (C) Copyright 2001-2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2006-2007
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* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
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*
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* (C) Copyright 2009-2010
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* Max Tretene, ACube Systems Srl. mtretene@acube-systems.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <command.h>
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#include <malloc.h>
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#include <pci.h>
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#include <video_fb.h>
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#include <sm501.h>
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#ifdef CONFIG_VIDEO_SM502
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DECLARE_GLOBAL_DATA_PTR;
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#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
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(((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
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#ifdef CONFIG_VIDEO_SM501_8BPP
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#define BPP 8
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#endif
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#define read8(ptrReg) \
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*(volatile unsigned char *)(sm501.isaBase + ptrReg)
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#define write8(ptrReg,value) \
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*(volatile unsigned char *)(sm501.isaBase + ptrReg) = value
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#define read16(ptrReg) \
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(*(volatile unsigned short *)(sm501.isaBase + ptrReg))
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#define write16(ptrReg,value) \
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(*(volatile unsigned short *)(sm501.isaBase + ptrReg) = value)
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#define read32(ptrReg) \
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(*(volatile unsigned int *)(sm501.isaBase + ptrReg))
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#define write32(ptrReg, value) \
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(*(volatile unsigned int *)(sm501.isaBase + ptrReg) = value)
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GraphicDevice sm501;
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#define DISPLAY_WIDTH 640
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#define DISPLAY_HEIGHT 480
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static const SMI_REGS init_regs_640x480[] = {
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{0x00004, SWAP32(0x00000000)},
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/* clocks for pm0... */
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{0x00040, SWAP32(0x0002184f)},
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{0x00044, SWAP32(0x091a0a01)}, /* 24 MHz pixclk */
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{0x00054, SWAP32(0x00000000)},
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/* clocks for pm1... */
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{0x00048, SWAP32(0x0002184f)},
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{0x0004C, SWAP32(0x091a0a01)},
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{0x00054, SWAP32(0x00000001)},
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/* panel control regs... */
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{0x80004, SWAP32(0xc428bb17)},
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{0x8000C, SWAP32(0x00000000)},
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{0x80010, SWAP32(0x02800280)},
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{0x80014, SWAP32(0x02800000)},
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{0x80018, SWAP32(0x01e00000)},
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{0x8001C, SWAP32(0x00000000)},
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{0x80020, SWAP32(0x01e00280)},
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{0x80024, SWAP32(0x02fa027f)},
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{0x80028, SWAP32(0x004a0280)},
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{0x8002C, SWAP32(0x020c01df)},
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{0x80030, SWAP32(0x000201e7)},
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{0x80200, SWAP32(0x00010000)},
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{0x00008, SWAP32(0x20000000)}, /* gpio29 is pwm0, LED_PWM */
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{0x0000C, SWAP32(0x3f000000)}, /* gpio56 - gpio61 as flat panel data pins */
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{0x10020, SWAP32(0x25725728)}, /* 20 kHz pwm0, 50 % duty cycle, disabled */
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{0x80000, SWAP32(0x0f013104)}, /* panel display control: 8 bit indexed mode */
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{0x800F0, SWAP32(0x00000000)}, /* hardware sprite off */
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{0x80040, SWAP32(0x00000000)}, /* video layer off */
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/* Drawing Engine... */
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/* Contrary to what said in the datasheet the Drawing Engine registers */
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/* are NOT initialized to ZERO at power-up, this lead to strange visual */
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/* bugs under Linux and AmigaOS4.1 for example */
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{0x100000, 0},
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{0x100004, 0},
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{0x100008, 0},
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{0x10000c, 0},
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{0x100010, 0},
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{0x100014, 0},
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{0x100018, 0},
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{0x10001c, 0},
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{0x100020, 0},
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{0x100024, 0},
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{0x100028, 0},
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{0x10002c, 0},
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{0x100030, 0},
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{0x100034, 0},
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{0x100038, 0},
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{0x10003c, 0},
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{0x100040, 0},
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{0x100044, 0},
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{0x100048, 0},
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{0x10004c, 0},
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{0x100050, 0},
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{0, 0}
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};
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/*
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* Returns SM501 register base address. First thing called in the driver.
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*/
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unsigned int board_video_init (void)
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{
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pci_dev_t devbusfn;
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u32 addr;
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/*
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* Is SM501 connected (ppc221/ppc231)?
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*/
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devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
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if (devbusfn != -1) {
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
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return (addr & 0xfffffffe);
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}
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return 0;
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}
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/*
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* Returns SM501 framebuffer address
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*/
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unsigned int board_video_get_fb (void)
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{
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pci_dev_t devbusfn;
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u32 addr;
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/*
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* Is SM501 connected (ppc221/ppc231)?
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*/
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devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
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if (devbusfn != -1) {
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
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addr &= 0xfffffffe;
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#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
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addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
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#endif
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return addr;
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}
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return 0;
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}
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/*
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* Called after initializing the SM501 and before clearing the screen.
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*/
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void board_validate_screen (unsigned int base)
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{
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}
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/*
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* Return a pointer to the initialization sequence.
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*/
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const SMI_REGS *board_get_regs (void)
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{
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return init_regs_640x480;
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}
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int board_get_width (void)
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{
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return 640;
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}
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int board_get_height (void)
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{
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return 480;
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}
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/*-----------------------------------------------------------------------------
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* SmiSetRegs --
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*-----------------------------------------------------------------------------
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*/
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static void SmiSetRegs (void)
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{
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/*
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* The content of the chipset register depends on the board (clocks,
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* ...)
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*/
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const SMI_REGS *preg = board_get_regs ();
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while (preg->Index) {
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write32 (preg->Index, preg->Value);
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/*
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* Insert a delay between
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*/
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udelay (1000);
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preg ++;
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}
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}
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/*-----------------------------------------------------------------------------
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* video_hw_init --
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*-----------------------------------------------------------------------------
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*/
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void *video_hw_init (void)
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{
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unsigned int *vm, i;
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memset (&sm501, 0, sizeof (GraphicDevice));
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/*
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* Initialization of the access to the graphic chipset Retreive base
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* address of the chipset (see board/RPXClassic/eccx.c)
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*/
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if ((sm501.isaBase = board_video_init ()) == 0) {
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return (NULL);
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}
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if ((sm501.frameAdrs = board_video_get_fb ()) == 0) {
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return (NULL);
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}
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sm501.winSizeX = board_get_width ();
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sm501.winSizeY = board_get_height ();
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#if defined(CONFIG_VIDEO_SM501_8BPP)
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sm501.gdfIndex = GDF__8BIT_INDEX;
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sm501.gdfBytesPP = 1;
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#elif defined(CONFIG_VIDEO_SM501_16BPP)
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sm501.gdfIndex = GDF_16BIT_565RGB;
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sm501.gdfBytesPP = 2;
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#elif defined(CONFIG_VIDEO_SM501_32BPP)
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sm501.gdfIndex = GDF_32BIT_X888RGB;
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sm501.gdfBytesPP = 4;
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#else
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#error Unsupported SM501 BPP
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#endif
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sm501.memSize = sm501.winSizeX * sm501.winSizeY * sm501.gdfBytesPP;
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/* Load Smi registers */
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SmiSetRegs ();
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/* (see board/RPXClassic/RPXClassic.c) */
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board_validate_screen (sm501.isaBase);
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/* Clear video memory */
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i = sm501.memSize/4;
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vm = (unsigned int *)sm501.frameAdrs;
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while(i--)
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*vm++ = 0;
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return (&sm501);
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}
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/*-----------------------------------------------------------------------------
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* video_set_lut --
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*-----------------------------------------------------------------------------
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*/
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void video_set_lut (
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unsigned int index, /* color number */
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unsigned char r, /* red */
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unsigned char g, /* green */
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unsigned char b /* blue */
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)
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{
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unsigned long value = 0;
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//unsigned char tt = index;
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value = (r << 16) | (g << 8) | b;
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// using a gray palette
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//value = (tt << 16) | (tt << 8) | tt;
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write32 ((index*4) + 0x80400, SWAP32(value));
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}
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#endif /* CONFIG_VIDEO_SM502 */
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