59 lines
1.8 KiB
ReStructuredText
59 lines
1.8 KiB
ReStructuredText
.. _OPAL_SIGNAL_SYSTEM_RESET:
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OPAL_SIGNAL_SYSTEM_RESET
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========================
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::
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int64_t signal_system_reset(int32_t cpu_nr);
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This OPAL call causes the specified cpu(s) to be reset to the system
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reset exception handler (0x100).
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The SRR1 register will indicate a power-saving wakeup when appropriate,
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and the wake reason will be System Reset (see Power ISA).
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This interrupt may not be recoverable in some cases (e.g., if it is
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raised when the target has MSR[RI]=0), so it should not be used in
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normal operation, but only for crashing, debugging, and similar
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exceptional cases.
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OPAL_SIGNAL_SYSTEM_RESET can pull CPUs out of OPAL, which may be
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undesirable in a crash or shutdown situation (e.g., because they may
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hold locks which are required to access the console, or may be halfway
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through setting hardware registers), so OPAL_QUIESCE can be used
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before OPAL_SIGNAL_SYSTEM_RESET to (attempt to) ensure all CPUs are
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out of OPAL before being interrupted.
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Arguments
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---------
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::
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int32_t cpu_nr
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cpu_nr >= 0 The cpu server number of the target cpu to reset.
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SYS_RESET_ALL (-1) All cpus should be reset.
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SYS_RESET_ALL_OTHERS (-2) All but the current cpu should be reset.
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Returns
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-------
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OPAL_SUCCESS
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The system reset requests to target CPU(s) was successful. This returns
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asynchronously without acknowledgement from targets that system reset
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interrupt processing has completed or even started.
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OPAL_PARAMETER
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A parameter was incorrect.
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OPAL_HARDWARE
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Hardware indicated failure during reset, some or all of the target CPUs
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may have the system reset delivered.
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OPAL_CONSTRAINED
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Platform does not support broadcast operations.
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OPAL_PARTIAL
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Platform can not reset sibling threads on the same core as requested.
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None of the specified CPUs are reset in this case.
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OPAL_UNSUPPORTED
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This processor/platform is not supported.
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