77 lines
3 KiB
ReStructuredText
77 lines
3 KiB
ReStructuredText
.. _skiboot-5.9.5:
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=============
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skiboot-5.9.5
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=============
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skiboot 5.9.5 was released on Wednesday December 13th, 2017. It replaces
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:ref:`skiboot-5.9.4` as the current stable release in the 5.9.x series.
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Over :ref:`skiboot-5.9.4`, we have a few bug fixes, they are:
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- Fix *extremely* rare race in timer code.
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- xive: Ensure VC informational FIRs are masked
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Some HostBoot versions leave those as checkstop, they are harmless
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and can sometimes occur during normal operations.
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- xive: Fix occasional VC checkstops in xive_reset
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The current workaround for the scrub bug described in
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__xive_cache_scrub() has an issue in that it can leave
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dirty invalid entries in the cache.
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When cleaning up EQs or VPs during reset, if we then
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remove the underlying indirect page for these entries,
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the XIVE will checkstop when trying to flush them out
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of the cache.
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This replaces the existing workaround with a new pair of
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workarounds for VPs and EQs:
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- The VP one does the dummy watch on another entry than
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the one we scrubbed (which does the job of pushing old
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stores out) using an entry that is known to be backed by
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a permanent indirect page.
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- The EQ one switches to a more efficient workaround
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which consists of doing a non-side-effect ESB load from
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the EQ's ESe control bits.
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- io: Add load_wait() helper
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This uses the standard form twi/isync pair to ensure a load
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is consumed by the core before continuing. This can be necessary
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under some circumstances for example when having the following
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sequence:
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- Store reg A
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- Load reg A (ensure above store pushed out)
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- delay loop
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- Store reg A
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IE, a mandatory delay between 2 stores. In theory the first store
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is only guaranteed to rach the device after the load from the same
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location has completed. However the processor will start executing
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the delay loop without waiting for the return value from the load.
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This construct enforces that the delay loop isn't executed until
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the load value has been returned.
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- xive: Do not return a trigger page for an escalation interrupt
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This is bogus, we don't support them. (Thankfully the callers
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didn't actually try to use this on escalation interrupts).
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- xive: Mark a freed IRQ's IVE as valid and masked
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Removing the valid bit means a FIR will trip if it's accessed
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inadvertently. Under some circumstances, the XIVE will speculatively
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access an IVE for a masked interrupt and trip it. So make sure that
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freed entries are still marked valid (but masked).
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- hw/nx: Fix NX BAR assignments
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The NX rng BAR is used by each core to source random numbers for the
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DARN instruction. Currently we configure each core to use the NX rng of
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the chip that it exists on. Unfortunately, the NX can be deconfigured by
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hostboot and in this case we need to use the NX of a different chip.
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This patch moves the BAR assignments for the NX into the normal nx-rng
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init path. This lets us check if the normal (chip local) NX is active
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when configuring which NX a core should use so that we can fallback
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gracefully.
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