702 lines
23 KiB
C
702 lines
23 KiB
C
/* Copyright 2013-2014 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stdint.h>
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/* Hostboot runtime interface */
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/* Derived from src/include/runtime/interface.h in Hostboot */
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#define HOSTBOOT_RUNTIME_INTERFACE_VERSION 0x9002
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/** Memory error types defined for memory_error() interface. */
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enum MemoryError_t
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{
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/** Hardware has reported a solid memory CE that is
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* correctable, but continues to report errors on subsequent
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* reads. A second CE on that cache line will result in memory
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* UE. Therefore, it is advised to migrate off of the address
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* range as soon as possible. */
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MEMORY_ERROR_CE = 0,
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/** Hardware has reported an uncorrectable error in memory
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* (memory UE, channel failure, etc). The hypervisor should
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* migrate any partitions off this address range as soon as
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* possible. Note that these kind of errors will most likely
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* result in partition failures. It is advised that the
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* hypervisor waits some time for PRD to handle hardware
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* attentions so that the hypervisor will know all areas of
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* memory that are impacted by the failure. */
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MEMORY_ERROR_UE = 1,
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/** Firmware has predictively requested service on a part in the memory
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* subsystem. The partitions may not have been affected, but it is
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* advised to migrate off of the address range as soon as possible to
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* avoid potential partition outages. */
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MEMORY_ERROR_PREDICTIVE = 2,
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};
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/* Capability sets, for get_interface_capabilities */
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#define HBRT_CAPS_SET0_COMMON 0
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#define HBRT_CAPS_SET1_OPAL 1
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#define HBRT_CAPS_SET2_PHYP 2
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/* Capability flags */
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/**
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* xscom_read and xscom_write return proper return codes on error.
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* Previous implementations may have incorrectly ignored failures.
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*/
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#define HBRT_CAPS_OPAL_HAS_XSCOM_RC (1ul << 0)
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#define HBRT_CAPS_OPAL_HAS_WAKEUP_SUPPORT (1ul << 1)
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/**
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* Load types for the load_pm_complex() interface
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* HBRT_PM_LOAD: initial load of all lids/sections from scratch,
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* preserve nothing
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* HBRT_PM_RELOAD: concurrent reload of all lids/sections,
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* but preserve runtime updates
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*/
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#define HBRT_PM_LOAD 0
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#define HBRT_PM_RELOAD 1
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struct host_interfaces {
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/** Interface version. */
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uint64_t interface_version;
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/** Put a string to the console. */
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void (*puts)(const char*);
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/** Critical failure in runtime execution. */
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void (*assert)(void);
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/** OPTIONAL. Hint to environment that the page may be executed. */
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int (*set_page_execute)(void*);
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/** malloc */
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void *(*malloc)(size_t);
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/** free */
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void (*free)(void*);
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/** realloc */
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void *(*realloc)(void*, size_t);
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/**
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* @brief Send a PEL to the FSP
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* @param[in] plid Platform Log identifier
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* @param[in] data size in bytes
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* @param[in] pointer to data
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* @return 0 on success else error code
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* @platform FSP
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*/
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int (*send_error_log)(uint32_t,uint32_t,void *);
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/**
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* @brief Scan communication read
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* @param[in] chip_id (based on devtree defn)
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* @param[in] address
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* @param[in] pointer to 8-byte data buffer
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* @return 0 on success else return code
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* @platform FSP,OpenPOWER
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*/
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int (*scom_read)(uint64_t, uint64_t, void*);
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/**
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* @brief Scan communication write
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* @param[in] chip_id (based on devtree defn)
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* @param[in] address
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* @param[in] pointer to 8-byte data buffer
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* @return 0 on success else return code
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* @platform FSP,OpenPOWER
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*/
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int (*scom_write)(uint64_t, uint64_t, const void *);
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/**
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* @brief Load a LID from PNOR, FSP, etc.
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*
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* @param[in] LID number.
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* @param[out] Allocated buffer for LID.
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* @param[out] Size of LID (in bytes).
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*
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* @return 0 on success, else RC.
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* @platform FSP
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*/
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int (*lid_load)(uint32_t lid, void **buf, size_t *len);
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/**
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* @brief Release memory from previously loaded LID.
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*
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* @param[in] Allocated buffer for LID to release.
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*
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* @return 0 on success, else RC.
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* @platform FSP
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*/
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int (*lid_unload)(void *buf);
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/**
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* @brief Get the address of a reserved memory region by its devtree
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* name.
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*
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* @param[in] Devtree name (ex. "ibm,hbrt-vpd-image")
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* @param[in] Devtree instance
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* @return physical address of region (or NULL).
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* @platform FSP,OpenPOWER
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*/
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uint64_t (*get_reserved_mem)(const char *name, uint32_t instance);
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/**
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* @brief Force a core to be awake, or clear the force
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* @param[in] i_core Core to wake up (pid)
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* @param[in] i_mode 0=force awake
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* 1=clear force
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* 2=clear all previous forces
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* @return rc non-zero on error
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* @platform FSP
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*/
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int (*wakeup)( uint32_t i_core, uint32_t i_mode );
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/**
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* @brief Delay/sleep for at least the time given
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*
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* The sleep time must be normalised; i_nano_seconds should be between
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* 0 and 999999999.
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*
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* @param[in] seconds
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* @param[in] nano seconds
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* @platform FSP,OpenPOWER
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*/
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void (*nanosleep)(uint64_t i_seconds, uint64_t i_nano_seconds);
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/**
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* @brief Report an OCC error to the host
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* @param[in] Failing status that identifies the nature of the fail
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* @param[in] Identifier that specifies the failing part
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* @platform FSP
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*/
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void (*report_occ_failure)( uint64_t i_status, uint64_t i_partId );
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/**
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* @brief Reads the clock value from a POSIX clock.
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* @param[in] i_clkId - The clock ID to read.
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* @param[out] o_tp - The timespec struct to store the clock value in.
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*
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* @return 0 or -(errno).
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* @retval 0 - SUCCESS.
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* @retval -EINVAL - Invalid clock requested.
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* @retval -EFAULT - NULL ptr given for timespec struct.
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*
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* @platform OpenPOWER
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*/
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int (*clock_gettime)( clockid_t i_clkId, struct timespec* o_tp );
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/**
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* @brief Read Pnor
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* @param[in] i_proc: processor Id
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* @param[in] i_partitionName: name of the partition to read
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* @param[in] i_offset: offset within the partition
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* @param[out] o_data: pointer to the data read
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* @param[in] i_sizeBytes: size of data to read
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* @retval rc - number of bytes read, or non-zero on error
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* @platform OpenPOWER
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*/
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int (*pnor_read) ( uint32_t i_proc, const char* i_partitionName,
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uint64_t i_offset, void* o_data, size_t i_sizeBytes );
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/**
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* @brief Write to Pnor
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* @param[in] i_proc: processor Id
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* @param[in] i_partitionName: name of the partition to write
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* @param[in] i_offset: offset within the partition
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* @param[in] i_data: pointer to the data to write
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* @param[in] i_sizeBytes: size of data to write
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* @retval rc - number of bytes written, or non-zero on error
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* @platform OpenPOWER
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*/
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int (*pnor_write) ( uint32_t i_proc, const char* i_partitionName,
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uint64_t i_offset, void* i_data, size_t i_sizeBytes );
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/**
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* i2c master description: chip, engine and port packed into
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* a single 64-bit argument
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*
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* ---------------------------------------------------
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* | chip | reserved | eng | port |
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* | (32) | (16) | (8) | (8) |
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* ---------------------------------------------------
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*/
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#define HBRT_I2C_MASTER_CHIP_SHIFT 32
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#define HBRT_I2C_MASTER_CHIP_MASK (0xfffffffful << 32)
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#define HBRT_I2C_MASTER_ENGINE_SHIFT 8
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#define HBRT_I2C_MASTER_ENGINE_MASK (0xfful << 8)
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#define HBRT_I2C_MASTER_PORT_SHIFT 0
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#define HBRT_I2C_MASTER_PORT_MASK (0xfful)
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/**
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* @brief Read data from an i2c device
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* @param[in] i_master - Chip/engine/port of i2c bus
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* @param[in] i_devAddr - I2C address of device
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* @param[in] i_offsetSize - Length of offset (in bytes)
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* @param[in] i_offset - Offset within device to read
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* @param[in] i_length - Number of bytes to read
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* @param[out] o_data - Data that was read
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* @return 0 on success else return code
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* @platform OpenPOWER
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*/
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int (*i2c_read)( uint64_t i_master, uint16_t i_devAddr,
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uint32_t i_offsetSize, uint32_t i_offset,
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uint32_t i_length, void* o_data );
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/**
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* @brief Write data to an i2c device
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* @param[in] i_master - Chip/engine/port of i2c bus
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* @param[in] i_devAddr - I2C address of device
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* @param[in] i_offsetSize - Length of offset (in bytes)
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* @param[in] i_offset - Offset within device to write
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* @param[in] i_length - Number of bytes to write
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* @param[in] Data to write
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* @return 0 on success else return code
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* @platform OpenPOWER
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*/
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int (*i2c_write)( uint64_t i_master, uint16_t i_devAddr,
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uint32_t i_offsetSize, uint32_t i_offset,
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uint32_t i_length, void* i_data );
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/**
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* Perform an IPMI transaction
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* @param[in] netfn The IPMI netfn byte
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* @param[in] cmd The IPMI cmd byte
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* @param[in] tx_buf The IPMI packet to send to the host
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* @param[in] tx_size The number of bytes, to send
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* @param[in] rx_buf A buffer to be populated with the IPMI
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* response.
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* @param[inout] rx_size The allocated size of the rx buffer on
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* input, updated to the size of the response on output.
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* This should always begin with the IPMI completion
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* code.
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*/
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int (*ipmi_msg)(uint8_t netfn, uint8_t cmd,
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void *tx_buf, size_t tx_size,
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void *rx_buf, size_t *rx_size);
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/**
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* @brief Hardware has reported a memory error. This function requests
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* the hypervisor to remove the all addresses within the address range
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* given (including endpoints) from the available memory space.
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*
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* It is understood that the hypervisor may not be able to immediately
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* deallocate the memory because it may be in use by a partition.
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* Therefore, the hypervisor should cache all requests and deallocate
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* the memory once it has been freed.
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*
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* @param i_startAddr The beginning address of the range.
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* @param i_endAddr The end address of the range.
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* @param i_errorType See enum MemoryError_t.
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*
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* @return 0 if the request is successfully received. Any value other
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* than 0 on failure. The hypervisor should cache the request and
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* return immediately. It should not wait for the request to be
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* applied. See note above.
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*/
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int (*memory_error)( uint64_t i_startAddr, uint64_t i_endAddr,
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enum MemoryError_t i_errorType );
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/**
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* @brief Query the prd infrastructure for interface capabilities.
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* @param[in] i_set The set of capabilites to retrieve
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*
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* @return a bitmask containing the relevant HBRT_CAPS_* for
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* this implementation and the specified set.
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*/
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uint64_t (*get_interface_capabilities)(uint64_t i_set);
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/**
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* @brief Map a physical address space into usable memory
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* @note Repeated calls to map the same memory should not return an
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* error
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* @param[in] i_physMem Physical address
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* @param[in] i_bytes Number of bytes to map in
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* @return NULL on error, else pointer to usable memory
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* @platform FSP, OpenPOWER
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*/
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void* (*map_phys_mem)(uint64_t i_physMem, size_t i_bytes);
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/**
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* @brief Unmap a physical address space from usable memory
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* @param[in] i_ptr Previously mapped pointer
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* @return 0 on success, else RC
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* @platform FSP, OpenPOWER
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*/
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int (*unmap_phys_mem)(void* i_ptr);
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/**
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* @brief Modify the SCOM restore section of the HCODE image with the
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* given register data
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*
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* @note The Hypervisor should perform the following actions:
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* - insert the data into the HCODE image (p9_stop_api)
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*
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* @pre HBRT is responsible for enabling special wakeup on the
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* associated core(s) before calling this interface
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*
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* @param i_chipId processor chip ID
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* plus ID type, always proc (0x0)
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* @param i_section runtime section to update
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* (passthru to pore_gen_scom)
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* @param i_operation type of operation to perform
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* (passthru to pore_gen_scom)
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* @param i_scomAddr fully qualified scom address
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* @param i_scomData data for operation
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*
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* @return 0 if the request is successfully received.
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* Any value other than 0 on failure.
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* @platform FSP, OpenPOWER
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*/
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int (*hcode_scom_update)(uint64_t i_chipId,
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uint32_t i_section,
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uint32_t i_operation,
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uint64_t i_scomAddr,
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uint64_t i_scomData);
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/**
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* @brief Send a request to firmware, and receive a response
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* @details
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* req_len bytes are sent to runtime firmware, and resp_len
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* bytes received in response.
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*
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* Both req and resp are allocated by the caller. If resp_len
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* is not large enough to contain the full response, an error
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* is returned.
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*
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* @param[in] i_reqLen length of request data
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* @param[in] i_req request data
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* @param[inout] o_respLen in: size of request data buffer
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* out: length of request data
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* @param[in] o_resp response data
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* @return 0 on success, else RC
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* @platform FSP, OpenPOWER
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*/
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int (*firmware_request)(uint64_t i_reqLen, void *i_req,
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uint64_t *o_respLen, void *o_resp);
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/* Reserve some space for future growth. */
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void (*reserved[27])(void);
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};
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struct runtime_interfaces {
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/** Interface version. */
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uint64_t interface_version;
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/**
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* @brief Execute CxxTests that may be contained in the image.
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*
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* @param[in] - Pointer to CxxTestStats structure for results reporting.
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*/
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void (*cxxtestExecute)(void *);
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/**
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* @brief Get a list of lids numbers of the lids known to HostBoot
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*
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* @param[out] o_num - the number of lids in the list
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* @return a pointer to the list
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* @platform FSP
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*/
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const uint32_t * (*get_lid_list)(size_t * o_num);
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/**
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* @brief Load OCC Image and common data into mainstore, also setup OCC
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* BARSs
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*
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* @param[in] i_homer_addr_phys - The physical mainstore address of the
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* start of the HOMER image
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* @param[in] i_homer_addr_va - Virtual memory address of the HOMER
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* image
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* @param[in] i_common_addr_phys - The physical mainstore address
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* of the OCC common area.
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* @param[in] i_common_addr_va - Virtual memory address of the common
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* area
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* @param[in] i_chip - The HW chip id (XSCOM chip ID)
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* @return 0 on success else return code
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* @platform FSP
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*/
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int (*occ_load)(uint64_t i_homer_addr_phys,
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uint64_t i_homer_addr_va,
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uint64_t i_common_addr_phys,
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uint64_t i_common_addr_va,
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uint64_t i_chip);
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/**
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* @brief Start OCC on all chips, by module
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*
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* @param[in] i_chip - Array of functional HW chip ids
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* @Note The caller must include a complete modules worth of chips
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* @param[in] i_num_chips - Number of chips in the array
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* @return 0 on success else return code
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* @platform FSP
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*/
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int (*occ_start)(uint64_t* i_chip, size_t i_num_chips);
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/**
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* @brief Stop OCC hold OCCs in reset
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*
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* @param[in] i_chip - Array of functional HW chip ids
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* @Note The caller must include a complete modules worth of chips
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* @param[in] i_num_chips - Number of chips in the array
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* @return 0 on success else return code
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* @platform FSP
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*/
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int (*occ_stop)(uint64_t* i_chip, size_t i_num_chips);
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/**
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* @brief Notify HTMGT that an OCC has an error to report
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*
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* @details When an OCC has encountered an error that it wants to
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* be reported, this interface will be called to trigger
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* HTMGT to collect and commit the error.
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*
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* @param[i] i_chipId - Id of processor with failing OCC
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* @platform OpenPower
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*/
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void (*process_occ_error) (uint64_t i_chipId);
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/**
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* @brief Enable chip attentions
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*
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* @return 0 on success else return code
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* @platform OpenPower
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*/
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int (*enable_attns)(void);
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/**
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* @brief Disable chip attentions
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*
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* @return 0 on success else return code
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* @platform OpenPower
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*/
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int (*disable_attns)(void);
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/**
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* @brief handle chip attentions
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*
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* @param[in] i_proc - processor chip id at attention XSCOM chip id
|
|
* based on devtree defn
|
|
* @param[in] i_ipollStatus - processor chip Ipoll status
|
|
* @param[in] i_ipollMask - processor chip Ipoll mask
|
|
* @return 0 on success else return code
|
|
* @platform OpenPower
|
|
*/
|
|
int (*handle_attns)(uint64_t i_proc, uint64_t i_ipollStatus,
|
|
uint64_t i_ipollMask);
|
|
|
|
/**
|
|
* @brief Notify HTMGT that an OCC has failed and needs to be reset
|
|
*
|
|
* @details When BMC detects an OCC failure that requires a reset,
|
|
* this interface will be called to trigger the OCC reset. HTMGT
|
|
* maintains a reset count and if there are additional resets
|
|
* available, the OCCs get reset/reloaded. If the recovery attempts
|
|
* have been exhauseted or the OCC fails to go active, an unrecoverable
|
|
* error will be logged and the system will remain in safe mode.
|
|
*
|
|
* @param[in] i_chipId ChipID which identifies the OCC reporting an
|
|
* error
|
|
* @platform OpenPOWER
|
|
*/
|
|
void (*process_occ_reset)(uint64_t i_chipId);
|
|
|
|
/**
|
|
* @brief Change the OCC state
|
|
*
|
|
* @details This is a blocking call that will change the OCC state.
|
|
* The OCCs will only actuate (update processor frequency/ voltages)
|
|
* when in Active state. The OCC will only be monitoring/observing
|
|
* when in Observation state.
|
|
*
|
|
* @note When the OCCs are initially started, the state will
|
|
* default to Active. If the state is changed to Observation, that
|
|
* state will be retained until the next IPL. (If the OCC would get
|
|
* reset, it would return to the last requested state)
|
|
*
|
|
* @param[in] i_occActivation set to true to move OCC to Active state
|
|
* or false to move OCC to Observation state
|
|
*
|
|
* @return 0 on success, or return code if the state did not change.
|
|
* @platform OpenPower
|
|
*/
|
|
int (*enable_occ_actuation)(bool i_occActivation);
|
|
|
|
/**
|
|
* @brief Apply a set of attribute overrides
|
|
*
|
|
* @param[in] pointer to binary override data
|
|
* @param[in] length of override data (bytes)
|
|
* @returns 0 on success, or return code if the command failed
|
|
*
|
|
* @platform OpenPower
|
|
*/
|
|
int (*apply_attr_override)(uint8_t *i_data, size_t size);
|
|
|
|
/**
|
|
* @brief Send a pass-through command to HTMGT
|
|
*
|
|
* @details This is a blocking call that will send a command to
|
|
* HTMGT.
|
|
*
|
|
* @note If o_rspLength is returned with a non-zero value, the
|
|
* data at the o_rspData should be dumped to stdout in a
|
|
* hex dump format.
|
|
* @note The maximum response data returned will be 4096 bytes
|
|
*
|
|
* @param[in] i_cmdLength number of bytes in pass-thru command data
|
|
* @param[in] *i_cmdData pointer to pass-thru command data
|
|
* @param[out] *o_rspLength pointer to number of bytes returned in
|
|
* o_rspData
|
|
* @param[out] *o_rspData pointer to a 4096 byte buffer that will
|
|
* contain the response data from the command
|
|
*
|
|
* @returns 0 on success, or return code if the command failed
|
|
* @platform OpenPower
|
|
*/
|
|
int (*mfg_htmgt_pass_thru)(uint16_t i_cmdLength, uint8_t *i_cmdData,
|
|
uint16_t *o_rspLength, uint8_t *o_rspData);
|
|
|
|
/**
|
|
* @brief Execute an arbitrary command inside hostboot runtime
|
|
* @param[in] Number of arguments (standard C args)
|
|
* @param[in] Array of argument values (standard C args)
|
|
* @param[out] Response message (NULL terminated), memory allocated
|
|
* by hbrt, if o_outString is NULL then no response will
|
|
* be sent
|
|
* @return 0 on success, else error code
|
|
*/
|
|
int (*run_command)(int argc, const char **argv, char **o_outString);
|
|
|
|
/**
|
|
* @brief Verify integrity of a secure container
|
|
* @param[in] i_pContainer Pointer to a valid secure container,
|
|
* Must not be NULL. Container is assumed to be stripped of any
|
|
* ECC and must start with a valid secure header (which contains
|
|
* the container size information)
|
|
* @param[in] i_pHwKeyHash Pointer to a valid hardware keys' hash.
|
|
* Must not be NULL.
|
|
* @param[in] i_hwKeyHashSize Size of the hardware keys' hash.
|
|
* A value which incorrectly states the size of the hardware keys'
|
|
* hash will be detected as a verification error or worse, an
|
|
* illegal memory access. Must not be 0.
|
|
* @note If secureboot is compiled out, the function pointer will be
|
|
* set to NULL. If caller's secureboot support is compiled in and
|
|
* secureboot is enabled by policy, then caller should treat a NULL
|
|
* pointer as a verification failure.
|
|
* @return Integer error code indicating success or failure
|
|
* @retval 0 Container verified correctly
|
|
* @retval !0 API error or otherwise failed to verify container
|
|
* @platform FSP, OpenPOWER
|
|
*/
|
|
int (*verify_container)(const void *i_pContainer,
|
|
const void *i_pHwKeyHash,
|
|
size_t i_hwKeyHashSize);
|
|
|
|
/**
|
|
* @brief SBE message passing
|
|
*
|
|
* @details
|
|
* This is a blocking call that will pass an SBE message
|
|
* with a pass-through command through HBRT to code that
|
|
* will process the command and provide a response.
|
|
*
|
|
* @param[in] i_procChipId Chip ID of the processor whose SBE is
|
|
* passing the message and sent the interrupt
|
|
*
|
|
* @return 0 on success, or return code if the command failed
|
|
* @platform FSP, OpenPOWER
|
|
*/
|
|
int (*sbe_message_passing)(uint32_t i_procChipId);
|
|
|
|
/**
|
|
* @brief Load OCC/HCODE images into mainstore
|
|
*
|
|
* @param[in] i_chip the HW chip id (XSCOM chip ID)
|
|
* @param[in] i_homer_addr the physical mainstore address of the
|
|
* start of the HOMER image,
|
|
* @param[in] i_occ_common_addr the physical mainstore address of the
|
|
* OCC common area, 8MB, used for
|
|
* OCC-OCC communication (1 per node)
|
|
* @param[in] i_mode selects initial load vs concurrent
|
|
* reloads
|
|
* HBRT_PM_LOAD:
|
|
* load all lids/sections from scratch,
|
|
* preserve nothing
|
|
* HBRT_PM_RELOAD:
|
|
* reload all lids/sections,
|
|
* but preserve runtime updates
|
|
* @return 0 on success else return code
|
|
* @platform FSP, OpenPOWER
|
|
*/
|
|
int (*load_pm_complex)(uint64_t i_chip,
|
|
uint64_t i_homer_addr,
|
|
uint64_t i_occ_common_addr,
|
|
uint32_t i_mode);
|
|
|
|
/**
|
|
* @brief Start OCC/HCODE on the specified chip
|
|
* @param[in] i_chip the HW chip id
|
|
* @return 0 on success else return code
|
|
* @platform FSP, OpenPOWER
|
|
*/
|
|
int (*start_pm_complex)(uint64_t i_chip);
|
|
|
|
/**
|
|
* @brief Reset OCC/HCODE on the specified chip
|
|
* @param[in] i_chip the HW chip id
|
|
* @return 0 on success else return code
|
|
* @platform FSP, OpenPOWER
|
|
*/
|
|
int (*reset_pm_complex)(uint64_t i_chip);
|
|
|
|
/**
|
|
* @brief Query the IPOLL event mask supported by HBRT
|
|
*
|
|
* @details This call allows the wrapper application to query
|
|
* the ipoll event mask to set when the HBRT instance is running. Bits
|
|
* that are *set* in this bitmask represent events that will be
|
|
* forwarded to the handle_attn() callback.
|
|
*
|
|
* @return The IPOLL event bits to enable during HBRT execution
|
|
* @platform FSP, OpenPOWER
|
|
*/
|
|
uint64_t (*get_ipoll_events)(void);
|
|
|
|
/**
|
|
* @brief Receive an async notification from firmware
|
|
* @param[in] i_len length of notification data
|
|
* @param[in] i_data notification data
|
|
* @platform FSP, OpenPOWER
|
|
*/
|
|
void (*firmware_notify)(uint64_t len, void *data);
|
|
|
|
/**
|
|
* @brief Prepare for HBRT concurrent code update
|
|
*
|
|
* @details This call allows the Host to inform HBRT that a concurrent
|
|
* code update has been initiated. HBRT then prepares updated targeting
|
|
* data for use by the updated HBRT code.
|
|
*
|
|
* @return 0 on success else return code
|
|
* @platform FSP
|
|
*/
|
|
int (*prepare_hbrt_update)( void );
|
|
|
|
|
|
/* Reserve some space for future growth. */
|
|
void (*reserved[21])(void);
|
|
};
|