150 lines
3.6 KiB
C
150 lines
3.6 KiB
C
/* Copyright 2014-2016 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* imitations under the License.
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <time.h>
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#include "xscom.h"
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#define DBG(fmt...) do { if (verbose) printf(fmt); } while(0)
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#define ERR(fmt...) do { fprintf(stderr, fmt); } while(0)
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#define OCB_PIB_BASE_P8 0x0006B000
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#define OCB_PIB_BASE_P9 0x0006D000
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#define OCBCSR0 0x11
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#define OCBCSR0_AND 0x12
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#define OCBCSR0_OR 0x13
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#define OCB_STREAM_MODE PPC_BIT(4)
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#define OCB_STREAM_TYPE PPC_BIT(5)
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#define OCBAR0 0x10
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#define OCBDR0 0x15
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#define PVR_TYPE_P8E 0x004b /* Murano */
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#define PVR_TYPE_P8 0x004d /* Venice */
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#define PVR_TYPE_P8NVL 0x004c /* Naples */
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#define PVR_TYPE_P9 0x004e
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#define PVR_TYPE_P9P 0x004f /* Axone */
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#ifdef __powerpc__
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static uint64_t get_xscom_base(void)
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{
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unsigned int pvr;
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asm volatile("mfpvr %0" : "=r" (pvr));
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switch (pvr >> 16) {
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case PVR_TYPE_P9:
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case PVR_TYPE_P9P:
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return OCB_PIB_BASE_P9;
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case PVR_TYPE_P8E:
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case PVR_TYPE_P8:
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case PVR_TYPE_P8NVL:
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return OCB_PIB_BASE_P8;
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}
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ERR("Unknown processor, exiting\n");
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exit(1);
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return 0;
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}
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#else
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/* Just so it compiles on x86 */
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static uint64_t get_xscom_base(void) { return 0; }
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#endif
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int sram_read(uint32_t chip_id, int chan, uint32_t addr, uint64_t *val)
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{
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uint64_t sdat, base = get_xscom_base();
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uint32_t coff = chan * 0x20;
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int rc;
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/* Read for debug purposes */
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rc = xscom_read(chip_id, base + OCBCSR0 + coff, &sdat);
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if (rc) {
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ERR("xscom OCBCSR0 read error %d\n", rc);
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return -1;
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}
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/* Create an AND mask to clear bit 4 and 5 and poke the AND register */
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sdat = ~(OCB_STREAM_MODE | OCB_STREAM_TYPE);
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rc = xscom_write(chip_id, base + OCBCSR0_AND + coff, sdat);
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if (rc) {
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ERR("xscom OCBCSR0_AND write error %d\n", rc);
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return -1;
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}
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sdat = ((uint64_t)addr) << 32;
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rc = xscom_write(chip_id, base + OCBAR0 + coff, sdat);
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if (rc) {
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ERR("xscom OCBAR0 write error %d\n", rc);
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return -1;
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}
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rc = xscom_read(chip_id, base + OCBDR0 + coff, val);
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if (rc) {
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ERR("xscom OCBDR0 read error %d\n", rc);
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return -1;
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}
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return 0;
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}
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int sram_write(uint32_t chip_id, int chan, uint32_t addr, uint64_t val)
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{
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uint64_t sdat, base = get_xscom_base();
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uint32_t coff = chan * 0x20;
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int rc;
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#if 0
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if (dummy) {
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printf("[dummy] write chip %d OCC sram 0x%08x = %016lx\n",
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chip_id, addr, val);
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return 0;
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}
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#endif
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/* Read for debug purposes */
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rc = xscom_read(chip_id, base + OCBCSR0 + coff, &sdat);
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if (rc) {
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ERR("xscom OCBCSR0 read error %d\n", rc);
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return -1;
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}
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/* Create an AND mask to clear bit 4 and 5 and poke the AND register */
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sdat = ~(OCB_STREAM_MODE | OCB_STREAM_TYPE);
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rc = xscom_write(chip_id, base + OCBCSR0_AND + coff, sdat);
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if (rc) {
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ERR("xscom OCBCSR0_AND write error %d\n", rc);
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return -1;
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}
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sdat = ((uint64_t)addr) << 32;
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rc = xscom_write(chip_id, base + OCBAR0 + coff, sdat);
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if (rc) {
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ERR("xscom OCBAR0 write error %d\n", rc);
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return -1;
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}
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rc = xscom_write(chip_id, base + OCBDR0 + coff, val);
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if (rc) {
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ERR("xscom OCBDR0 write error %d\n", rc);
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return -1;
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}
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return 0;
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}
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