344 lines
9 KiB
C
344 lines
9 KiB
C
/* Copyright 2013-2014 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <skiboot.h>
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#include "spira.h"
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#include <cpu.h>
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#include <fsp.h>
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#include <opal.h>
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#include <ccan/str/str.h>
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#include <device.h>
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#include <types.h>
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#include "hdata.h"
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#define PACA_MAX_THREADS 4
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static unsigned int paca_index(const struct HDIF_common_hdr *paca)
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{
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void *start = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG);
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return ((void *)paca - start)
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/ be32_to_cpu(spira.ntuples.paca.alloc_len);
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}
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static struct dt_node *add_cpu_node(struct dt_node *cpus,
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const struct HDIF_common_hdr *paca,
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const struct sppaca_cpu_id *id,
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bool okay)
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{
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const struct sppaca_cpu_timebase *timebase;
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const struct sppaca_cpu_cache *cache;
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const struct sppaca_cpu_attr *attr;
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struct dt_node *cpu;
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u32 no, size, ve_flags, l2_phandle, chip_id;
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/* We use the process_interrupt_line as the res id */
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no = be32_to_cpu(id->process_interrupt_line);
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ve_flags = be32_to_cpu(id->verify_exists_flags);
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prlog(PR_INFO, "CPU[%i]: PIR=%i RES=%i %s %s(%u threads)\n",
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paca_index(paca), be32_to_cpu(id->pir), no,
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ve_flags & CPU_ID_PACA_RESERVED
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? "**RESERVED**" : cpu_state(ve_flags),
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ve_flags & CPU_ID_SECONDARY_THREAD
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? "[secondary] " :
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(be32_to_cpu(id->pir) == boot_cpu->pir ? "[boot] " : ""),
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((ve_flags & CPU_ID_NUM_SECONDARY_THREAD_MASK)
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>> CPU_ID_NUM_SECONDARY_THREAD_SHIFT) + 1);
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timebase = HDIF_get_idata(paca, SPPACA_IDATA_TIMEBASE, &size);
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if (!timebase || size < sizeof(*timebase)) {
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prerror("CPU[%i]: bad timebase size %u @ %p\n",
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paca_index(paca), size, timebase);
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return NULL;
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}
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cache = HDIF_get_idata(paca, SPPACA_IDATA_CACHE_SIZE, &size);
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if (!cache || size < sizeof(*cache)) {
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prerror("CPU[%i]: bad cache size %u @ %p\n",
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paca_index(paca), size, cache);
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return NULL;
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}
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cpu = add_core_common(cpus, cache, timebase, no, okay);
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/* Core attributes */
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attr = HDIF_get_idata(paca, SPPACA_IDATA_CPU_ATTR, &size);
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if (attr)
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add_core_attr(cpu, be32_to_cpu(attr->attr));
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/* Add cache info */
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l2_phandle = add_core_cache_info(cpus, cache, no, okay);
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dt_add_property_cells(cpu, "l2-cache", l2_phandle);
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/* We append the secondary cpus in __cpu_parse */
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dt_add_property_cells(cpu, "ibm,ppc-interrupt-server#s", no);
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dt_add_property_cells(cpu, DT_PRIVATE "hw_proc_id",
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be32_to_cpu(id->hardware_proc_id));
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dt_add_property_cells(cpu, "ibm,pir", be32_to_cpu(id->pir));
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chip_id = pcid_to_chip_id(be32_to_cpu(id->processor_chip_id));
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dt_add_property_cells(cpu, "ibm,chip-id", chip_id);
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return cpu;
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}
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static struct dt_node *find_cpu_by_hardware_proc_id(struct dt_node *root,
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u32 hw_proc_id)
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{
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struct dt_node *i;
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dt_for_each_node(root, i) {
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const struct dt_property *prop;
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if (!dt_has_node_property(i, "device_type", "cpu"))
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continue;
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prop = dt_find_property(i, DT_PRIVATE "hw_proc_id");
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if (!prop)
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return NULL;
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if (be32_to_cpu(*(be32 *)prop->prop) == hw_proc_id)
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return i;
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}
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return NULL;
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}
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/* Note that numbers are small. */
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static void add_be32_sorted(__be32 arr[], __be32 new, unsigned num)
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{
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unsigned int i;
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/* Walk until we find where we belong (insertion sort). */
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for (i = 0; i < num; i++) {
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if (be32_to_cpu(new) < be32_to_cpu(arr[i])) {
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__be32 tmp = arr[i];
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arr[i] = new;
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new = tmp;
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}
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}
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arr[i] = new;
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}
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static void add_xics_icps(void)
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{
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struct dt_node *cpu;
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unsigned int i;
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u64 reg[PACA_MAX_THREADS * 2];
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struct dt_node *icp;
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dt_for_each_node(dt_root, cpu) {
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u32 irange[2], size, pir;
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const struct dt_property *intsrv;
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const struct HDIF_common_hdr *paca;
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u64 ibase;
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unsigned int num_threads;
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bool found = false;
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if (!dt_has_node_property(cpu, "device_type", "cpu"))
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continue;
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intsrv = dt_find_property(cpu, "ibm,ppc-interrupt-server#s");
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if (!intsrv)
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continue;
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pir = dt_prop_get_u32(cpu, "ibm,pir");
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/* Get ibase address */
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paca = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG);
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for_each_paca(paca) {
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const struct sppaca_cpu_id *id;
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id = HDIF_get_idata(paca, SPPACA_IDATA_CPU_ID, &size);
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if (!CHECK_SPPTR(id))
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continue;
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if (pir != be32_to_cpu(id->pir))
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continue;
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ibase = cleanup_addr(be64_to_cpu(id->ibase));
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found = true;
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break;
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}
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if (!found)
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return;
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num_threads = intsrv->len / sizeof(u32);
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assert(num_threads <= PACA_MAX_THREADS);
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icp = dt_new_addr(dt_root, "interrupt-controller", ibase);
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if (!icp)
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continue;
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dt_add_property_strings(icp, "compatible",
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"IBM,ppc-xicp",
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"IBM,power7-xicp");
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irange[0] = dt_property_get_cell(intsrv, 0); /* Index */
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irange[1] = num_threads; /* num servers */
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dt_add_property(icp, "ibm,interrupt-server-ranges",
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irange, sizeof(irange));
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dt_add_property(icp, "interrupt-controller", NULL, 0);
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dt_add_property_cells(icp, "#address-cells", 0);
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dt_add_property_string(icp, "device_type",
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"PowerPC-External-Interrupt-Presentation");
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for (i = 0; i < num_threads*2; i += 2) {
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reg[i] = ibase;
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/* One page is enough for a handful of regs. */
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reg[i+1] = 4096;
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ibase += reg[i+1];
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}
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dt_add_property(icp, "reg", reg, sizeof(reg));
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}
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}
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static bool __paca_parse(void)
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{
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const struct HDIF_common_hdr *paca;
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struct dt_node *cpus;
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paca = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG);
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if (!paca) {
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prerror("Invalid PACA (PCIA = %p)\n",
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ntuple_addr(&spira.ntuples.pcia));
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return false;
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}
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if (be32_to_cpu(spira.ntuples.paca.act_len) < sizeof(*paca)) {
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prerror("PACA: invalid size %u\n",
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be32_to_cpu(spira.ntuples.paca.act_len));
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return false;
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}
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cpus = dt_new(dt_root, "cpus");
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dt_add_property_cells(cpus, "#address-cells", 1);
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dt_add_property_cells(cpus, "#size-cells", 0);
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for_each_paca(paca) {
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const struct sppaca_cpu_id *id;
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u32 size, ve_flags;
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bool okay;
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id = HDIF_get_idata(paca, SPPACA_IDATA_CPU_ID, &size);
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/* The ID structure on Blade314 is only 0x54 long. We can
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* cope with it as we don't use all the additional fields.
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* The minimum size we support is 0x40
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*/
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if (!id || size < SPIRA_CPU_ID_MIN_SIZE) {
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prerror("CPU[%i]: bad id size %u @ %p\n",
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paca_index(paca), size, id);
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return false;
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}
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ve_flags = be32_to_cpu(id->verify_exists_flags);
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switch ((ve_flags&CPU_ID_VERIFY_MASK) >> CPU_ID_VERIFY_SHIFT) {
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case CPU_ID_VERIFY_USABLE_NO_FAILURES:
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case CPU_ID_VERIFY_USABLE_FAILURES:
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okay = true;
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break;
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default:
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okay = false;
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}
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prlog(PR_INFO, "CPU[%i]: PIR=%i RES=%i %s\n",
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paca_index(paca), be32_to_cpu(id->pir),
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be32_to_cpu(id->process_interrupt_line),
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okay ? "OK" : "UNAVAILABLE");
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/* Secondary threads don't get their own node. */
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if (ve_flags & CPU_ID_SECONDARY_THREAD)
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continue;
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if (!add_cpu_node(cpus, paca, id, okay))
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return false;
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}
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/* Now account for secondaries. */
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for_each_paca(paca) {
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const struct dt_property *prop;
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const struct sppaca_cpu_id *id;
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u32 size, state, num, ve_flags;
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struct dt_node *cpu;
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__be32 *new_prop;
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id = HDIF_get_idata(paca, 2, &size);
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if (!CHECK_SPPTR(id))
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continue;
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ve_flags = be32_to_cpu(id->verify_exists_flags);
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state = (ve_flags & CPU_ID_VERIFY_MASK) >> CPU_ID_VERIFY_SHIFT;
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switch (state) {
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case CPU_ID_VERIFY_USABLE_NO_FAILURES:
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case CPU_ID_VERIFY_USABLE_FAILURES:
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break;
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default:
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continue;
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}
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/* Only interested in secondary threads. */
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if (!(ve_flags & CPU_ID_SECONDARY_THREAD))
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continue;
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cpu = find_cpu_by_hardware_proc_id(cpus,
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be32_to_cpu(id->hardware_proc_id));
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if (!cpu) {
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prerror("CPU[%i]: could not find primary hwid %i\n",
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paca_index(paca),
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be32_to_cpu(id->hardware_proc_id));
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return false;
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}
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/* Add the cpu #. */
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prop = dt_find_property(cpu, "ibm,ppc-interrupt-server#s");
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if (!prop) {
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prerror("CPU[%i]: could not find mapping information\n",
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paca_index(paca));
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return false;
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}
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num = prop->len / sizeof(u32);
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new_prop = malloc((num + 1) * sizeof(u32));
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if (!new_prop) {
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prerror("Property allocation length %zu failed\n",
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(num + 1) * sizeof(u32));
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return false;
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}
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memcpy(new_prop, prop->prop, prop->len);
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add_be32_sorted(new_prop, id->process_interrupt_line, num);
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dt_del_property(cpu, (struct dt_property *)prop);
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dt_add_property(cpu, "ibm,ppc-interrupt-server#s",
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new_prop, (num + 1) * sizeof(__be32));
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free(new_prop);
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}
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/*
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* P7 and P8 use the XICS interrupt controller which has a per-core
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* interrupt controller node.
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*/
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if (proc_gen <= proc_gen_p8)
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add_xics_icps();
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return true;
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}
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int paca_parse(void)
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{
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if (!__paca_parse()) {
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prerror("CPU: Initial CPU parsing failed\n");
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return -1;
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}
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return 0;
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}
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