97 lines
2.2 KiB
C
97 lines
2.2 KiB
C
/* Copyright 2013-2014 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <io.h>
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#include <psi.h>
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#include <lock.h>
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#include <fsp.h>
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static void psi_tce_enable(struct psi *psi, bool enable)
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{
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void *addr;
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u64 val;
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switch (proc_gen) {
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case proc_gen_p8:
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case proc_gen_p9:
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addr = psi->regs + PSIHB_PHBSCR;
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break;
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default:
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prerror("%s: Unknown CPU type\n", __func__);
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return;
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}
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val = in_be64(addr);
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if (enable)
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val |= PSIHB_CR_TCE_ENABLE;
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else
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val &= ~PSIHB_CR_TCE_ENABLE;
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out_be64(addr, val);
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}
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/*
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* Configure the PSI interface for communicating with
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* an FSP, such as enabling the TCEs, FSP commands,
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* etc...
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*/
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void psi_init_for_fsp(struct psi *psi)
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{
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uint64_t reg;
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bool enable_tce = true;
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lock(&psi_lock);
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/* Disable and setup TCE base address */
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psi_tce_enable(psi, false);
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switch (proc_gen) {
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case proc_gen_p8:
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case proc_gen_p9:
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out_be64(psi->regs + PSIHB_TAR, PSI_TCE_TABLE_BASE |
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PSIHB_TAR_256K_ENTRIES);
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break;
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default:
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enable_tce = false;
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};
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/* Enable various other configuration register bits based
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* on what pHyp does. We keep interrupts disabled until
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* after the mailbox has been properly configured. We assume
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* basic stuff such as PSI link enable is already there.
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*
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* - FSP CMD Enable
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* - FSP MMIO Enable
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* - TCE Enable
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* - Error response enable
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*
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* Clear all other error bits
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*/
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if (!psi->active) {
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prerror("PSI: psi_init_for_fsp() called on inactive link!\n");
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unlock(&psi_lock);
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return;
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}
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reg = in_be64(psi->regs + PSIHB_CR);
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reg |= PSIHB_CR_FSP_CMD_ENABLE;
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reg |= PSIHB_CR_FSP_MMIO_ENABLE;
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reg |= PSIHB_CR_FSP_ERR_RSP_ENABLE;
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reg &= ~0x00000000ffffffffull;
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out_be64(psi->regs + PSIHB_CR, reg);
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psi_tce_enable(psi, enable_tce);
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unlock(&psi_lock);
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}
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