243 lines
6.4 KiB
C
243 lines
6.4 KiB
C
/* Copyright 2015 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <skiboot.h>
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#include <chip.h>
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#include <xscom.h>
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#include <io.h>
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#include <cpu.h>
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#include <nx.h>
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#include <vas.h>
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/* Configuration settings */
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#define CFG_842_FC_ENABLE (0x1f) /* enable all 842 functions */
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#define CFG_842_ENABLE (1) /* enable 842 engines */
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#define DMA_CSB_WR NX_DMA_CSB_WR_CI
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#define DMA_COMPLETION_MODE NX_DMA_COMPLETION_MODE_CI
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#define DMA_CPB_WR NX_DMA_CPB_WR_CI_PAD
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#define DMA_OUTPUT_DATA_WR NX_DMA_OUTPUT_DATA_WR_CI
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#define EE_1 (1) /* enable engine 842 1 */
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#define EE_0 (1) /* enable engine 842 0 */
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static int nx_cfg_842(u32 gcid, u64 xcfg)
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{
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u64 cfg, ci, ct;
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int rc, instance = gcid + 1;
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BUILD_ASSERT(MAX_CHIPS < NX_842_CFG_CI_MAX);
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rc = xscom_read(gcid, xcfg, &cfg);
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if (rc) {
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prerror("NX%d: ERROR: XSCOM 842 config read failure %d\n",
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gcid, rc);
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return rc;
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}
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ct = GETFIELD(NX_842_CFG_CT, cfg);
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if (!ct)
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prlog(PR_INFO, "NX%d: 842 CT set to %u\n", gcid, NX_CT_842);
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else if (ct == NX_CT_842)
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prlog(PR_INFO, "NX%d: 842 CT already set to %u\n",
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gcid, NX_CT_842);
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else
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prlog(PR_INFO, "NX%d: 842 CT already set to %u, "
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"changing to %u\n", gcid, (unsigned int)ct, NX_CT_842);
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ct = NX_CT_842;
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cfg = SETFIELD(NX_842_CFG_CT, cfg, ct);
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/* Coprocessor Instance must be shifted left.
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* See hw doc Section 5.5.1.
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*/
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ci = GETFIELD(NX_842_CFG_CI, cfg) >> NX_842_CFG_CI_LSHIFT;
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if (!ci)
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prlog(PR_INFO, "NX%d: 842 CI set to %d\n", gcid, instance);
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else if (ci == instance)
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prlog(PR_INFO, "NX%d: 842 CI already set to %u\n", gcid,
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(unsigned int)ci);
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else
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prlog(PR_INFO, "NX%d: 842 CI already set to %u, "
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"changing to %d\n", gcid, (unsigned int)ci, instance);
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ci = instance;
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cfg = SETFIELD(NX_842_CFG_CI, cfg, ci << NX_842_CFG_CI_LSHIFT);
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/* Enable all functions */
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cfg = SETFIELD(NX_842_CFG_FC_ENABLE, cfg, CFG_842_FC_ENABLE);
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cfg = SETFIELD(NX_842_CFG_ENABLE, cfg, CFG_842_ENABLE);
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rc = xscom_write(gcid, xcfg, cfg);
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if (rc)
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prerror("NX%d: ERROR: 842 CT %u CI %u config failure %d\n",
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gcid, (unsigned int)ct, (unsigned int)ci, rc);
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else
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prlog(PR_DEBUG, "NX%d: 842 Config 0x%016lx\n",
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gcid, (unsigned long)cfg);
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return rc;
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}
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static int nx_cfg_842_umac(struct dt_node *node, u32 gcid, u32 pb_base)
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{
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int rc;
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u64 umac_bar, umac_notify;
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struct dt_node *nx_node;
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static u32 nx842_tid = 1; /* tid counter within coprocessor type */
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nx_node = dt_new(node, "ibm,842-high-fifo");
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umac_bar = pb_base + NX_P9_842_HIGH_PRI_RX_FIFO_BAR;
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umac_notify = pb_base + NX_P9_842_HIGH_PRI_RX_FIFO_NOTIFY_MATCH;
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rc = nx_cfg_rx_fifo(nx_node, "ibm,p9-nx-842", "High", gcid,
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NX_CT_842, nx842_tid++, umac_bar,
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umac_notify);
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if (rc)
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return rc;
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nx_node = dt_new(node, "ibm,842-normal-fifo");
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umac_bar = pb_base + NX_P9_842_NORMAL_PRI_RX_FIFO_BAR;
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umac_notify = pb_base + NX_P9_842_NORMAL_PRI_RX_FIFO_NOTIFY_MATCH;
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rc = nx_cfg_rx_fifo(nx_node, "ibm,p9-nx-842", "Normal", gcid,
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NX_CT_842, nx842_tid++, umac_bar,
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umac_notify);
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return rc;
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}
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static int nx_cfg_842_dma(u32 gcid, u64 xcfg)
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{
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u64 cfg;
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int rc;
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rc = xscom_read(gcid, xcfg, &cfg);
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if (rc) {
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prerror("NX%d: ERROR: XSCOM DMA config read failure %d\n",
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gcid, rc);
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return rc;
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}
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if (proc_gen >= proc_gen_p8) {
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cfg = SETFIELD(NX_DMA_CFG_842_COMPRESS_PREFETCH, cfg,
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DMA_COMPRESS_PREFETCH);
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cfg = SETFIELD(NX_DMA_CFG_842_DECOMPRESS_PREFETCH, cfg,
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DMA_DECOMPRESS_PREFETCH);
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}
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cfg = SETFIELD(NX_DMA_CFG_842_COMPRESS_MAX_RR, cfg,
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DMA_COMPRESS_MAX_RR);
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cfg = SETFIELD(NX_DMA_CFG_842_DECOMPRESS_MAX_RR, cfg,
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DMA_DECOMPRESS_MAX_RR);
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cfg = SETFIELD(NX_DMA_CFG_842_SPBC, cfg,
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DMA_SPBC);
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if (proc_gen < proc_gen_p9) {
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cfg = SETFIELD(NX_DMA_CFG_842_CSB_WR, cfg,
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DMA_CSB_WR);
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cfg = SETFIELD(NX_DMA_CFG_842_COMPLETION_MODE, cfg,
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DMA_COMPLETION_MODE);
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cfg = SETFIELD(NX_DMA_CFG_842_CPB_WR, cfg,
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DMA_CPB_WR);
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cfg = SETFIELD(NX_DMA_CFG_842_OUTPUT_DATA_WR, cfg,
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DMA_OUTPUT_DATA_WR);
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}
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rc = xscom_write(gcid, xcfg, cfg);
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if (rc)
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prerror("NX%d: ERROR: DMA config failure %d\n", gcid, rc);
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else
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prlog(PR_DEBUG, "NX%d: DMA 0x%016lx\n", gcid,
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(unsigned long)cfg);
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return rc;
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}
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static int nx_cfg_842_ee(u32 gcid, u64 xcfg)
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{
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u64 cfg;
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int rc;
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rc = xscom_read(gcid, xcfg, &cfg);
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if (rc) {
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prerror("NX%d: ERROR: XSCOM EE config read failure %d\n",
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gcid, rc);
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return rc;
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}
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cfg = SETFIELD(NX_EE_CFG_CH1, cfg, EE_1);
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cfg = SETFIELD(NX_EE_CFG_CH0, cfg, EE_0);
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rc = xscom_write(gcid, xcfg, cfg);
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if (rc)
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prerror("NX%d: ERROR: Engine Enable failure %d\n", gcid, rc);
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else
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prlog(PR_DEBUG, "NX%d: Engine Enable 0x%016lx\n",
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gcid, (unsigned long)cfg);
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return rc;
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}
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void nx_enable_842(struct dt_node *node, u32 gcid, u32 pb_base)
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{
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u64 cfg_dma, cfg_842, cfg_ee;
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int rc;
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if (dt_node_is_compatible(node, "ibm,power8-nx")) {
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cfg_dma = pb_base + NX_P8_DMA_CFG;
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cfg_842 = pb_base + NX_P8_842_CFG;
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cfg_ee = pb_base + NX_P8_EE_CFG;
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} else {
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prerror("NX%d: ERROR: Unknown NX type!\n", gcid);
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return;
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}
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rc = nx_cfg_842_dma(gcid, cfg_dma);
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if (rc)
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return;
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rc = nx_cfg_842(gcid, cfg_842);
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if (rc)
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return;
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rc = nx_cfg_842_ee(gcid, cfg_ee);
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if (rc)
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return;
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prlog(PR_INFO, "NX%d: 842 Coprocessor Enabled\n", gcid);
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dt_add_property_cells(node, "ibm,842-coprocessor-type", NX_CT_842);
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dt_add_property_cells(node, "ibm,842-coprocessor-instance", gcid + 1);
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}
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void p9_nx_enable_842(struct dt_node *node, u32 gcid, u32 pb_base)
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{
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u64 cfg_dma, cfg_ee;
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int rc;
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cfg_dma = pb_base + NX_P9_DMA_CFG;
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cfg_ee = pb_base + NX_P9_EE_CFG;
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rc = nx_cfg_842_dma(gcid, cfg_dma);
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if (rc)
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return;
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rc = nx_cfg_842_umac(node, gcid, pb_base);
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if (rc)
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return;
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rc = nx_cfg_842_ee(gcid, cfg_ee);
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if (rc)
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return;
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prlog(PR_INFO, "NX%d: 842 Coprocessor Enabled\n", gcid);
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}
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