307 lines
8.5 KiB
C
307 lines
8.5 KiB
C
/* Copyright 2015 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <skiboot.h>
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#include <chip.h>
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#include <xscom.h>
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#include <io.h>
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#include <cpu.h>
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#include <nx.h>
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/* Configuration settings */
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#define CFG_SYM_FC_ENABLE (0) /* disable all sym functions */
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#define CFG_SYM_ENABLE (0) /* disable sym engines */
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#define CFG_ASYM_FC_ENABLE (0) /* disable all asym functions */
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#define CFG_ASYM_ENABLE (0) /* disable asym engines */
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#define CFG_CRB_IQ_SYM (0) /* don't use any extra input queues */
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#define CFG_CRB_IQ_ASYM (0) /* don't use any extra input queues */
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#define AES_SHA_MAX_RR (1) /* valid range: 1-8 */
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#define AES_SHA_CSB_WR NX_DMA_CSB_WR_PDMA
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#define AES_SHA_COMPLETION_MODE NX_DMA_COMPLETION_MODE_PDMA
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#define AES_SHA_CPB_WR NX_DMA_CPB_WR_DMA_NOPAD
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#define AES_SHA_OUTPUT_DATA_WR NX_DMA_OUTPUT_DATA_WR_DMA
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#define AMF_MAX_RR (1) /* valid range: 1-8 */
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#define AMF_CSB_WR NX_DMA_CSB_WR_PDMA
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#define AMF_COMPLETION_MODE NX_DMA_COMPLETION_MODE_PDMA
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#define AMF_CPB_WR (0) /* CPB WR not done with AMF */
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#define AMF_OUTPUT_DATA_WR NX_DMA_OUTPUT_DATA_WR_DMA
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#define EE_CH7 (0) /* disable engine AMF 3(P8) */
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#define EE_CH6 (0) /* disable engine AMF 2(P8) */
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#define EE_CH5 (0) /* disable engine AMF 1(P8) */
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#define EE_CH4 (0) /* disable engine SYM AMF 0(P8) */
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#define EE_CH3 (0) /* disable engine SYM 1 */
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#define EE_CH2 (0) /* disable engine SYM 0 */
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static int nx_cfg_sym(u32 gcid, u64 xcfg)
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{
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u64 cfg, ci, ct;
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int rc, instance = gcid + 1;
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BUILD_ASSERT(MAX_CHIPS < NX_SYM_CFG_CI_MAX);
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rc = xscom_read(gcid, xcfg, &cfg);
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if (rc) {
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prerror("NX%d: ERROR: XSCOM SYM config read failure %d\n",
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gcid, rc);
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return rc;
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}
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ct = GETFIELD(NX_SYM_CFG_CT, cfg);
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if (!ct)
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prlog(PR_INFO, "NX%d: SYM CT set to %u\n", gcid, NX_CT_SYM);
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else if (ct == NX_CT_SYM)
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prlog(PR_INFO, "NX%d: SYM CT already set to %u\n",
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gcid, NX_CT_SYM);
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else
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prlog(PR_INFO, "NX%d: SYM CT already set to %u, "
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"changing to %u\n", gcid, (unsigned int)ct, NX_CT_SYM);
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ct = NX_CT_SYM;
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cfg = SETFIELD(NX_SYM_CFG_CT, cfg, ct);
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/* Coprocessor Instance must be shifted left.
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* See hw doc Section 5.5.1.
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*/
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ci = GETFIELD(NX_SYM_CFG_CI, cfg) >> NX_SYM_CFG_CI_LSHIFT;
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if (!ci)
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prlog(PR_INFO, "NX%d: SYM CI set to %d\n", gcid, instance);
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else if (ci == instance)
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prlog(PR_INFO, "NX%d: SYM CI already set to %u\n", gcid,
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(unsigned int)ci);
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else
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prlog(PR_INFO, "NX%d: SYM CI already set to %u, "
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"changing to %d\n", gcid, (unsigned int)ci, instance);
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ci = instance;
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cfg = SETFIELD(NX_SYM_CFG_CI, cfg, ci << NX_SYM_CFG_CI_LSHIFT);
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cfg = SETFIELD(NX_SYM_CFG_FC_ENABLE, cfg, CFG_SYM_FC_ENABLE);
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cfg = SETFIELD(NX_SYM_CFG_ENABLE, cfg, CFG_SYM_ENABLE);
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rc = xscom_write(gcid, xcfg, cfg);
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if (rc)
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prerror("NX%d: ERROR: SYM CT %u CI %u config failure %d\n",
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gcid, (unsigned int)ct, (unsigned int)ci, rc);
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else
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prlog(PR_DEBUG, "NX%d: SYM Config 0x%016lx\n",
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gcid, (unsigned long)cfg);
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return rc;
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}
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static int nx_cfg_asym(u32 gcid, u64 xcfg)
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{
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u64 cfg, ci, ct;
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int rc, instance = gcid + 1;
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BUILD_ASSERT(MAX_CHIPS < NX_ASYM_CFG_CI_MAX);
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rc = xscom_read(gcid, xcfg, &cfg);
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if (rc) {
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prerror("NX%d: ERROR: XSCOM ASYM config read failure %d\n",
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gcid, rc);
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return rc;
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}
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ct = GETFIELD(NX_ASYM_CFG_CT, cfg);
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if (!ct)
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prlog(PR_INFO, "NX%d: ASYM CT set to %u\n",
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gcid, NX_CT_ASYM);
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else if (ct == NX_CT_ASYM)
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prlog(PR_INFO, "NX%d: ASYM CT already set to %u\n",
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gcid, NX_CT_ASYM);
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else
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prlog(PR_INFO, "NX%d: ASYM CT already set to %u, "
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"changing to %u\n", gcid, (unsigned int)ct, NX_CT_ASYM);
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ct = NX_CT_ASYM;
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cfg = SETFIELD(NX_ASYM_CFG_CT, cfg, ct);
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/* Coprocessor Instance must be shifted left.
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* See hw doc Section 5.5.1.
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*/
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ci = GETFIELD(NX_ASYM_CFG_CI, cfg) >> NX_ASYM_CFG_CI_LSHIFT;
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if (!ci)
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prlog(PR_INFO, "NX%d: ASYM CI set to %d\n", gcid, instance);
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else if (ci == instance)
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prlog(PR_INFO, "NX%d: ASYM CI already set to %u\n", gcid,
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(unsigned int)ci);
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else
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prlog(PR_INFO, "NX%d: ASYM CI already set to %u, "
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"changing to %d\n", gcid, (unsigned int)ci, instance);
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ci = instance;
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cfg = SETFIELD(NX_ASYM_CFG_CI, cfg, ci << NX_ASYM_CFG_CI_LSHIFT);
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cfg = SETFIELD(NX_ASYM_CFG_FC_ENABLE, cfg, CFG_ASYM_FC_ENABLE);
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cfg = SETFIELD(NX_ASYM_CFG_ENABLE, cfg, CFG_ASYM_ENABLE);
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rc = xscom_write(gcid, xcfg, cfg);
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if (rc)
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prerror("NX%d: ERROR: ASYM CT %u CI %u config failure %d\n",
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gcid, (unsigned int)ct, (unsigned int)ci, rc);
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else
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prlog(PR_DEBUG, "NX%d: ASYM Config 0x%016lx\n",
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gcid, (unsigned long)cfg);
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return rc;
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}
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static int nx_cfg_dma(u32 gcid, u64 xcfg)
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{
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u64 cfg;
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int rc;
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rc = xscom_read(gcid, xcfg, &cfg);
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if (rc) {
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prerror("NX%d: ERROR: XSCOM DMA config read failure %d\n",
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gcid, rc);
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return rc;
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}
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cfg = SETFIELD(NX_DMA_CFG_AES_SHA_MAX_RR, cfg,
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AES_SHA_MAX_RR);
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cfg = SETFIELD(NX_DMA_CFG_AES_SHA_CSB_WR, cfg,
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AES_SHA_CSB_WR);
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cfg = SETFIELD(NX_DMA_CFG_AES_SHA_COMPLETION_MODE, cfg,
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AES_SHA_COMPLETION_MODE);
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cfg = SETFIELD(NX_DMA_CFG_AES_SHA_CPB_WR, cfg,
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AES_SHA_CPB_WR);
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cfg = SETFIELD(NX_DMA_CFG_AES_SHA_OUTPUT_DATA_WR, cfg,
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AES_SHA_OUTPUT_DATA_WR);
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cfg = SETFIELD(NX_DMA_CFG_AMF_MAX_RR, cfg,
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AMF_MAX_RR);
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cfg = SETFIELD(NX_DMA_CFG_AMF_CSB_WR, cfg,
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AMF_CSB_WR);
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cfg = SETFIELD(NX_DMA_CFG_AMF_COMPLETION_MODE, cfg,
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AMF_COMPLETION_MODE);
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cfg = SETFIELD(NX_DMA_CFG_AMF_CPB_WR, cfg,
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AMF_CPB_WR);
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cfg = SETFIELD(NX_DMA_CFG_AMF_OUTPUT_DATA_WR, cfg,
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AMF_OUTPUT_DATA_WR);
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rc = xscom_write(gcid, xcfg, cfg);
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if (rc)
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prerror("NX%d: ERROR: DMA config failure %d\n", gcid, rc);
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else
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prlog(PR_DEBUG, "NX%d: DMA 0x%016lx\n", gcid,
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(unsigned long)cfg);
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return rc;
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}
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static int nx_cfg_iq(u32 gcid, u64 xcfg)
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{
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u64 cfg;
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int rc;
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rc = xscom_read(gcid, xcfg, &cfg);
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if (rc) {
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prerror("NX%d: ERROR: XSCOM CRB IQ config read failure %d\n",
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gcid, rc);
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return rc;
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}
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cfg = SETFIELD(NX_CRB_IQ_SYM, cfg, CFG_CRB_IQ_SYM);
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cfg = SETFIELD(NX_CRB_IQ_ASYM, cfg, CFG_CRB_IQ_ASYM);
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rc = xscom_write(gcid, xcfg, cfg);
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if (rc)
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prerror("NX%d: ERROR: CRB Input Queue failure %d\n", gcid, rc);
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else
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prlog(PR_DEBUG, "NX%d: CRB Input Queue 0x%016lx\n",
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gcid, (unsigned long)cfg);
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return rc;
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}
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static int nx_cfg_ee(u32 gcid, u64 xcfg)
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{
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u64 cfg;
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int rc;
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rc = xscom_read(gcid, xcfg, &cfg);
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if (rc) {
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prerror("NX%d: ERROR: XSCOM EE config read failure %d\n",
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gcid, rc);
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return rc;
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}
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cfg = SETFIELD(NX_EE_CFG_CH7, cfg, EE_CH7);
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cfg = SETFIELD(NX_EE_CFG_CH6, cfg, EE_CH6);
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cfg = SETFIELD(NX_EE_CFG_CH5, cfg, EE_CH5);
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cfg = SETFIELD(NX_EE_CFG_CH4, cfg, EE_CH4);
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cfg = SETFIELD(NX_EE_CFG_CH3, cfg, EE_CH3);
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cfg = SETFIELD(NX_EE_CFG_CH2, cfg, EE_CH2);
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rc = xscom_write(gcid, xcfg, cfg);
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if (rc)
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prerror("NX%d: ERROR: Engine Enable failure %d\n", gcid, rc);
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else
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prlog(PR_DEBUG, "NX%d: Engine Enable 0x%016lx\n",
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gcid, (unsigned long)cfg);
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return rc;
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}
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void nx_create_crypto_node(struct dt_node *node)
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{
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u32 gcid;
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u32 pb_base;
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u64 cfg_dma, cfg_sym, cfg_asym, cfg_iq, cfg_ee;
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int rc;
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gcid = dt_get_chip_id(node);
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pb_base = dt_get_address(node, 0, NULL);
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prlog(PR_INFO, "NX%d: Crypto at 0x%x\n", gcid, pb_base);
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if (dt_node_is_compatible(node, "ibm,power8-nx")) {
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cfg_dma = pb_base + NX_P8_DMA_CFG;
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cfg_sym = pb_base + NX_P8_SYM_CFG;
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cfg_asym = pb_base + NX_P8_ASYM_CFG;
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cfg_iq = pb_base + NX_P8_CRB_IQ;
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cfg_ee = pb_base + NX_P8_EE_CFG;
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} else if (dt_node_is_compatible(node, "ibm,power9-nx")) {
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prlog(PR_INFO, "NX%d: POWER9 nx-crypto not yet supported\n",
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gcid);
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return;
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} else {
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prerror("NX%d: ERROR: Unknown NX type!\n", gcid);
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return;
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}
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rc = nx_cfg_dma(gcid, cfg_dma);
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if (rc)
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return;
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rc = nx_cfg_sym(gcid, cfg_sym);
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if (rc)
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return;
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rc = nx_cfg_asym(gcid, cfg_asym);
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if (rc)
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return;
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rc = nx_cfg_iq(gcid, cfg_iq);
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if (rc)
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return;
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rc = nx_cfg_ee(gcid, cfg_ee);
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if (rc)
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return;
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prlog(PR_INFO, "NX%d: Crypto Coprocessors Disabled (not supported)\n", gcid);
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}
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