132 lines
3.5 KiB
C
132 lines
3.5 KiB
C
/* Copyright 2013-2015 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <skiboot.h>
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#include <xscom.h>
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#include <io.h>
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#include <cpu.h>
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#include <nx.h>
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#include <chip.h>
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#include <phys-map.h>
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#include <xscom-p9-regs.h>
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/*
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* On P9 the DARN instruction is used to access the HW RNG. There is still
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* an NX RNG BAR, but it is used to configure which NX a core will source
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* random numbers from rather than being a MMIO window.
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*/
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static void nx_init_p9_rng(uint32_t chip_id)
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{
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uint64_t bar, tmp;
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if (chip_quirk(QUIRK_NO_RNG))
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return;
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phys_map_get(chip_id, NX_RNG, 0, &bar, NULL);
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xscom_write(chip_id, P9X_NX_MMIO_BAR, bar | P9X_NX_MMIO_BAR_EN);
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/* Read config register for pace info */
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xscom_read(chip_id, P9X_NX_RNG_CFG, &tmp);
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prlog(PR_INFO, "NX RNG[%x] pace:%lli\n", chip_id, 0xffff & (tmp >> 2));
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}
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void nx_create_rng_node(struct dt_node *node)
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{
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u64 bar, cfg;
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u64 xbar, xcfg;
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u32 pb_base;
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u32 gcid;
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u64 rng_addr, rng_len, len, addr_mask;
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struct dt_node *rng;
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int rc;
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gcid = dt_get_chip_id(node);
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pb_base = dt_get_address(node, 0, NULL);
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if (dt_node_is_compatible(node, "ibm,power8-nx")) {
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xbar = pb_base + NX_P8_RNG_BAR;
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xcfg = pb_base + NX_P8_RNG_CFG;
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addr_mask = NX_P8_RNG_BAR_ADDR;
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} else if (dt_node_is_compatible(node, "ibm,power9-nx")) {
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nx_init_p9_rng(gcid);
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return;
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} else {
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prerror("NX%d: Unknown NX type!\n", gcid);
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return;
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}
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rc = xscom_read(gcid, xbar, &bar); /* Get RNG BAR */
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if (rc) {
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prerror("NX%d: ERROR: XSCOM RNG BAR read failure %d\n",
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gcid, rc);
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return;
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}
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rc = xscom_read(gcid, xcfg, &cfg); /* Get RNG CFG */
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if (rc) {
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prerror("NX%d: ERROR: XSCOM RNG config read failure %d\n",
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gcid, rc);
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return;
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}
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/*
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* We mask in-place rather than using GETFIELD for the base address
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* as we happen to *know* that it's properly aligned in the register.
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*
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* FIXME? Always assusme BAR gets a valid address from FSP
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*/
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rng_addr = bar & addr_mask;
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len = GETFIELD(NX_RNG_BAR_SIZE, bar);
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if (len > 4) {
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prerror("NX%d: Corrupted bar size %lld\n", gcid, len);
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return;
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}
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rng_len = (u64[]){ 0x1000, /* 4K */
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0x10000, /* 64K */
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0x400000000UL, /* 16G*/
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0x100000, /* 1M */
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0x1000000 /* 16M */} [len];
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prlog(PR_INFO, "NX%d: RNG BAR set to 0x%016llx..0x%016llx\n",
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gcid, rng_addr, rng_addr + rng_len - 1);
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/* RNG must be enabled before MMIO is enabled */
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rc = xscom_write(gcid, xcfg, cfg | NX_RNG_CFG_ENABLE);
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if (rc) {
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prerror("NX%d: ERROR: XSCOM RNG config enable failure %d\n",
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gcid, rc);
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return;
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}
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/* The BAR needs to be enabled too */
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rc = xscom_write(gcid, xbar, bar | NX_RNG_BAR_ENABLE);
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if (rc) {
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prerror("NX%d: ERROR: XSCOM RNG config enable failure %d\n",
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gcid, rc);
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return;
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}
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rng = dt_new_addr(dt_root, "hwrng", rng_addr);
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if (!rng)
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return;
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dt_add_property_strings(rng, "compatible", "ibm,power-rng");
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dt_add_property_u64s(rng, "reg", rng_addr, rng_len);
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dt_add_property_cells(rng, "ibm,chip-id", gcid);
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}
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