171 lines
6.5 KiB
C
171 lines
6.5 KiB
C
/* Copyright 2016 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* In-Memory Collection (IMC) Counters :
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* Power9 has IMC instrumentation support with which several
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* metrics of the platform can be monitored. These metrics
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* are backed by the Performance Monitoring Units (PMUs) and
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* their counters. IMC counters can be configured to run
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* continuously from startup to shutdown and data from these
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* counters are fed directly into a pre-defined memory location.
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*
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* Depending on the counters' location and monitoring engines,
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* they are classified into three domains :
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* Nest IMC, core IMC and thread IMC.
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*
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* Nest Counters :
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* Nest counters are per-chip counters and can help in providing utilisation
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* metrics like memory bandwidth, Xlink/Alink bandwidth etc.
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* A microcode in OCC programs the nest counters and moves counter values to
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* per chip HOMER region in a fixed offset for each unit. Engine has a
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* control block structure for communication with Hypervisor(Host OS).
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*/
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#ifndef __IMC_H
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#define __IMC_H
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/*
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* Control Block structure offset in HOMER nest Region
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*/
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#define P9_CB_STRUCT_OFFSET 0x1BFC00
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#define P9_CB_STRUCT_CMD 0x1BFC08
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#define P9_CB_STRUCT_SPEED 0x1BFC10
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/* Nest microcode Status */
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#define NEST_IMC_PAUSE 0x2
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#define NEST_IMC_RUNNING 0x1
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#define NEST_IMC_NOP 0
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/*
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* Control Block Structure:
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*
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* Name Producer Consumer Values Desc
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* IMCRunStatus IMC Code Hypervisor 0 Initializing
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* (Host OS) 1 Running
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* 2 Paused
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*
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* IMCCommand Hypervisor IMC Code 0 NOP
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* 1 Resume
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* 2 Pause
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* 3 Clear and Restart
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*
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* IMCCollection Hypervisor IMC Code 0 128us
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* Speed 1 256us
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* 2 1ms
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* 3 4ms
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* 4 16ms
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* 5 64ms
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* 6 256ms
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* 7 1000ms
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*
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* IMCAvailability IMC Code Hypervisor - 64-bit value describes
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* the Vector Nest PMU
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* availability.
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* Bits 0-47 denote the
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* availability of 48 different
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* nest units.
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* Rest are reserved. For details
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* regarding which bit belongs
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* to which unit, see
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* include/nest_imc.h.
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* If a bit is unset (0),
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* then, the corresponding unit
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* is unavailable. If its set (1),
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* then, the unit is available.
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*
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* IMCRun Mode Hypervisor IMC Code 0 Normal Mode (Monitor Mode)
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* 1 Debug Mode 1 (PB)
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* 2 Debug Mode 2 (MEM)
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* 3 Debug Mode 3 (PCIE)
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* 4 Debug Mode 4 (CAPP)
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* 5 Debug Mode 5 (NPU 1)
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* 6 Debug Mode 6 (NPU 2)
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*/
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struct imc_chip_cb
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{
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u64 imc_chip_run_status;
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u64 imc_chip_command;
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u64 imc_chip_collection_speed;
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u64 imc_chip_avl_vector;
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u64 imc_chip_run_mode;
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};
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/* Size of IMC dtb LID (256KBytes) */
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#define MAX_DECOMPRESSED_IMC_DTB_SIZE 0x40000
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#define MAX_COMPRESSED_IMC_DTB_SIZE 0x40000
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/* IMC device types */
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#define IMC_COUNTER_CHIP 0x10
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#define IMC_COUNTER_CORE 0x4
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#define IMC_COUNTER_THREAD 0x1
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#define IMC_COUNTER_TRACE 0x2
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/*
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* Nest IMC operations
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*/
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#define NEST_IMC_ENABLE 0x1
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#define NEST_IMC_DISABLE 0x2
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/*
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* Core IMC SCOMs
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*/
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#define CORE_IMC_EVENT_MASK_ADDR 0x20010AA8ull
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#define CORE_IMC_EVENT_MASK 0x0402010000000000ull
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#define CORE_IMC_PDBAR_MASK 0x0003ffffffffe000ull
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#define CORE_IMC_HTM_MODE_ENABLE 0xE800000000000000ull
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#define CORE_IMC_HTM_MODE_DISABLE 0xE000000000000000ull
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/*
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* Trace IMC SCOMs for IMC trace-mode.
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*
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* TRACE_IMC_SCOM layout
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*
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* 0 4 8 12 16 20 24 28
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* [ ] [ CPMC_LOAD [2:33]
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* |
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* *SAMPSEL
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*
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* 32 36 40 44 48 52 56 60
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* ] [ ] [ ] [ ] [ RESERVED [51:63] ]
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* | | |
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* *CPMC1SEL *CPMC2SEL *BUFFERSIZE
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*/
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#define TRACE_IMC_ADDR 0x20010AA9ull
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#define TRACE_IMC_SAMPLESEL(x) ((uint64_t)x << 62)
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#define TRACE_IMC_CPMC_LOAD(x) ((0xffffffff - (uint64_t)x) << 30)
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#define TRACE_IMC_CPMC1SEL(x) ((uint64_t)x << 23)
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#define TRACE_IMC_CPMC2SEL(x) ((uint64_t)x << 16)
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#define TRACE_IMC_BUFFERSIZE(x) ((uint64_t)x << 13)
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#define TRACE_IMC_SCOM(a, b, c, d, e) (TRACE_IMC_SAMPLESEL(a) |\
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TRACE_IMC_CPMC_LOAD(b) |\
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TRACE_IMC_CPMC1SEL(c) |\
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TRACE_IMC_CPMC2SEL(d) |\
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TRACE_IMC_BUFFERSIZE(e))
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void imc_init(void);
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void imc_catalog_preload(void);
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void imc_decompress_catalog(void);
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#define MAX_NEST_COMBINED_UNITS 4
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struct combined_units_node {
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const char *name;
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u64 unit1;
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u64 unit2;
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};
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#endif /* __IMC_H */
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