237 lines
7.4 KiB
C
237 lines
7.4 KiB
C
/* Copyright 2013-2015 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __NPU_REGS_H
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#define __NPU_REGS_H
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/* Size of a single link */
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#define NPU_LINK_SIZE 0x40
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/* Link registers */
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#define NX_PB_ERR_RPT_0 0x00
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#define NX_PB_ERR_RPT_1 0x01
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#define NX_MMIO_BAR_0 0x02
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#define NX_MMIO_BAR_1 0x03
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#define NX_MMIO_BAR_BASE PPC_BITMASK(14,51)
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#define NX_MMIO_BAR_ENABLE PPC_BIT(52)
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#define NX_MMIO_BAR_SIZE PPC_BITMASK(53,55)
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#define NX_NODAL_BAR0 0x04
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#define NX_NODAL_BAR1 0x05
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#define NX_NODAL_BAR_ENABLE PPC_BIT(0)
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#define NX_NODAL_BAR_MASK PPC_BITMASK(1,14)
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#define NX_NODAL_BAR_BASE PPC_BITMASK(15,32)
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#define NX_GROUP_BAR0 0x06
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#define NX_GROUP_BAR1 0x07
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#define NX_GROUP_BAR_ENABLE PPC_BIT(0)
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#define NX_GROUP_BAR_MASK PPC_BITMASK(1,14)
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#define NX_GROUP_BAR_BASE PPC_BITMASK(15,32)
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#define NX_EPSILON_COUN 0x08
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#define NX_EPSILON_COUN_DISABLE PPC_BIT(6)
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#define NX_MISC_CONTROL 0x09
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#define NX_PB_DEBUG 0x0a
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#define NX_PB_ECC 0x0b
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#define NX_DEBUG_SNAPSHOT_0 0x0c
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#define NX_DEBUG_SNAPSHOT_1 0x0d
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#define NX_CS_CTL 0x0e
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#define NX_CONFIG_CQ 0x0f
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#define NX_MRBO0 0x10
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#define NX_MRBO1 0x11
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#define NX_AS_CMD_CFG 0x12
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#define NX_NP_BUID 0x13
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#define NP_BUID_ENABLE PPC_BIT(0)
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#define NP_BUID_BASE PPC_BITMASK(1,15)
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#define NP_IRQ_LEVELS PPC_BITMASK(16,23)
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#define NP_BUID_MASK PPC_BITMASK(24,32)
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#define NX_TL_CMD_CR 0x20
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#define NX_TL_CMD_D_CR 0x21
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#define NX_TL_RSP_CR 0x22
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#define NX_TL_RSP_D_CR 0x23
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#define NX_DL_REG_ADDR 0x24
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#define NX_DL_REG_DATA 0x25
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#define NX_NTL_CONTROL 0x26
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#define NX_NTL_PMU_CONTROL 0x27
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#define NX_NTL_PMU_COUNT 0x28
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#define NX_NTL_ER_HOLD 0x29
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#define NX_NTL_FST_ERR 0x2a
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#define NX_NTL_ECC 0x2b
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#define NX_NTL_FST_MSK 0x2c
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/* NP AT register */
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#define NX_FIR 0x00
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#define NX_FIR_CLEAR 0x01
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#define NX_FIR_SET 0x02
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#define NX_FIR_MASK 0x03
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#define NX_FIR_MASK_CLR 0x04
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#define NX_FIR_MASK_SET 0x05
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#define NX_FIR_ACTION0 0x06
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#define NX_FIR_ACTION1 0x07
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#define NX_FIR_WOF 0x08
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#define NX_AT_PMU_CTRL 0x26
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#define NX_AT_PMU_CNT 0x27
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#define NX_AT_ERR_HOLD 0x28
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#define NX_AT_ERR_HOLD_RESET PPC_BIT(63)
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#define NX_AT_DEBUG 0x29
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#define NX_AT_ECC 0x2a
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#define NX_BAR 0x2b
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/* AT MMIO registers */
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#define NPU_LSI_SOURCE_ID 0x00100
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#define NPU_LSI_SRC_ID_BASE PPC_BITMASK(5,11)
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#define NPU_DMA_CHAN_STATUS 0x00110
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#define NPU_INTREP_TIMER 0x001f8
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#define NPU_DMARD_SYNC 0x00200
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#define NPU_DMARD_SYNC_START_RD PPC_BIT(0)
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#define NPU_DMARD_SYNC_RD PPC_BIT(1)
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#define NPU_DMARD_SYNC_START_WR PPC_BIT(2)
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#define NPU_DMARD_SYNC_WR PPC_BIT(3)
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#define NPU_TCE_KILL 0x00210
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#define NPU_IODA_ADDR 0x00220
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#define NPU_IODA_AD_AUTOINC PPC_BIT(0)
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#define NPU_IODA_AD_TSEL PPC_BITMASK(11,15)
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#define NPU_IODA_AD_TADR PPC_BITMASK(54,63)
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#define NPU_IODA_DATA0 0x00228
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#define NPU_XIVE_UPD 0x00248
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#define NPU_GEN_CAP 0x00250
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#define NPU_TCE_CAP 0x00258
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#define NPU_INT_CAP 0x00260
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#define NPU_EEH_CAP 0x00268
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#define NPU_VR 0x00800
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#define NPU_CTRLR 0x00810
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#define NPU_TCR 0x00880
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#define NPU_Q_DMA_R 0x00888
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#define NPU_AT_ESR 0x00c80
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#define NPU_AT_FESR 0x00c88
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#define NPU_AT_LR_ER 0x00c98
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#define NPU_AT_SI_ER 0x00ca0
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#define NPU_AT_FR_ER 0x00ca8
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#define NPU_AT_FE_ER 0x00cb0
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#define NPU_AT_ESMR 0x00cd0
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#define NPU_AT_FESMR 0x00cd8
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#define NPU_AT_I_LR0 0x00d00
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#define NPU_AT_I_LR1 0x00d08
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#define NPU_AT_I_LR2 0x00d10
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#define NPU_AT_I_LR3 0x00d18
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/* AT */
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#define NPU_AT_SCOM_OFFSET 0x180
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/* NTL */
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#define TL_CMD_CR 0x10000
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#define TL_CMD_D_CR 0x10008
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#define TL_RSP_CR 0x10010
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#define TL_RSP_D_CR 0x10018
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#define NTL_CONTROL 0x10020
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#define NTL_CONTROL_RESET PPC_BIT(0)
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/* IODA tables */
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#define NPU_IODA_TBL_LIST 1
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#define NPU_IODA_TBL_LXIVT 2
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#define NPU_IODA_TBL_PCT 4
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#define NPU_IODA_TBL_PESTB 8
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#define NPU_IODA_TBL_TVT 9
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#define NPU_IODA_TBL_TCD 10
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#define NPU_IODA_TBL_TDR 11
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#define NPU_IODA_TBL_PESTB_ADDR 12
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#define NPU_IODA_TBL_EA 16
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/* LXIVT */
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#define NPU_IODA_LXIVT_SERVER PPC_BITMASK(8,23)
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#define NPU_IODA_LXIVT_PRIORITY PPC_BITMASK(24,31)
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/* PCT */
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#define NPU_IODA_PCT_LINK_ENABLED PPC_BIT(0)
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#define NPU_IODA_PCT_PE PPC_BITMASK(2,3)
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/* TVT */
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#define NPU_IODA_TVT_TTA PPC_BITMASK(0,47)
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#define NPU_IODA_TVT_LEVELS PPC_BITMASK(48,50)
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#define NPU_IODA_TVE_1_LEVEL 0
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#define NPU_IODA_TVE_2_LEVELS 1
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#define NPU_IODA_TVE_3_LEVELS 2
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#define NPU_IODA_TVE_4_LEVELS 3
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#define NPU_IODA_TVT_SIZE PPC_BITMASK(51,55)
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#define NPU_IODA_TVT_PSIZE PPC_BITMASK(59,63)
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/* NDL Registers */
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#define NDL_STATUS 0xfff0
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#define NDL_CONTROL 0xfff4
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/* BAR Sizes */
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#define NX_MMIO_PL_SIZE 0x200000
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#define NX_MMIO_AT_SIZE 0x10000
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#define NX_MMIO_DL_SIZE 0x20000
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/* Translates a PHY SCOM address to an MMIO offset */
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#define PL_MMIO_ADDR(reg) (((reg >> 32) & 0xfffffull) << 1)
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/* PHY register scom offsets & fields */
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#define RX_PR_CNTL_PL 0x0002180000000000UL
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#define RX_PR_RESET PPC_BIT(63)
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#define TX_MODE1_PL 0x0004040000000000UL
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#define TX_LANE_PDWN PPC_BIT(48)
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#define TX_MODE2_PL 0x00040c0000000000UL
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#define TX_RXCAL PPC_BIT(57)
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#define TX_UNLOAD_CLK_DISABLE PPC_BIT(56)
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#define TX_CNTL_STAT2 0x00041c0000000000UL
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#define TX_FIFO_INIT PPC_BIT(48)
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#define RX_BANK_CONTROLS 0x0000f80000000000UL
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#define RX_LANE_ANA_PDWN PPC_BIT(54)
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#define RX_MODE 0x0002000000000000UL
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#define RX_LANE_DIG_PDWN PPC_BIT(48)
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#define RX_PR_MODE 0x0002100000000000UL
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#define RX_PR_PHASE_STEP PPC_BITMASK(60, 63)
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#define RX_A_DAC_CNTL 0x0000080000000000UL
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#define RX_PR_IQ_RES_SEL PPC_BITMASK(58, 60)
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#define RX_LANE_BUSY_VEC_0_15 0x000b000000000000UL
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#define TX_FFE_TOTAL_2RSTEP_EN 0x000c240000000000UL
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#define TX_FFE_TOTAL_ENABLE_P_ENC PPC_BITMASK(49,55)
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#define TX_FFE_TOTAL_ENABLE_N_ENC PPC_BITMASK(57,63)
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#define TX_FFE_PRE_2RSTEP_SEL 0x000c2c0000000000UL
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#define TX_FFE_PRE_P_SEL_ENC PPC_BITMASK(51,54)
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#define TX_FFE_PRE_N_SEL_ENC PPC_BITMASK(59,62)
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#define TX_FFE_MARGIN_2RSTEP_SEL 0x000c34000000000UL
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#define TX_FFE_MARGIN_PU_P_SEL_ENC PPC_BITMASK(51,55)
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#define TX_FFE_MARGIN_PD_N_SEL_ENC PPC_BITMASK(59,63)
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#define TX_IORESET_VEC_0_15 0x000d2c0000000000UL
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#define TX_IMPCAL_PB 0x000f040000000000UL
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#define TX_ZCAL_REQ PPC_BIT(49)
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#define TX_ZCAL_DONE PPC_BIT(50)
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#define TX_ZCAL_ERROR PPC_BIT(51)
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#define TX_IMPCAL_NVAL_PB 0x000f0c0000000000UL
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#define TX_ZCAL_N PPC_BITMASK(48,56)
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#define TX_IMPCAL_PVAL_PB 0x000f140000000000UL
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#define TX_ZCAL_P PPC_BITMASK(48,56)
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#define RX_EO_STEP_CNTL_PG 0x0008300000000000UL
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#define RX_EO_ENABLE_LATCH_OFFSET_CAL PPC_BIT(48)
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#define RX_EO_ENABLE_CM_COARSE_CAL PPC_BIT(57)
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#define RX_RUN_LANE_VEC_0_15 0x0009b80000000000UL
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#define RX_RECAL_ABORT_VEC_0_15 0x0009c80000000000UL
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#define RX_IORESET_VEC_0_15 0x0009d80000000000UL
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#define RX_EO_RECAL_PG 0x000a800000000000UL
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#define RX_INIT_DONE_VEC_0_15 0x000ac00000000000UL
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#define TX_IMPCAL_SWO1_PB 0x000f240000000000UL
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#define TX_ZCAL_SWO_EN PPC_BIT(48)
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#define TX_IMPCAL_SWO2_PB 0x000f2c0000000000UL
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#endif /* __NPU_REGS_H */
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