527 lines
18 KiB
C
527 lines
18 KiB
C
/* Copyright 2016 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __XIVE_H__
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#define __XIVE_H__
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/* IC register offsets */
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#define CQ_SWI_CMD_HIST 0x020
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#define CQ_SWI_CMD_POLL 0x028
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#define CQ_SWI_CMD_BCAST 0x030
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#define CQ_SWI_CMD_ASSIGN 0x038
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#define CQ_SWI_CMD_BLK_UPD 0x040
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#define CQ_SWI_RSP 0x048
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#define X_CQ_CFG_PB_GEN 0x0a
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#define CQ_CFG_PB_GEN 0x050
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#define CQ_INT_ADDR_OPT PPC_BITMASK(14,15)
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#define X_CQ_IC_BAR 0x10
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#define X_CQ_MSGSND 0x0b
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#define CQ_MSGSND 0x058
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#define CQ_CNPM_SEL 0x078
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#define CQ_IC_BAR 0x080
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#define CQ_IC_BAR_VALID PPC_BIT(0)
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#define CQ_IC_BAR_64K PPC_BIT(1)
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#define X_CQ_TM1_BAR 0x12
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#define CQ_TM1_BAR 0x90
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#define X_CQ_TM2_BAR 0x014
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#define CQ_TM2_BAR 0x0a0
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#define CQ_TM_BAR_VALID PPC_BIT(0)
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#define CQ_TM_BAR_64K PPC_BIT(1)
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#define X_CQ_PC_BAR 0x16
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#define CQ_PC_BAR 0x0b0
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#define CQ_PC_BAR_VALID PPC_BIT(0)
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#define X_CQ_PC_BARM 0x17
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#define CQ_PC_BARM 0x0b8
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#define CQ_PC_BARM_MASK PPC_BITMASK(26,38)
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#define X_CQ_VC_BAR 0x18
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#define CQ_VC_BAR 0x0c0
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#define CQ_VC_BAR_VALID PPC_BIT(0)
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#define X_CQ_VC_BARM 0x19
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#define CQ_VC_BARM 0x0c8
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#define CQ_VC_BARM_MASK PPC_BITMASK(21,37)
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#define X_CQ_TAR 0x1e
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#define CQ_TAR 0x0f0
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#define CQ_TAR_TBL_AUTOINC PPC_BIT(0)
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#define CQ_TAR_TSEL_BLK PPC_BIT(12)
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#define CQ_TAR_TSEL_MIG PPC_BIT(13)
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#define CQ_TAR_TSEL_VDT PPC_BIT(14)
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#define CQ_TAR_TSEL_EDT PPC_BIT(15)
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#define X_CQ_TDR 0x1f
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#define CQ_TDR 0x0f8
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#define X_CQ_PBI_CTL 0x20
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#define CQ_PBI_CTL 0x100
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#define CQ_PBI_PC_64K PPC_BIT(5)
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#define CQ_PBI_VC_64K PPC_BIT(6)
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#define CQ_PBI_LNX_TRIG PPC_BIT(7)
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#define CQ_PBI_FORCE_TM_LOCAL PPC_BIT(22)
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#define CQ_PBO_CTL 0x108
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#define CQ_AIB_CTL 0x110
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#define X_CQ_RST_CTL 0x23
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#define CQ_RST_CTL 0x118
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#define X_CQ_FIRMASK 0x33
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#define CQ_FIRMASK 0x198
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#define CQ_FIR_PB_RCMDX_CI_ERR1 PPC_BIT(19)
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#define CQ_FIR_VC_INFO_ERROR_0_1 PPC_BITMASK(62,63)
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#define X_CQ_FIRMASK_AND 0x34
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#define CQ_FIRMASK_AND 0x1a0
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#define X_CQ_FIRMASK_OR 0x35
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#define CQ_FIRMASK_OR 0x1a8
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/* PC LBS1 register offsets */
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#define X_PC_TCTXT_CFG 0x100
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#define PC_TCTXT_CFG 0x400
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#define PC_TCTXT_CFG_BLKGRP_EN PPC_BIT(0)
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#define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1)
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#define PC_TCTXT_CFG_LGS_EN PPC_BIT(2)
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#define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3)
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#define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8)
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#define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9)
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#define PC_TCTXT_CHIPID PPC_BITMASK(12,15)
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#define PC_TCTXT_INIT_AGE PPC_BITMASK(30,31)
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#define X_PC_TCTXT_TRACK 0x101
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#define PC_TCTXT_TRACK 0x408
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#define PC_TCTXT_TRACK_EN PPC_BIT(0)
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#define X_PC_TCTXT_INDIR0 0x104
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#define PC_TCTXT_INDIR0 0x420
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#define PC_TCTXT_INDIR_VALID PPC_BIT(0)
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#define PC_TCTXT_INDIR_THRDID PPC_BITMASK(9,15)
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#define X_PC_TCTXT_INDIR1 0x105
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#define PC_TCTXT_INDIR1 0x428
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#define X_PC_TCTXT_INDIR2 0x106
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#define PC_TCTXT_INDIR2 0x430
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#define X_PC_TCTXT_INDIR3 0x107
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#define PC_TCTXT_INDIR3 0x438
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#define X_PC_THREAD_EN_REG0 0x108
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#define PC_THREAD_EN_REG0 0x440
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#define X_PC_THREAD_EN_REG0_SET 0x109
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#define PC_THREAD_EN_REG0_SET 0x448
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#define X_PC_THREAD_EN_REG0_CLR 0x10a
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#define PC_THREAD_EN_REG0_CLR 0x450
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#define X_PC_THREAD_EN_REG1 0x10c
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#define PC_THREAD_EN_REG1 0x460
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#define X_PC_THREAD_EN_REG1_SET 0x10d
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#define PC_THREAD_EN_REG1_SET 0x468
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#define X_PC_THREAD_EN_REG1_CLR 0x10e
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#define PC_THREAD_EN_REG1_CLR 0x470
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#define X_PC_GLOBAL_CONFIG 0x110
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#define PC_GLOBAL_CONFIG 0x480
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#define PC_GCONF_INDIRECT PPC_BIT(32)
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#define PC_GCONF_CHIPID_OVR PPC_BIT(40)
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#define PC_GCONF_CHIPID PPC_BITMASK(44,47)
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#define X_PC_VSD_TABLE_ADDR 0x111
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#define PC_VSD_TABLE_ADDR 0x488
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#define X_PC_VSD_TABLE_DATA 0x112
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#define PC_VSD_TABLE_DATA 0x490
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#define X_PC_AT_KILL 0x116
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#define PC_AT_KILL 0x4b0
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#define PC_AT_KILL_VALID PPC_BIT(0)
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#define PC_AT_KILL_BLOCK_ID PPC_BITMASK(27,31)
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#define PC_AT_KILL_OFFSET PPC_BITMASK(48,60)
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#define X_PC_AT_KILL_MASK 0x117
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#define PC_AT_KILL_MASK 0x4b8
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/* PC LBS2 register offsets */
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#define X_PC_VPC_CACHE_ENABLE 0x161
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#define PC_VPC_CACHE_ENABLE 0x708
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#define PC_VPC_CACHE_EN_MASK PPC_BITMASK(0,31)
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#define X_PC_VPC_SCRUB_TRIG 0x162
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#define PC_VPC_SCRUB_TRIG 0x710
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#define X_PC_VPC_SCRUB_MASK 0x163
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#define PC_VPC_SCRUB_MASK 0x718
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#define PC_SCRUB_VALID PPC_BIT(0)
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#define PC_SCRUB_WANT_DISABLE PPC_BIT(1)
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#define PC_SCRUB_WANT_INVAL PPC_BIT(2)
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#define PC_SCRUB_BLOCK_ID PPC_BITMASK(27,31)
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#define PC_SCRUB_OFFSET PPC_BITMASK(45,63)
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#define X_PC_VPC_CWATCH_SPEC 0x167
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#define PC_VPC_CWATCH_SPEC 0x738
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#define PC_VPC_CWATCH_CONFLICT PPC_BIT(0)
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#define PC_VPC_CWATCH_FULL PPC_BIT(8)
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#define PC_VPC_CWATCH_BLOCKID PPC_BITMASK(27,31)
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#define PC_VPC_CWATCH_OFFSET PPC_BITMASK(45,63)
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#define X_PC_VPC_CWATCH_DAT0 0x168
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#define PC_VPC_CWATCH_DAT0 0x740
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#define X_PC_VPC_CWATCH_DAT1 0x169
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#define PC_VPC_CWATCH_DAT1 0x748
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#define X_PC_VPC_CWATCH_DAT2 0x16a
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#define PC_VPC_CWATCH_DAT2 0x750
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#define X_PC_VPC_CWATCH_DAT3 0x16b
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#define PC_VPC_CWATCH_DAT3 0x758
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#define X_PC_VPC_CWATCH_DAT4 0x16c
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#define PC_VPC_CWATCH_DAT4 0x760
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#define X_PC_VPC_CWATCH_DAT5 0x16d
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#define PC_VPC_CWATCH_DAT5 0x768
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#define X_PC_VPC_CWATCH_DAT6 0x16e
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#define PC_VPC_CWATCH_DAT6 0x770
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#define X_PC_VPC_CWATCH_DAT7 0x16f
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#define PC_VPC_CWATCH_DAT7 0x778
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/* VC0 register offsets */
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#define X_VC_GLOBAL_CONFIG 0x200
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#define VC_GLOBAL_CONFIG 0x800
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#define VC_GCONF_INDIRECT PPC_BIT(32)
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#define X_VC_VSD_TABLE_ADDR 0x201
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#define VC_VSD_TABLE_ADDR 0x808
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#define X_VC_VSD_TABLE_DATA 0x202
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#define VC_VSD_TABLE_DATA 0x810
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#define VC_IVE_ISB_BLOCK_MODE 0x818
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#define VC_EQD_BLOCK_MODE 0x820
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#define VC_VPS_BLOCK_MODE 0x828
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#define X_VC_IRQ_CONFIG_IPI 0x208
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#define VC_IRQ_CONFIG_IPI 0x840
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#define VC_IRQ_CONFIG_MEMB_EN PPC_BIT(45)
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#define VC_IRQ_CONFIG_MEMB_SZ PPC_BITMASK(46,51)
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#define VC_IRQ_CONFIG_HW 0x848
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#define VC_IRQ_CONFIG_CASCADE1 0x850
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#define VC_IRQ_CONFIG_CASCADE2 0x858
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#define VC_IRQ_CONFIG_REDIST 0x860
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#define VC_IRQ_CONFIG_IPI_CASC 0x868
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#define X_VC_AIB_TX_ORDER_TAG2 0x22d
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#define VC_AIB_TX_ORDER_TAG2_REL_TF PPC_BIT(20)
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#define VC_AIB_TX_ORDER_TAG2 0x890
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#define X_VC_AT_MACRO_KILL 0x23e
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#define VC_AT_MACRO_KILL 0x8b0
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#define X_VC_AT_MACRO_KILL_MASK 0x23f
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#define VC_AT_MACRO_KILL_MASK 0x8b8
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#define VC_KILL_VALID PPC_BIT(0)
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#define VC_KILL_TYPE PPC_BITMASK(14,15)
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#define VC_KILL_IRQ 0
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#define VC_KILL_IVC 1
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#define VC_KILL_SBC 2
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#define VC_KILL_EQD 3
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#define VC_KILL_BLOCK_ID PPC_BITMASK(27,31)
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#define VC_KILL_OFFSET PPC_BITMASK(48,60)
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#define X_VC_EQC_CACHE_ENABLE 0x211
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#define VC_EQC_CACHE_ENABLE 0x908
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#define VC_EQC_CACHE_EN_MASK PPC_BITMASK(0,15)
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#define X_VC_EQC_SCRUB_TRIG 0x212
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#define VC_EQC_SCRUB_TRIG 0x910
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#define X_VC_EQC_SCRUB_MASK 0x213
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#define VC_EQC_SCRUB_MASK 0x918
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#define X_VC_EQC_CWATCH_SPEC 0x215
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#define VC_EQC_CONFIG 0x920
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#define X_VC_EQC_CONFIG 0x214
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#define VC_EQC_CONF_SYNC_IPI PPC_BIT(32)
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#define VC_EQC_CONF_SYNC_HW PPC_BIT(33)
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#define VC_EQC_CONF_SYNC_ESC1 PPC_BIT(34)
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#define VC_EQC_CONF_SYNC_ESC2 PPC_BIT(35)
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#define VC_EQC_CONF_SYNC_REDI PPC_BIT(36)
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#define VC_EQC_CONF_EQP_INTERLEAVE PPC_BIT(38)
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#define VC_EQC_CONF_ENABLE_END_s_BIT PPC_BIT(39)
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#define VC_EQC_CONF_ENABLE_END_u_BIT PPC_BIT(40)
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#define VC_EQC_CONF_ENABLE_END_c_BIT PPC_BIT(41)
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#define VC_EQC_CONF_ENABLE_MORE_QSZ PPC_BIT(42)
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#define VC_EQC_CONF_SKIP_ESCALATE PPC_BIT(43)
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#define VC_EQC_CWATCH_SPEC 0x928
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#define VC_EQC_CWATCH_CONFLICT PPC_BIT(0)
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#define VC_EQC_CWATCH_FULL PPC_BIT(8)
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#define VC_EQC_CWATCH_BLOCKID PPC_BITMASK(28,31)
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#define VC_EQC_CWATCH_OFFSET PPC_BITMASK(40,63)
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#define X_VC_EQC_CWATCH_DAT0 0x216
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#define VC_EQC_CWATCH_DAT0 0x930
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#define X_VC_EQC_CWATCH_DAT1 0x217
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#define VC_EQC_CWATCH_DAT1 0x938
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#define X_VC_EQC_CWATCH_DAT2 0x218
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#define VC_EQC_CWATCH_DAT2 0x940
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#define X_VC_EQC_CWATCH_DAT3 0x219
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#define VC_EQC_CWATCH_DAT3 0x948
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#define X_VC_IVC_SCRUB_TRIG 0x222
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#define VC_IVC_SCRUB_TRIG 0x990
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#define X_VC_IVC_SCRUB_MASK 0x223
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#define VC_IVC_SCRUB_MASK 0x998
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#define X_VC_SBC_SCRUB_TRIG 0x232
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#define VC_SBC_SCRUB_TRIG 0xa10
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#define X_VC_SBC_SCRUB_MASK 0x233
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#define VC_SBC_SCRUB_MASK 0xa18
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#define VC_SCRUB_VALID PPC_BIT(0)
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#define VC_SCRUB_WANT_DISABLE PPC_BIT(1)
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#define VC_SCRUB_WANT_INVAL PPC_BIT(2) /* EQC and SBC only */
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#define VC_SCRUB_BLOCK_ID PPC_BITMASK(28,31)
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#define VC_SCRUB_OFFSET PPC_BITMASK(40,63)
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#define X_VC_IVC_CACHE_ENABLE 0x221
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#define VC_IVC_CACHE_ENABLE 0x988
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#define VC_IVC_CACHE_EN_MASK PPC_BITMASK(0,15)
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#define X_VC_SBC_CACHE_ENABLE 0x231
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#define VC_SBC_CACHE_ENABLE 0xa08
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#define VC_SBC_CACHE_EN_MASK PPC_BITMASK(0,15)
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#define VC_IVC_CACHE_SCRUB_TRIG 0x990
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#define VC_IVC_CACHE_SCRUB_MASK 0x998
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#define VC_SBC_CACHE_ENABLE 0xa08
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#define VC_SBC_CACHE_SCRUB_TRIG 0xa10
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#define VC_SBC_CACHE_SCRUB_MASK 0xa18
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#define VC_SBC_CONFIG 0xa20
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#define X_VC_SBC_CONFIG 0x234
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#define VC_SBC_CONF_CPLX_CIST PPC_BIT(44)
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#define VC_SBC_CONF_CIST_BOTH PPC_BIT(45)
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#define VC_SBC_CONF_NO_UPD_PRF PPC_BIT(59)
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/* VC1 register offsets */
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/* VSD Table address register definitions (shared) */
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#define VST_ADDR_AUTOINC PPC_BIT(0)
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#define VST_TABLE_SELECT PPC_BITMASK(13,15)
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#define VST_TSEL_IVT 0
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#define VST_TSEL_SBE 1
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#define VST_TSEL_EQDT 2
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#define VST_TSEL_VPDT 3
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#define VST_TSEL_IRQ 4 /* VC only */
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#define VST_TABLE_OFFSET PPC_BITMASK(27,31)
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/* Number of queue overflow pages */
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#define VC_QUEUE_OVF_COUNT 6
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/* Bits in a VSD entry.
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*
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* Note: the address is naturally aligned, we don't use a PPC_BITMASK,
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* but just a mask to apply to the address before OR'ing it in.
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*
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* Note: VSD_FIRMWARE is a SW bit ! It hijacks an unused bit in the
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* VSD and is only meant to be used in indirect mode !
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*/
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#define VSD_MODE PPC_BITMASK(0,1)
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#define VSD_MODE_SHARED 1
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#define VSD_MODE_EXCLUSIVE 2
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#define VSD_MODE_FORWARD 3
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#define VSD_ADDRESS_MASK 0x0ffffffffffff000ull
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#define VSD_MIGRATION_REG PPC_BITMASK(52,55)
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#define VSD_INDIRECT PPC_BIT(56)
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#define VSD_TSIZE PPC_BITMASK(59,63)
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#define VSD_FIRMWARE PPC_BIT(2) /* Read warning above */
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/*
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* TM registers are special, see below
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*/
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/* TM register offsets */
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#define TM_QW0_USER 0x000 /* All rings */
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#define TM_QW1_OS 0x010 /* Ring 0..2 */
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#define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */
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#define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */
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/* Byte offsets inside a QW QW0 QW1 QW2 QW3 */
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#define TM_NSR 0x0 /* + + - + */
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#define TM_CPPR 0x1 /* - + - + */
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#define TM_IPB 0x2 /* - + + + */
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#define TM_LSMFB 0x3 /* - + + + */
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#define TM_ACK_CNT 0x4 /* - + - - */
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#define TM_INC 0x5 /* - + - + */
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#define TM_AGE 0x6 /* - + - + */
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#define TM_PIPR 0x7 /* - + - + */
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/* QW word 2 contains the valid bit at the top and other fields
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* depending on the QW
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*/
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#define TM_WORD2 0x8
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#define TM_QW0W2_VU PPC_BIT32(0)
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#define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1,31) // XX 2,31 ?
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#define TM_QW1W2_VO PPC_BIT32(0)
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#define TM_QW1W2_OS_CAM PPC_BITMASK32(8,31)
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#define TM_QW2W2_VP PPC_BIT32(0)
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#define TM_QW2W2_POOL_CAM PPC_BITMASK32(8,31)
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#define TM_QW3W2_VT PPC_BIT32(0)
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#define TM_QW3W2_LP PPC_BIT32(6)
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#define TM_QW3W2_LE PPC_BIT32(7)
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#define TM_QW3W2_T PPC_BIT32(31)
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/* In addition to normal loads to "peek" and writes (only when invalid)
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* using 4 and 8 bytes accesses, the above registers support these
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* "special" byte operations:
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*
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* - Byte load from QW0[NSR] - User level NSR (EBB)
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* - Byte store to QW0[NSR] - User level NSR (EBB)
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* - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access
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* - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0
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* otherwise VT||0000000
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* - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present)
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*
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* Then we have all these "special" CI ops at these offset that trigger
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* all sorts of side effects:
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*
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* We can OR'in these a cache line index from 0...3 (ie, 0, 0x80, 0x100, 0x180)
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* to select a specific snooper. 0 is pretty busy so 0x80 or 0x100 is recommended
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* XXX TODO. add that and find way to tell KVM about it.
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*/
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#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/
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#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */
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#define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */
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#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user context */
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#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */
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#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS context to reg */
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#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool context to reg*/
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#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */
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#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd line */
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#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */
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#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even line */
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#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */
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/* XXX more... */
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/* NSR fields for the various QW ack types */
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#define TM_QW0_NSR_EB PPC_BIT8(0)
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#define TM_QW1_NSR_EO PPC_BIT8(0)
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#define TM_QW3_NSR_HE PPC_BITMASK8(0,1)
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#define TM_QW3_NSR_HE_NONE 0
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#define TM_QW3_NSR_HE_POOL 1
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#define TM_QW3_NSR_HE_PHYS 2
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#define TM_QW3_NSR_HE_LSI 3
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#define TM_QW3_NSR_I PPC_BIT8(2)
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#define TM_QW3_NSR_GRP_LVL PPC_BIT8(3,7)
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/*
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* Definition of the XIVE in-memory tables
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*/
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/* IVE/EAS
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*
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* One per interrupt source. Targets that interrupt to a given EQ
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* and provides the corresponding logical interrupt number (EQ data)
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*
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* We also map this structure to the escalation descriptor inside
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* an EQ, though in that case the valid and masked bits are not used.
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*/
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struct xive_ive {
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/* Use a single 64-bit definition to make it easier to
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* perform atomic updates
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|
*/
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uint64_t w;
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#define IVE_VALID PPC_BIT(0)
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#define IVE_EQ_BLOCK PPC_BITMASK(4,7) /* Destination EQ block# */
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#define IVE_EQ_INDEX PPC_BITMASK(8,31) /* Destination EQ index */
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#define IVE_MASKED PPC_BIT(32) /* Masked */
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#define IVE_EQ_DATA PPC_BITMASK(33,63) /* Data written to the EQ */
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};
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|
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/* EQ */
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struct xive_eq {
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uint32_t w0;
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#define EQ_W0_VALID PPC_BIT32(0) /* "v" bit */
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#define EQ_W0_ENQUEUE PPC_BIT32(1) /* "q" bit */
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#define EQ_W0_UCOND_NOTIFY PPC_BIT32(2) /* "n" bit */
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#define EQ_W0_BACKLOG PPC_BIT32(3) /* "b" bit */
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#define EQ_W0_PRECL_ESC_CTL PPC_BIT32(4) /* "p" bit */
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#define EQ_W0_ESCALATE_CTL PPC_BIT32(5) /* "e" bit */
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#define EQ_W0_UNCOND_ESCALATE PPC_BIT32(6) /* "u" bit - DD2.0 */
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|
#define EQ_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit - DD2.0 */
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|
#define EQ_W0_QSIZE PPC_BITMASK32(12,15)
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|
#define EQ_W0_SW0 PPC_BIT32(16)
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|
#define EQ_W0_FIRMWARE EQ_W0_SW0 /* Owned by FW */
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|
#define EQ_QSIZE_4K 0
|
|
#define EQ_QSIZE_64K 4
|
|
#define EQ_W0_HWDEP PPC_BITMASK32(24,31)
|
|
uint32_t w1;
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|
#define EQ_W1_ESn PPC_BITMASK32(0,1)
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|
#define EQ_W1_ESn_P PPC_BIT32(0)
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|
#define EQ_W1_ESn_Q PPC_BIT32(1)
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|
#define EQ_W1_ESe PPC_BITMASK32(2,3)
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|
#define EQ_W1_ESe_P PPC_BIT32(2)
|
|
#define EQ_W1_ESe_Q PPC_BIT32(3)
|
|
#define EQ_W1_GENERATION PPC_BIT32(9)
|
|
#define EQ_W1_PAGE_OFF PPC_BITMASK32(10,31)
|
|
uint32_t w2;
|
|
#define EQ_W2_MIGRATION_REG PPC_BITMASK32(0,3)
|
|
#define EQ_W2_OP_DESC_HI PPC_BITMASK32(4,31)
|
|
uint32_t w3;
|
|
#define EQ_W3_OP_DESC_LO PPC_BITMASK32(0,31)
|
|
uint32_t w4;
|
|
#define EQ_W4_ESC_EQ_BLOCK PPC_BITMASK32(4,7)
|
|
#define EQ_W4_ESC_EQ_INDEX PPC_BITMASK32(8,31)
|
|
uint32_t w5;
|
|
#define EQ_W5_ESC_EQ_DATA PPC_BITMASK32(1,31)
|
|
uint32_t w6;
|
|
#define EQ_W6_FORMAT_BIT PPC_BIT32(8)
|
|
#define EQ_W6_NVT_BLOCK PPC_BITMASK32(9,12)
|
|
#define EQ_W6_NVT_INDEX PPC_BITMASK32(13,31)
|
|
uint32_t w7;
|
|
#define EQ_W7_F0_IGNORE PPC_BIT32(0)
|
|
#define EQ_W7_F0_BLK_GROUPING PPC_BIT32(1)
|
|
#define EQ_W7_F0_PRIORITY PPC_BITMASK32(8,15)
|
|
#define EQ_W7_F1_WAKEZ PPC_BIT32(0)
|
|
#define EQ_W7_F1_LOG_SERVER_ID PPC_BITMASK32(1,31)
|
|
};
|
|
|
|
/* VP */
|
|
struct xive_vp {
|
|
uint32_t w0;
|
|
#define VP_W0_VALID PPC_BIT32(0)
|
|
uint32_t w1;
|
|
uint32_t w2;
|
|
uint32_t w3;
|
|
uint32_t w4;
|
|
uint32_t w5;
|
|
uint32_t w6;
|
|
uint32_t w7;
|
|
uint32_t w8;
|
|
#define VP_W8_GRP_VALID PPC_BIT32(0)
|
|
uint32_t w9;
|
|
uint32_t wa;
|
|
uint32_t wb;
|
|
uint32_t wc;
|
|
uint32_t wd;
|
|
uint32_t we;
|
|
uint32_t wf;
|
|
};
|
|
|
|
/* Internal APIs to other modules */
|
|
|
|
/* IRQ allocators return this on failure */
|
|
#define XIVE_IRQ_ERROR 0xffffffff
|
|
|
|
void init_xive(void);
|
|
int64_t xive_reset(void);
|
|
|
|
/* Allocate a chunk of HW sources */
|
|
uint32_t xive_alloc_hw_irqs(uint32_t chip_id, uint32_t count, uint32_t align);
|
|
/* Allocate a chunk of IPI sources */
|
|
uint32_t xive_alloc_ipi_irqs(uint32_t chip_id, uint32_t count, uint32_t align);
|
|
|
|
/* Get notification port address for a HW source entity */
|
|
#define XIVE_HW_SRC_PHBn(__n) (__n)
|
|
#define XIVE_HW_SRC_PSI 8
|
|
|
|
uint64_t xive_get_notify_port(uint32_t chip_id, uint32_t ent);
|
|
uint32_t xive_get_notify_base(uint32_t girq);
|
|
|
|
/* XIVE feature flag to de/activate store EOI */
|
|
#define XIVE_STORE_EOI_ENABLED 0
|
|
|
|
/* Internal IRQ flags */
|
|
#define XIVE_SRC_TRIGGER_PAGE 0x01 /* Trigger page exist (either separate
|
|
* or not, so different from the OPAL
|
|
* flag which is only set when the
|
|
* trigger page is separate).
|
|
*/
|
|
#define XIVE_SRC_EOI_PAGE1 0x02 /* EOI on the second page */
|
|
#define XIVE_SRC_STORE_EOI 0x04 /* EOI using stores supported */
|
|
#define XIVE_SRC_LSI 0x08 /* Interrupt is an LSI */
|
|
#define XIVE_SRC_SHIFT_BUG 0x10 /* ESB update offset << 4 */
|
|
|
|
struct irq_source_ops;
|
|
void xive_register_hw_source(uint32_t base, uint32_t count, uint32_t shift,
|
|
void *mmio, uint32_t flags, void *data,
|
|
const struct irq_source_ops *ops);
|
|
void xive_register_ipi_source(uint32_t base, uint32_t count, void *data,
|
|
const struct irq_source_ops *ops);
|
|
|
|
void xive_cpu_callin(struct cpu_thread *cpu);
|
|
|
|
/* Get the trigger page address for an interrupt allocated with
|
|
* xive_alloc_ipi_irqs()
|
|
*/
|
|
void *xive_get_trigger_port(uint32_t girq);
|
|
|
|
/* To be used by special EOI override in PSI */
|
|
struct irq_source;
|
|
void __xive_source_eoi(struct irq_source *is, uint32_t isn);
|
|
|
|
#endif /* __XIVE_H__ */
|