85 lines
2.8 KiB
C
85 lines
2.8 KiB
C
#ifndef __XSCOM_P9_REGS_H__
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#define __XSCOM_P9_REGS_H__
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/* Core FIR (Fault Isolation Register) */
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#define P9_CORE_FIR 0x20010A40
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/* Core WOF (Whose On First) */
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#define P9_CORE_WOF 0x20010A48
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/* pMisc Receive Malfunction Alert Register */
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#define P9_MALFUNC_ALERT 0x00090022
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#define P9_NX_STATUS_REG 0x02011040 /* NX status register */
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#define P9_NX_DMA_ENGINE_FIR 0x02011100 /* DMA & Engine FIR Data Register */
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#define P9_NX_PBI_FIR 0x02011080 /* PowerBus Interface FIR Register */
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/*
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* Bit 54 from NX status register is set to 1 when HMI interrupt is triggered
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* due to NX checksop.
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*/
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#define NX_HMI_ACTIVE PPC_BIT(54)
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/* Direct controls */
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#define P9_EC_DIRECT_CONTROLS 0x10a9c
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#define P9_THREAD_STOP(t) PPC_BIT(7 + 8*(t))
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#define P9_THREAD_CONT(t) PPC_BIT(6 + 8*(t))
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#define P9_THREAD_SRESET(t) PPC_BIT(4 + 8*(t))
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#define P9_THREAD_CLEAR_MAINT(t) PPC_BIT(3 + 8*(t))
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#define P9_THREAD_PWR(t) PPC_BIT(32 + 8*(t))
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#define P9_RAS_STATUS 0x10a02
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#define P9_THREAD_QUIESCED(t) PPC_BITMASK(0 + 8*(t), 3 + 8*(t))
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#define P9_CORE_THREAD_STATE 0x10ab3
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#define P9_THREAD_INFO 0x10a9b
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/* EC_PPM_SPECIAL_WKUP_HYP */
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#define P9_SPWKUP_SET PPC_BIT(0)
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#define P9_EC_PPM_SSHHYP 0x0114
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#define P9_CORE_GATED PPC_BIT(0)
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#define P9_SPECIAL_WKUP_DONE PPC_BIT(1)
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/* EX (core pair) registers, use XSCOM_ADDR_P9_EX to access */
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#define P9X_EX_NCU_STATUS_REG 0x1100f
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#define P9X_EX_NCU_SPEC_BAR 0x11010
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#define P9X_EX_NCU_SPEC_BAR_ENABLE PPC_BIT(0)
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#define P9X_EX_NCU_SPEC_BAR_256K PPC_BIT(1)
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#define P9X_EX_NCU_SPEC_BAR_ADDRMSK 0x0fffffffffffc000ull /* naturally aligned */
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#define P9X_NX_MMIO_BAR 0x201108d
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#define P9X_NX_MMIO_BAR_EN PPC_BIT(52)
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#define P9X_NX_MMIO_OFFSET 0x00060302031d0000ull
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#define P9X_NX_RNG_CFG 0x20110E0
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#define P9X_NX_RNG_CFG_EN PPC_BIT(63)
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#define P9X_EX_NCU_DARN_BAR 0x11011
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#define P9X_EX_NCU_DARN_BAR_EN PPC_BIT(0)
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#define P9_GPIO_DATA_OUT 0x00000000000B0051ull
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#define P9_GPIO_DATA_OUT_ENABLE 0x00000000000B0054ull
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#define P9_GPIO_INTERRUPT_STATUS 0x00000000000B0057ull
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#define P9_GPIO_INTERRUPT_ENABLE 0x00000000000B005Dull
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#define P9_GPIO_INTERRUPT_CONDITION 0x00000000000B005Eull
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/* xscom address for SCOM Control and data Register */
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/* bits 54:60 of SCOM SPRC register is used for core specific SPR selection. */
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#define P9_SCOM_SPRC 0x20010A80
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#define P9_SCOMC_SPR_SELECT PPC_BITMASK(54, 60)
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#define P9_SCOMC_TFMR_T0 0x8 /* 0b0001000 TFMR */
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#define P9_SCOM_SPRD 0x20010A81
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#define PB_CENT_HP_MODE_CURR 0x5011c0c
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#define PB_CFG_CHG_RATE_GP_MASTER PPC_BIT(2)
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#define PB_CFG_PUMP_MODE PPC_BIT(54)
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/* Power 9 EC slave per-core power mgt slave registers */
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#define EC_PPM_SPECIAL_WKUP_OTR 0x010A
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#define EC_PPM_SPECIAL_WKUP_FSP 0x010B
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#define EC_PPM_SPECIAL_WKUP_OCC 0x010C
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#define EC_PPM_SPECIAL_WKUP_HYP 0x010D
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#endif /* __XSCOM_P9_REGS_H__ */
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