644 lines
15 KiB
C
644 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <ahci.h>
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#include <linux/mbus.h>
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#include <asm/io.h>
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#include <asm/pl310.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <sdhci.h>
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#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
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#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
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static struct mbus_win windows[] = {
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/* SPI */
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{ MBUS_SPI_BASE, MBUS_SPI_SIZE,
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
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/* NOR */
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{ MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
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};
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void lowlevel_init(void)
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{
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/*
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* Dummy implementation, we only need LOWLEVEL_INIT
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* on Armada to configure CP15 in start.S / cpu_init_cp15()
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*/
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}
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void reset_cpu(unsigned long ignored)
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{
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struct mvebu_system_registers *reg =
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(struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
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writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
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writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
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while (1)
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;
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}
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int mvebu_soc_family(void)
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{
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u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
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switch (devid) {
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case SOC_MV78230_ID:
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case SOC_MV78260_ID:
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case SOC_MV78460_ID:
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return MVEBU_SOC_AXP;
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case SOC_88F6720_ID:
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return MVEBU_SOC_A375;
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case SOC_88F6810_ID:
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case SOC_88F6820_ID:
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case SOC_88F6828_ID:
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return MVEBU_SOC_A38X;
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case SOC_98DX3236_ID:
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case SOC_98DX3336_ID:
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case SOC_98DX4251_ID:
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return MVEBU_SOC_MSYS;
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}
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return MVEBU_SOC_UNKNOWN;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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#if defined(CONFIG_ARMADA_375)
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/* SAR frequency values for Armada 375 */
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static const struct sar_freq_modes sar_freq_tab[] = {
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{ 0, 0x0, 266, 133, 266 },
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{ 1, 0x0, 333, 167, 167 },
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{ 2, 0x0, 333, 167, 222 },
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{ 3, 0x0, 333, 167, 333 },
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{ 4, 0x0, 400, 200, 200 },
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{ 5, 0x0, 400, 200, 267 },
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{ 6, 0x0, 400, 200, 400 },
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{ 7, 0x0, 500, 250, 250 },
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{ 8, 0x0, 500, 250, 334 },
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{ 9, 0x0, 500, 250, 500 },
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{ 10, 0x0, 533, 267, 267 },
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{ 11, 0x0, 533, 267, 356 },
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{ 12, 0x0, 533, 267, 533 },
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{ 13, 0x0, 600, 300, 300 },
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{ 14, 0x0, 600, 300, 400 },
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{ 15, 0x0, 600, 300, 600 },
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{ 16, 0x0, 666, 333, 333 },
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{ 17, 0x0, 666, 333, 444 },
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{ 18, 0x0, 666, 333, 666 },
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{ 19, 0x0, 800, 400, 267 },
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{ 20, 0x0, 800, 400, 400 },
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{ 21, 0x0, 800, 400, 534 },
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{ 22, 0x0, 900, 450, 300 },
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{ 23, 0x0, 900, 450, 450 },
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{ 24, 0x0, 900, 450, 600 },
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{ 25, 0x0, 1000, 500, 500 },
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{ 26, 0x0, 1000, 500, 667 },
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{ 27, 0x0, 1000, 333, 500 },
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{ 28, 0x0, 400, 400, 400 },
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{ 29, 0x0, 1100, 550, 550 },
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{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
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};
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#elif defined(CONFIG_ARMADA_38X)
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/* SAR frequency values for Armada 38x */
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static const struct sar_freq_modes sar_freq_tab[] = {
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{ 0x0, 0x0, 666, 333, 333 },
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{ 0x2, 0x0, 800, 400, 400 },
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{ 0x4, 0x0, 1066, 533, 533 },
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{ 0x6, 0x0, 1200, 600, 600 },
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{ 0x8, 0x0, 1332, 666, 666 },
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{ 0xc, 0x0, 1600, 800, 800 },
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{ 0x10, 0x0, 1866, 933, 933 },
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{ 0x13, 0x0, 2000, 1000, 933 },
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{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
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};
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#else
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/* SAR frequency values for Armada XP */
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static const struct sar_freq_modes sar_freq_tab[] = {
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{ 0xa, 0x5, 800, 400, 400 },
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{ 0x1, 0x5, 1066, 533, 533 },
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{ 0x2, 0x5, 1200, 600, 600 },
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{ 0x2, 0x9, 1200, 600, 400 },
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{ 0x3, 0x5, 1333, 667, 667 },
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{ 0x4, 0x5, 1500, 750, 750 },
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{ 0x4, 0x9, 1500, 750, 500 },
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{ 0xb, 0x9, 1600, 800, 533 },
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{ 0xb, 0xa, 1600, 800, 640 },
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{ 0xb, 0x5, 1600, 800, 800 },
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{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
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};
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#endif
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void get_sar_freq(struct sar_freq_modes *sar_freq)
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{
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u32 val;
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u32 freq;
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int i;
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#if defined(CONFIG_ARMADA_375)
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val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
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#else
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val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
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#endif
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freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
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#if defined(SAR2_CPU_FREQ_MASK)
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/*
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* Shift CPU0 clock frequency select bit from SAR2 register
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* into correct position
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*/
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freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
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>> SAR2_CPU_FREQ_OFFS) << 3;
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#endif
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for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
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if (sar_freq_tab[i].val == freq) {
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#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
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*sar_freq = sar_freq_tab[i];
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return;
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#else
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int k;
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u8 ffc;
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ffc = (val & SAR_FFC_FREQ_MASK) >>
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SAR_FFC_FREQ_OFFS;
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for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
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if (sar_freq_tab[k].ffc == ffc) {
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*sar_freq = sar_freq_tab[k];
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return;
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}
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}
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i = k;
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#endif
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}
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}
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/* SAR value not found, return 0 for frequencies */
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*sar_freq = sar_freq_tab[i - 1];
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}
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int print_cpuinfo(void)
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{
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u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
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u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
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struct sar_freq_modes sar_freq;
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puts("SoC: ");
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switch (devid) {
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case SOC_MV78230_ID:
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puts("MV78230-");
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break;
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case SOC_MV78260_ID:
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puts("MV78260-");
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break;
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case SOC_MV78460_ID:
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puts("MV78460-");
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break;
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case SOC_88F6720_ID:
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puts("MV88F6720-");
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break;
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case SOC_88F6810_ID:
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puts("MV88F6810-");
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break;
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case SOC_88F6820_ID:
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puts("MV88F6820-");
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break;
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case SOC_88F6828_ID:
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puts("MV88F6828-");
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break;
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case SOC_98DX3236_ID:
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puts("98DX3236-");
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break;
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case SOC_98DX3336_ID:
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puts("98DX3336-");
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break;
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case SOC_98DX4251_ID:
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puts("98DX4251-");
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break;
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default:
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puts("Unknown-");
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break;
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}
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if (mvebu_soc_family() == MVEBU_SOC_AXP) {
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switch (revid) {
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case 1:
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puts("A0");
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break;
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case 2:
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puts("B0");
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break;
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default:
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printf("?? (%x)", revid);
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break;
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}
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}
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if (mvebu_soc_family() == MVEBU_SOC_A375) {
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switch (revid) {
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case MV_88F67XX_A0_ID:
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puts("A0");
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break;
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default:
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printf("?? (%x)", revid);
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break;
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}
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}
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if (mvebu_soc_family() == MVEBU_SOC_A38X) {
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switch (revid) {
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case MV_88F68XX_Z1_ID:
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puts("Z1");
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break;
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case MV_88F68XX_A0_ID:
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puts("A0");
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break;
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case MV_88F68XX_B0_ID:
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puts("B0");
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break;
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default:
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printf("?? (%x)", revid);
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break;
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}
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}
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get_sar_freq(&sar_freq);
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printf(" at %d MHz\n", sar_freq.p_clk);
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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/*
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* This function initialize Controller DRAM Fastpath windows.
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* It takes the CS size information from the 0x1500 scratch registers
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* and sets the correct windows sizes and base addresses accordingly.
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*
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* These values are set in the scratch registers by the Marvell
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* DDR3 training code, which is executed by the SPL before the
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* main payload (U-Boot) is executed.
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*/
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static void update_sdram_window_sizes(void)
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{
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u64 base = 0;
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u32 size, temp;
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int i;
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for (i = 0; i < SDRAM_MAX_CS; i++) {
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size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
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if (size != 0) {
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size |= ~(SDRAM_ADDR_MASK);
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/* Set Base Address */
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temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
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writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
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/*
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* Check if out of max window size and resize
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* the window
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*/
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temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
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~(SDRAM_ADDR_MASK)) | 1;
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temp |= (size & SDRAM_ADDR_MASK);
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writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
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base += ((u64)size + 1);
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} else {
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/*
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* Disable window if not used, otherwise this
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* leads to overlapping enabled windows with
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* pretty strange results
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*/
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clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
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}
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}
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}
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void mmu_disable(void)
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{
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asm volatile(
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"mrc p15, 0, r0, c1, c0, 0\n"
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"bic r0, #1\n"
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"mcr p15, 0, r0, c1, c0, 0\n");
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}
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#ifdef CONFIG_ARCH_CPU_INIT
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static void set_cbar(u32 addr)
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{
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asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
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}
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#define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
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#define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
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#define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
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(((addr) & 0xF) << 6))
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#define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
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(((reg) & 0xF) << 2))
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static void setup_usb_phys(void)
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{
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int dev;
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/*
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* USB PLL init
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*/
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/* Setup PLL frequency */
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/* USB REF frequency = 25 MHz */
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clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
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/* Power up PLL and PHY channel */
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setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
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/* Assert VCOCAL_START */
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setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
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mdelay(1);
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/*
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* USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
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*/
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for (dev = 0; dev < 3; dev++) {
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setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
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/* Assert REG_RCAL_START in channel REG 1 */
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setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
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udelay(40);
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clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
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}
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}
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/*
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* This function is not called from the SPL U-Boot version
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*/
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int arch_cpu_init(void)
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{
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struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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/*
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* Only with disabled MMU its possible to switch the base
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* register address on Armada 38x. Without this the SDRAM
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* located at >= 0x4000.0000 is also not accessible, as its
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* still locked to cache.
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*/
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mmu_disable();
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/* Linux expects the internal registers to be at 0xf1000000 */
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writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
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set_cbar(SOC_REGS_PHY_BASE + 0xC000);
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/*
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* From this stage on, the SoC detection is working. As we have
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* configured the internal register base to the value used
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* in the macros / defines in the U-Boot header (soc.h).
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*/
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if (mvebu_soc_family() == MVEBU_SOC_A38X) {
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/*
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* To fully release / unlock this area from cache, we need
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* to flush all caches and disable the L2 cache.
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*/
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icache_disable();
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dcache_disable();
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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/*
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* We need to call mvebu_mbus_probe() before calling
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* update_sdram_window_sizes() as it disables all previously
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* configured mbus windows and then configures them as
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* required for U-Boot. Calling update_sdram_window_sizes()
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* without this configuration will not work, as the internal
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* registers can't be accessed reliably because of potenial
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* double mapping.
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* After updating the SDRAM access windows we need to call
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* mvebu_mbus_probe() again, as this now correctly configures
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* the SDRAM areas that are later used by the MVEBU drivers
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* (e.g. USB, NETA).
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*/
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/*
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* First disable all windows
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*/
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mvebu_mbus_probe(NULL, 0);
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if (mvebu_soc_family() == MVEBU_SOC_AXP) {
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/*
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* Now the SDRAM access windows can be reconfigured using
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* the information in the SDRAM scratch pad registers
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*/
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update_sdram_window_sizes();
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}
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/*
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* Finally the mbus windows can be configured with the
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* updated SDRAM sizes
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*/
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mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
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if (mvebu_soc_family() == MVEBU_SOC_AXP) {
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/* Enable GBE0, GBE1, LCD and NFC PUP */
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clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
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GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
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NAND_PUP_EN | SPI_PUP_EN);
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/* Configure USB PLL and PHYs on AXP */
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setup_usb_phys();
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}
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/* Enable NAND and NAND arbiter */
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clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
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/* Disable MBUS error propagation */
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clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
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return 0;
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}
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#endif /* CONFIG_ARCH_CPU_INIT */
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u32 mvebu_get_nand_clock(void)
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{
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u32 reg;
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if (mvebu_soc_family() == MVEBU_SOC_A38X)
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reg = MVEBU_DFX_DIV_CLK_CTRL(1);
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else
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reg = MVEBU_CORE_DIV_CLK_CTRL(1);
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return CONFIG_SYS_MVEBU_PLL_CLOCK /
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((readl(reg) &
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NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
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}
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/*
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* SOC specific misc init
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*/
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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/* Nothing yet, perhaps we need something here later */
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return 0;
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}
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#endif /* CONFIG_ARCH_MISC_INIT */
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#ifdef CONFIG_MMC_SDHCI_MV
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int board_mmc_init(bd_t *bis)
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{
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mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
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|
SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SCSI_AHCI_PLAT
|
|
#define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
|
|
#define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
|
|
|
|
#define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
|
|
#define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
|
|
#define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
|
|
|
|
static void ahci_mvebu_mbus_config(void __iomem *base)
|
|
{
|
|
const struct mbus_dram_target_info *dram;
|
|
int i;
|
|
|
|
dram = mvebu_mbus_dram_info();
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
writel(0, base + AHCI_WINDOW_CTRL(i));
|
|
writel(0, base + AHCI_WINDOW_BASE(i));
|
|
writel(0, base + AHCI_WINDOW_SIZE(i));
|
|
}
|
|
|
|
for (i = 0; i < dram->num_cs; i++) {
|
|
const struct mbus_dram_window *cs = dram->cs + i;
|
|
|
|
writel((cs->mbus_attr << 8) |
|
|
(dram->mbus_dram_target_id << 4) | 1,
|
|
base + AHCI_WINDOW_CTRL(i));
|
|
writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
|
|
writel(((cs->size - 1) & 0xffff0000),
|
|
base + AHCI_WINDOW_SIZE(i));
|
|
}
|
|
}
|
|
|
|
static void ahci_mvebu_regret_option(void __iomem *base)
|
|
{
|
|
/*
|
|
* Enable the regret bit to allow the SATA unit to regret a
|
|
* request that didn't receive an acknowlegde and avoid a
|
|
* deadlock
|
|
*/
|
|
writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
|
|
writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
|
|
}
|
|
|
|
void scsi_init(void)
|
|
{
|
|
printf("MVEBU SATA INIT\n");
|
|
ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
|
|
ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
|
|
ahci_init((void __iomem *)MVEBU_SATA0_BASE);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_USB_XHCI_MVEBU
|
|
#define USB3_MAX_WINDOWS 4
|
|
#define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
|
|
#define USB3_WIN_BASE(w) (0x4 + ((w) * 8))
|
|
|
|
static void xhci_mvebu_mbus_config(void __iomem *base,
|
|
const struct mbus_dram_target_info *dram)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < USB3_MAX_WINDOWS; i++) {
|
|
writel(0, base + USB3_WIN_CTRL(i));
|
|
writel(0, base + USB3_WIN_BASE(i));
|
|
}
|
|
|
|
for (i = 0; i < dram->num_cs; i++) {
|
|
const struct mbus_dram_window *cs = dram->cs + i;
|
|
|
|
/* Write size, attributes and target id to control register */
|
|
writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
|
|
(dram->mbus_dram_target_id << 4) | 1,
|
|
base + USB3_WIN_CTRL(i));
|
|
|
|
/* Write base address to base register */
|
|
writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
|
|
}
|
|
}
|
|
|
|
int board_xhci_enable(fdt_addr_t base)
|
|
{
|
|
const struct mbus_dram_target_info *dram;
|
|
|
|
printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
|
|
|
|
dram = mvebu_mbus_dram_info();
|
|
xhci_mvebu_mbus_config((void __iomem *)base, dram);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
void enable_caches(void)
|
|
{
|
|
/* Avoid problem with e.g. neta ethernet driver */
|
|
invalidate_dcache_all();
|
|
|
|
/*
|
|
* Armada 375 still has some problems with d-cache enabled in the
|
|
* ethernet driver (mvpp2). So lets keep the d-cache disabled
|
|
* until this is solved.
|
|
*/
|
|
if (mvebu_soc_family() != MVEBU_SOC_A375) {
|
|
/* Enable D-cache. I-cache is already enabled in start.S */
|
|
dcache_enable();
|
|
}
|
|
}
|
|
|
|
void v7_outer_cache_enable(void)
|
|
{
|
|
if (mvebu_soc_family() == MVEBU_SOC_AXP) {
|
|
struct pl310_regs *const pl310 =
|
|
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
|
|
u32 u;
|
|
|
|
/* The L2 cache is already disabled at this point */
|
|
|
|
/*
|
|
* For Aurora cache in no outer mode, enable via the CP15
|
|
* coprocessor broadcasting of cache commands to L2.
|
|
*/
|
|
asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
|
|
u |= BIT(8); /* Set the FW bit */
|
|
asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
|
|
|
|
isb();
|
|
|
|
/* Enable the L2 cache */
|
|
setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
|
|
}
|
|
}
|
|
|
|
void v7_outer_cache_disable(void)
|
|
{
|
|
struct pl310_regs *const pl310 =
|
|
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
|
|
|
|
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
|
|
}
|