180 lines
4 KiB
C
180 lines
4 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/armv7.h>
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#include <asm/gic.h>
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#include <asm/io.h>
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#include <asm/psci.h>
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#include <asm/secure.h>
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#define BOOT_API_A7_CORE0_MAGIC_NUMBER 0xCA7FACE0
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#define BOOT_API_A7_CORE1_MAGIC_NUMBER 0xCA7FACE1
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#define MPIDR_AFF0 GENMASK(7, 0)
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#define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404)
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#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5)
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#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
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#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
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#define STM32MP1_PSCI_NR_CPUS 2
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#if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
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#error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
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#endif
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u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = {
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PSCI_AFFINITY_LEVEL_ON,
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PSCI_AFFINITY_LEVEL_OFF};
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void __secure psci_set_state(int cpu, u8 state)
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{
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psci_state[cpu] = state;
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dsb();
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isb();
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}
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static u32 __secure stm32mp_get_gicd_base_address(void)
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{
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u32 periphbase;
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/* get the GIC base address from the CBAR register */
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asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
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return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
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}
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static void __secure stm32mp_smp_kick_all_cpus(void)
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{
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u32 gic_dist_addr;
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gic_dist_addr = stm32mp_get_gicd_base_address();
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/* kick all CPUs (except this one) by writing to GICD_SGIR */
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writel(1U << 24, gic_dist_addr + GICD_SGIR);
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}
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void __secure psci_arch_cpu_entry(void)
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{
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u32 cpu = psci_get_cpu_id();
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psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
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}
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int __secure psci_features(u32 function_id, u32 psci_fid)
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{
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switch (psci_fid) {
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case ARM_PSCI_0_2_FN_PSCI_VERSION:
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case ARM_PSCI_0_2_FN_CPU_OFF:
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case ARM_PSCI_0_2_FN_CPU_ON:
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case ARM_PSCI_0_2_FN_AFFINITY_INFO:
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case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
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case ARM_PSCI_0_2_FN_SYSTEM_OFF:
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case ARM_PSCI_0_2_FN_SYSTEM_RESET:
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return 0x0;
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}
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return ARM_PSCI_RET_NI;
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}
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unsigned int __secure psci_version(u32 function_id)
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{
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return ARM_PSCI_VER_1_0;
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}
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int __secure psci_affinity_info(u32 function_id, u32 target_affinity,
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u32 lowest_affinity_level)
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{
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u32 cpu = target_affinity & MPIDR_AFF0;
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if (lowest_affinity_level > 0)
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return ARM_PSCI_RET_INVAL;
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if (target_affinity & ~MPIDR_AFF0)
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return ARM_PSCI_RET_INVAL;
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if (cpu >= STM32MP1_PSCI_NR_CPUS)
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return ARM_PSCI_RET_INVAL;
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return psci_state[cpu];
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}
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int __secure psci_migrate_info_type(u32 function_id)
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{
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/* Trusted OS is either not present or does not require migration */
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return 2;
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}
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int __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
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u32 context_id)
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{
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u32 cpu = target_cpu & MPIDR_AFF0;
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if (target_cpu & ~MPIDR_AFF0)
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return ARM_PSCI_RET_INVAL;
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if (cpu >= STM32MP1_PSCI_NR_CPUS)
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return ARM_PSCI_RET_INVAL;
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if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
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return ARM_PSCI_RET_ALREADY_ON;
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/* store target PC and context id*/
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psci_save(cpu, pc, context_id);
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/* write entrypoint in backup RAM register */
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writel((u32)&psci_cpu_entry, TAMP_BACKUP_BRANCH_ADDRESS);
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psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING);
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/* write magic number in backup register */
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if (cpu == 0x01)
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writel(BOOT_API_A7_CORE1_MAGIC_NUMBER,
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TAMP_BACKUP_MAGIC_NUMBER);
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else
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writel(BOOT_API_A7_CORE0_MAGIC_NUMBER,
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TAMP_BACKUP_MAGIC_NUMBER);
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stm32mp_smp_kick_all_cpus();
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return ARM_PSCI_RET_SUCCESS;
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}
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int __secure psci_cpu_off(u32 function_id)
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{
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u32 cpu;
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cpu = psci_get_cpu_id();
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psci_cpu_off_common();
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psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
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/* reset core: wfi is managed by BootRom */
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if (cpu == 0x01)
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writel(RCC_MP_GRSTCSETR_MPUP1RST, RCC_MP_GRSTCSETR);
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else
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writel(RCC_MP_GRSTCSETR_MPUP0RST, RCC_MP_GRSTCSETR);
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/* just waiting reset */
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while (1)
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wfi();
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}
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void __secure psci_system_reset(u32 function_id)
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{
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/* System reset */
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writel(RCC_MP_GRSTCSETR_MPSYSRST, RCC_MP_GRSTCSETR);
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/* just waiting reset */
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while (1)
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wfi();
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}
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void __secure psci_system_off(u32 function_id)
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{
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/* System Off is not managed, waiting user power off
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* TODO: handle I2C write in PMIC Main Control register bit 0 = SWOFF
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*/
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while (1)
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wfi();
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}
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